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From: Bharat Kumar Gogada <bharatku@xilinx.com>
To: "lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"bhelgaas@google.com" <bhelgaas@google.com>,
	Ravikiran Gummaluri <rgummal@xilinx.com>,
	"maz@kernel.org" <maz@kernel.org>
Subject: RE: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
Date: Fri, 6 Mar 2020 11:45:47 +0000	[thread overview]
Message-ID: <MN2PR02MB6336BBFDCB07F424C36742B0A5E30@MN2PR02MB6336.namprd02.prod.outlook.com> (raw)
In-Reply-To: <20200306111620.GA10297@e121166-lin.cambridge.arm.com>

> From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Sent: Friday, March 6, 2020 4:46 PM
> To: Bharat Kumar Gogada <bharatku@xilinx.com>
> Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org;
> bhelgaas@google.com; Ravikiran Gummaluri <rgummal@xilinx.com>;
> maz@kernel.org
> Subject: Re: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver
> 
> On Fri, Feb 28, 2020 at 12:48:48PM +0000, Bharat Kumar Gogada wrote:
> > > Subject: Re: [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root
> > > Port driver
> > >
> > > [+MarcZ, FHI]
> > >
> > > On Tue, Feb 25, 2020 at 02:39:56PM +0000, Bharat Kumar Gogada wrote:
> > >
> > > [...]
> > >
> > > > > > +/* ECAM definitions */
> > > > > > +#define ECAM_BUS_NUM_SHIFT		20
> > > > > > +#define ECAM_DEV_NUM_SHIFT		12
> > > > >
> > > > > You don't need these ECAM_* defines, you can use
> pci_generic_ecam_ops.
> > > > Does this need separate ranges region for ECAM space ?
> > > > We have ECAM and controller space in same region.
> > >
> > > You can create an ECAM window with pci_ecam_create where *cfgres
> > > represent the ECAM area, I don't get what you mean by "same region".
> > >
> > > Do you mean "contiguous" ? Or something else ?
> > Yes, contiguous; within ECAM region some space is for controller registers.
> 
> What does that mean ? I don't get it. Can you explain to me how this address
> space works please ?
> 
Hi Lorenzo,
		reg = <0x6 0x00000000 0x0 0x1000000>,
		      <0x0 0xFCA10000 0x0 0x1000>;
		reg-names = "cfg", "cpm_slcr";

In the above cfg region some region of it reserved for bridge registers and rest for ECAM 
address space transactions. The bridge registers are mapped at an unused offset in config space
of root port, when the offset hit it will access controller register space.

This region is already being mapped 
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
port->reg_base = devm_ioremap_resource(dev, res);

Does pci_ecam_create will work along with above API simultaneously ?

Regards,
Bharat 


  reply	other threads:[~2020-03-06 11:45 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-30 16:12 [PATCH v5 0/2] Adding support for Versal CPM as Root Port driver Bharat Kumar Gogada
2020-01-30 16:12 ` [PATCH v5 1/2] PCI: xilinx-cpm: Add device tree binding for Versal CPM host bridge Bharat Kumar Gogada
2020-01-30 16:12 ` [PATCH v5 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver Bharat Kumar Gogada
2020-02-17  4:54   ` Bharat Kumar Gogada
2020-02-17 23:55   ` Bjorn Helgaas
2020-02-24  9:14     ` Bharat Kumar Gogada
2020-02-25 11:30   ` Lorenzo Pieralisi
2020-02-25 11:40   ` Lorenzo Pieralisi
2020-02-25 14:39     ` Bharat Kumar Gogada
2020-02-28 10:44       ` Lorenzo Pieralisi
2020-02-28 12:48         ` Bharat Kumar Gogada
2020-03-06 11:16           ` Lorenzo Pieralisi
2020-03-06 11:45             ` Bharat Kumar Gogada [this message]
2020-03-06 15:12               ` Lorenzo Pieralisi
2020-03-09 11:27                 ` Bharat Kumar Gogada
2020-03-16  5:24         ` Bharat Kumar Gogada
2020-03-30  9:37           ` Bharat Kumar Gogada
2020-04-16  7:07             ` Bharat Kumar Gogada
2020-04-20  8:52               ` Lorenzo Pieralisi

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