[PATCH 0/5] Add MSI-X support for cadence EP driver

[PATCH 0/5] Add MSI-X support for cadence EP driver

[Alan Douglas]

Patch series made against Bjorn Helgaas's pci next branch.
It relies on Gustavo Pimentel's patch series adding MSI-X
support in the PCIe EP driver framework, and implements
MSI-X support for the cadence endpoint driver.
 - Use AXI region 0 for interrupt signalling
 - Write MSI and MSI-X with 32bit value rather than 16bit
 - Check for masking before sending MSI or MSI-X
 - Check link is up before sending IRQ
 - Use BAR5 for MSI-X vectors

Alan Douglas (5):
  PCI: cadence: Use AXI region 0 to signal interrupts from EP
  PCI: cadence: Write MSI data with 32bits
  PCI: cadence: Check whether MSI is masked before sending it
  PCI: cadence: Check link is up before sending IRQ from EP
  PCI: cadence: Add MSI-X capability to EP driver

 drivers/pci/controller/pcie-cadence-ep.c |  129 ++++++++++++++++++++++++++++--
 drivers/pci/controller/pcie-cadence.h    |    1 +
 2 files changed, 124 insertions(+), 6 deletions(-)

Re: [PATCH 0/5] Add MSI-X support for cadence EP driver

[Lorenzo Pieralisi]

Hi Alan,

On Mon, Jul 30, 2018 at 06:21:00PM +0100, Alan Douglas wrote:
> Patch series made against Bjorn Helgaas's pci next branch.

Always rebase patches on a fixed -rc (ie Bjorn and I are using
v4.18-rc1) and mention the dependency rather than rebasing the
series on pci-next please.

> It relies on Gustavo Pimentel's patch series adding MSI-X
> support in the PCIe EP driver framework, and implements
> MSI-X support for the cadence endpoint driver.
>  - Use AXI region 0 for interrupt signalling
>  - Write MSI and MSI-X with 32bit value rather than 16bit
>  - Check for masking before sending MSI or MSI-X
>  - Check link is up before sending IRQ

These first four are fixes or changes required before enabling
the last patch in the series ?

Reworded: does the current driver work without the first 4
patches applied ?

If they are fixes please mark them as such in the commit log.

Thanks,
Lorenzo

>  - Use BAR5 for MSI-X vectors
> 
> Alan Douglas (5):
>   PCI: cadence: Use AXI region 0 to signal interrupts from EP
>   PCI: cadence: Write MSI data with 32bits
>   PCI: cadence: Check whether MSI is masked before sending it
>   PCI: cadence: Check link is up before sending IRQ from EP
>   PCI: cadence: Add MSI-X capability to EP driver
> 
>  drivers/pci/controller/pcie-cadence-ep.c |  129 ++++++++++++++++++++++++++++--
>  drivers/pci/controller/pcie-cadence.h    |    1 +
>  2 files changed, 124 insertions(+), 6 deletions(-)
> 

RE: [PATCH 0/5] Add MSI-X support for cadence EP driver

[Alan Douglas]

T24gIDA4IEF1Z3VzdCAyMDE4IDE3OjM4LCBMb3JlbnpvIFBpZXJhbGlzaSB3cm90ZToNCj4gT24g
TW9uLCBKdWwgMzAsIDIwMTggYXQgMDY6MjE6MDBQTSArMDEwMCwgQWxhbiBEb3VnbGFzIHdyb3Rl
Og0KPiA+IFBhdGNoIHNlcmllcyBtYWRlIGFnYWluc3QgQmpvcm4gSGVsZ2FhcydzIHBjaSBuZXh0
IGJyYW5jaC4NCj4gDQo+IEFsd2F5cyByZWJhc2UgcGF0Y2hlcyBvbiBhIGZpeGVkIC1yYyAoaWUg
Qmpvcm4gYW5kIEkgYXJlIHVzaW5nDQo+IHY0LjE4LXJjMSkgYW5kIG1lbnRpb24gdGhlIGRlcGVu
ZGVuY3kgcmF0aGVyIHRoYW4gcmViYXNpbmcgdGhlDQo+IHNlcmllcyBvbiBwY2ktbmV4dCBwbGVh
c2UuDQo+IA0KT0ssIHdpbGwgZG8gdGhhdCBmb3IgdjENCg0KPiA+IEl0IHJlbGllcyBvbiBHdXN0
YXZvIFBpbWVudGVsJ3MgcGF0Y2ggc2VyaWVzIGFkZGluZyBNU0ktWA0KPiA+IHN1cHBvcnQgaW4g
dGhlIFBDSWUgRVAgZHJpdmVyIGZyYW1ld29yaywgYW5kIGltcGxlbWVudHMNCj4gPiBNU0ktWCBz
dXBwb3J0IGZvciB0aGUgY2FkZW5jZSBlbmRwb2ludCBkcml2ZXIuDQo+ID4gIC0gVXNlIEFYSSBy
ZWdpb24gMCBmb3IgaW50ZXJydXB0IHNpZ25hbGxpbmcNCj4gPiAgLSBXcml0ZSBNU0kgYW5kIE1T
SS1YIHdpdGggMzJiaXQgdmFsdWUgcmF0aGVyIHRoYW4gMTZiaXQNCj4gPiAgLSBDaGVjayBmb3Ig
bWFza2luZyBiZWZvcmUgc2VuZGluZyBNU0kgb3IgTVNJLVgNCj4gPiAgLSBDaGVjayBsaW5rIGlz
IHVwIGJlZm9yZSBzZW5kaW5nIElSUQ0KPiANCj4gVGhlc2UgZmlyc3QgZm91ciBhcmUgZml4ZXMg
b3IgY2hhbmdlcyByZXF1aXJlZCBiZWZvcmUgZW5hYmxpbmcNCj4gdGhlIGxhc3QgcGF0Y2ggaW4g
dGhlIHNlcmllcyA/DQo+IA0KPiBSZXdvcmRlZDogZG9lcyB0aGUgY3VycmVudCBkcml2ZXIgd29y
ayB3aXRob3V0IHRoZSBmaXJzdCA0DQo+IHBhdGNoZXMgYXBwbGllZCA/DQo+IA0KPiBJZiB0aGV5
IGFyZSBmaXhlcyBwbGVhc2UgbWFyayB0aGVtIGFzIHN1Y2ggaW4gdGhlIGNvbW1pdCBsb2cuDQo+
IA0KVGhlc2UgYXJlIGZpeGVzLCB3aWxsIG1hcmsgdGhlbSBhcyBzdWNoIGluIHRoZSBsb2csIGFu
ZCB3aWxsDQpzcGxpdCBwYXRjaGVzIHN1Y2ggdGhhdCB0aGV5IGNhbiBiZSBhcHBsaWVkIHdpdGhv
dXQgYWRkaW5nDQpNU0ktWCBzdXBwb3J0Lg0KDQpUaGFua3MgZm9yIHlvdXIgY29tbWVudHMsDQpB
bGFuDQo=