* [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform
@ 2022-11-10 10:33 Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 1/8] dt-bindings: PCI: qcom: Add sm8350 to bindings Dmitry Baryshkov
` (7 more replies)
0 siblings, 8 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 10:33 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree
SM8350 is one of the recent Qualcomm platforms which lacks PCIe support.
Use sm8450 PHY tables to add support for the PCIe hosts on Qualcomm SM8350 platform.
Note: the PCIe0 table is based on the lahaina-v2.1.dtsi file, so it
might work incorrectly on earlier SoC revisions.
Dependencies:
- phy/next (for PHY patches only)
Changes since v1:
- removed pipe/ref clocks from the PCI schema, they are unused now
- split the sm8450 tables commit into separate split & rename (Bjorn)
- cleaned up the dtsi file, removing 'power-domain-names' and fixing
gpio proprety names.
Dmitry Baryshkov (8):
dt-bindings: PCI: qcom: Add sm8350 to bindings
dt-bindings: phy: qcom,qmp-pcie: add sm8350 bindings
PCI: qcom: Add support for SM8350
phy: qcom-qmp-pcie: split sm8450 gen3 PHY config tables
phy: qcom-qmp-pcie: rename the sm8450 gen3 PHY config tables
phy: qcom-qmp-pcie: add support for sm8350 platform
arm64: dts: qcom: sm8350: add PCIe devices
arm64: dts: qcom: sm8350-hdk: enable PCIe devices
.../devicetree/bindings/pci/qcom,pcie.yaml | 46 ++++
.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 22 ++
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 16 ++
arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 +++++++++++++++++-
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 164 ++++++++++--
6 files changed, 477 insertions(+), 18 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 1/8] dt-bindings: PCI: qcom: Add sm8350 to bindings
2022-11-10 10:33 [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform Dmitry Baryshkov
@ 2022-11-10 10:33 ` Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 2/8] dt-bindings: phy: qcom,qmp-pcie: add sm8350 bindings Dmitry Baryshkov
` (6 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 10:33 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree
Add bindings for two PCIe hosts on SM8350 platform. The only difference
between them is in the aggre0 clock, which warrants the oneOf clause for
the clocks properties.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 54f07852d279..502c15f7dd96 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -32,6 +32,7 @@ properties:
- qcom,pcie-sdm845
- qcom,pcie-sm8150
- qcom,pcie-sm8250
+ - qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
- qcom,pcie-ipq6018
@@ -185,6 +186,7 @@ allOf:
- qcom,pcie-sc8180x
- qcom,pcie-sc8280xp
- qcom,pcie-sm8250
+ - qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
then:
@@ -540,6 +542,49 @@ allOf:
items:
- const: pci # PCIe core reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sm8350
+ then:
+ oneOf:
+ # Unfortunately the "optional" aggre0 clock is used in the middle of the list
+ - properties:
+ clocks:
+ maxItems: 9
+ clock-names:
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre0 # Aggre NoC PCIe0 AXI clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+ - properties:
+ clocks:
+ maxItems: 8
+ clock-names:
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: tbu # PCIe TBU clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: aggre1 # Aggre NoC PCIe1 AXI clock
+ properties:
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
- if:
properties:
compatible:
@@ -670,6 +715,7 @@ allOf:
- qcom,pcie-sdm845
- qcom,pcie-sm8150
- qcom,pcie-sm8250
+ - qcom,pcie-sm8350
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
then:
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 2/8] dt-bindings: phy: qcom,qmp-pcie: add sm8350 bindings
2022-11-10 10:33 [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 1/8] dt-bindings: PCI: qcom: Add sm8350 to bindings Dmitry Baryshkov
@ 2022-11-10 10:33 ` Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 3/8] PCI: qcom: Add support for SM8350 Dmitry Baryshkov
` (5 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 10:33 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree, Rob Herring
Add bindings for the PCIe QMP PHYs found on SM8350.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
index 80aa8d2507fb..8a85318d9c92 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml
@@ -19,15 +19,18 @@ properties:
- qcom,sc8280xp-qmp-gen3x1-pcie-phy
- qcom,sc8280xp-qmp-gen3x2-pcie-phy
- qcom,sc8280xp-qmp-gen3x4-pcie-phy
+ - qcom,sm8350-qmp-gen3x1-pcie-phy
reg:
minItems: 1
maxItems: 2
clocks:
+ minItems: 5
maxItems: 6
clock-names:
+ minItems: 5
items:
- const: aux
- const: cfg_ahb
@@ -104,6 +107,25 @@ allOf:
reg:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8350-qmp-gen3x1-pcie-phy
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ maxItems: 5
+ else:
+ properties:
+ clocks:
+ minItems: 6
+ clock-names:
+ minItems: 6
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 3/8] PCI: qcom: Add support for SM8350
2022-11-10 10:33 [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 1/8] dt-bindings: PCI: qcom: Add sm8350 to bindings Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 2/8] dt-bindings: phy: qcom,qmp-pcie: add sm8350 bindings Dmitry Baryshkov
@ 2022-11-10 10:33 ` Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 4/8] phy: qcom-qmp-pcie: split sm8450 gen3 PHY config tables Dmitry Baryshkov
` (4 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 10:33 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree
Add support for the PCIe host on Qualcomm SM8350 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 7db94a22238d..3404c737afba 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1750,6 +1750,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
{ .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
+ { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
{ }
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 4/8] phy: qcom-qmp-pcie: split sm8450 gen3 PHY config tables
2022-11-10 10:33 [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform Dmitry Baryshkov
` (2 preceding siblings ...)
2022-11-10 10:33 ` [PATCH v2 3/8] PCI: qcom: Add support for SM8350 Dmitry Baryshkov
@ 2022-11-10 10:33 ` Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 5/8] phy: qcom-qmp-pcie: rename the " Dmitry Baryshkov
` (3 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 10:33 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree
SM8350 PHY config tables are mostly the same as SM8450 gen3 PHY config
tables. Split these tables to be used by SM8350 config.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 26 ++++++++++++++++++------
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 47cccc4b35b2..d9f8dffbe1da 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1252,7 +1252,6 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
- QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
@@ -1263,6 +1262,10 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
};
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
+};
+
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
@@ -1274,8 +1277,6 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
@@ -1283,14 +1284,19 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
- QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
- QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
- QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
+};
+
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
@@ -2030,6 +2036,14 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
},
+
+ .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
+ .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
+ .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
+ .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
+ },
+
.clk_list = sdm845_pciephy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
.reset_list = sdm845_pciephy_reset_l,
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 5/8] phy: qcom-qmp-pcie: rename the sm8450 gen3 PHY config tables
2022-11-10 10:33 [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform Dmitry Baryshkov
` (3 preceding siblings ...)
2022-11-10 10:33 ` [PATCH v2 4/8] phy: qcom-qmp-pcie: split sm8450 gen3 PHY config tables Dmitry Baryshkov
@ 2022-11-10 10:33 ` Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 6/8] phy: qcom-qmp-pcie: add support for sm8350 platform Dmitry Baryshkov
` (2 subsequent siblings)
7 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 10:33 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree
SM8350 PHY config tables are mostly the same as SM8450 gen3 PHY config
tables. Rename generic tables to remove x1 suffix.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index d9f8dffbe1da..4a55b2439952 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1218,7 +1218,7 @@ static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
};
-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_serdes_tbl[] = {
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
@@ -1274,7 +1274,7 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
};
-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rx_tbl[] = {
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
@@ -1302,7 +1302,7 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
};
-static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_tbl[] = {
+static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
@@ -2025,14 +2025,14 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
.lanes = 1,
.tbls = {
- .serdes = sm8450_qmp_gen3x1_pcie_serdes_tbl,
- .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_serdes_tbl),
+ .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
.tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
.tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
- .rx = sm8450_qmp_gen3x1_pcie_rx_tbl,
- .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rx_tbl),
- .pcs = sm8450_qmp_gen3x1_pcie_pcs_tbl,
- .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_tbl),
+ .rx = sm8450_qmp_gen3_pcie_rx_tbl,
+ .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
+ .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
},
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 6/8] phy: qcom-qmp-pcie: add support for sm8350 platform
2022-11-10 10:33 [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform Dmitry Baryshkov
` (4 preceding siblings ...)
2022-11-10 10:33 ` [PATCH v2 5/8] phy: qcom-qmp-pcie: rename the " Dmitry Baryshkov
@ 2022-11-10 10:33 ` Dmitry Baryshkov
2022-11-10 18:24 ` Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable " Dmitry Baryshkov
7 siblings, 1 reply; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 10:33 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm
SM8350 platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 120 ++++++++++++++++++++++-
1 file changed, 119 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 4a55b2439952..a1f5d31d161b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1315,6 +1315,40 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
};
+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
+};
+
+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
+};
+
+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
+ QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
+ QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
+};
+
static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
@@ -2021,6 +2055,80 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
.phy_status = PHYSTATUS_4_20,
};
+static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
+ .lanes = 1,
+
+ .offsets = &qmp_pcie_offsets_v5,
+
+ .tables = {
+ .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
+ .tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
+ .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
+ .rx = sm8450_qmp_gen3_pcie_rx_tbl,
+ .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
+ .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
+ .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
+ },
+
+ .tables_rc = &(const struct qmp_phy_cfg_tables) {
+ .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
+ .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
+ .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
+ },
+
+ .clk_list = sc8280xp_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sm8250_pcie_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+};
+
+static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
+ .lanes = 2,
+
+ .offsets = &qmp_pcie_offsets_v5,
+
+ .tables = {
+ .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
+ .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
+ .tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
+ .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
+ .rx = sm8450_qmp_gen3_pcie_rx_tbl,
+ .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
+ .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
+ .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
+ .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
+ },
+
+ .tables_rc = &(const struct qmp_phy_cfg_tables) {
+ .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
+ .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
+ .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
+ .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
+ },
+
+ .clk_list = sc8280xp_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
+ .reset_list = sdm845_pciephy_reset_l,
+ .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = sm8250_pcie_regs_layout,
+
+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
+ .phy_status = PHYSTATUS,
+};
+
static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
.lanes = 1,
@@ -2617,7 +2725,11 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
qmp->pipe_clks[0].id = "pipe";
qmp->pipe_clks[1].id = "pipediv2";
- ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks);
+ ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
+ if (ret)
+ return ret;
+
+ ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
if (ret)
return ret;
@@ -2737,6 +2849,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
}, {
.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
.data = &sm8250_qmp_gen3x2_pciephy_cfg,
+ }, {
+ .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
+ .data = &sm8350_qmp_gen3x1_pciephy_cfg,
+ }, {
+ .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
+ .data = &sm8350_qmp_gen3x2_pciephy_cfg,
}, {
.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
.data = &sm8450_qmp_gen3x1_pciephy_cfg,
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices
2022-11-10 10:33 [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform Dmitry Baryshkov
` (5 preceding siblings ...)
2022-11-10 10:33 ` [PATCH v2 6/8] phy: qcom-qmp-pcie: add support for sm8350 platform Dmitry Baryshkov
@ 2022-11-10 10:33 ` Dmitry Baryshkov
2022-11-10 10:53 ` Johan Hovold
2022-11-10 10:33 ` [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable " Dmitry Baryshkov
7 siblings, 1 reply; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 10:33 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree
Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 ++++++++++++++++++++++++++-
1 file changed, 244 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a86d9ea93b9d..90a26f406bf3 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -656,8 +656,8 @@ gcc: clock-controller@100000 {
"usb3_uni_phy_sec_gcc_usb30_pipe_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
- <0>,
- <0>,
+ <&pcie0_phy>,
+ <&pcie1_phy>,
<0>,
<0>,
<0>,
@@ -1582,6 +1582,202 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ pcie0: pci@1c00000 {
+ compatible = "qcom,pcie-sm8350";
+ reg = <0 0x01c00000 0 0x3000>,
+ <0 0x60000000 0 0xf1d>,
+ <0 0x60000f20 0 0xa8>,
+ <0 0x60001000 0 0x1000>,
+ <0 0x60100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3",
+ "msi4", "msi5", "msi6", "msi7";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu",
+ "aggre0",
+ "aggre1";
+
+ iommus = <&apps_smmu 0x1c00 0x7f>;
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ resets = <&gcc GCC_PCIE_0_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_0_GDSC>;
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+
+ status = "disabled";
+ };
+
+ pcie0_phy: phy@1c06000 {
+ compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
+ reg = <0 0x01c06000 0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_0_CLKREF_EN>,
+ <&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_0_PIPE_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
+
+ resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie1: pci@1c08000 {
+ compatible = "qcom,pcie-sm8350";
+ reg = <0 0x01c08000 0 0x3000>,
+ <0 0x40000000 0 0xf1d>,
+ <0 0x40000f20 0 0xa8>,
+ <0 0x40001000 0 0x1000>,
+ <0 0x40100000 0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>;
+
+ interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "tbu",
+ "ddrss_sf_tbu",
+ "aggre1";
+
+ iommus = <&apps_smmu 0x1c80 0x7f>;
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>;
+
+ resets = <&gcc GCC_PCIE_1_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_1_GDSC>;
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@1c0f000 {
+ compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
+ reg = <0 0x01c0e000 0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
+ <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_1_CLKREF_EN>,
+ <&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_1_PIPE_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
+
+ resets = <&gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
lpass_ag_noc: interconnect@3c40000 {
compatible = "qcom,sm8350-lpass-ag-noc";
reg = <0 0x03c40000 0 0xf080>;
@@ -1761,6 +1957,52 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 204>;
wakeup-parent = <&pdc>;
+ pcie0_default_state: pcie0-default-state {
+ perst-pins {
+ pins = "gpio94";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio95";
+ function = "pcie0_clkreqn";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio96";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_state: pcie1-default-state {
+ perst-pins {
+ pins = "gpio97";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq-pins {
+ pins = "gpio98";
+ function = "pcie1_clkreqn";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake-pins {
+ pins = "gpio99";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup_uart3_default_state: qup-uart3-default-state {
rx-pins {
pins = "gpio18";
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable PCIe devices
2022-11-10 10:33 [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform Dmitry Baryshkov
` (6 preceding siblings ...)
2022-11-10 10:33 ` [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices Dmitry Baryshkov
@ 2022-11-10 10:33 ` Dmitry Baryshkov
2022-11-10 10:51 ` Johan Hovold
7 siblings, 1 reply; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 10:33 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree
Enable PCIe0 and PCIe1 hosts found on SM8350 HDK board.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
index 0fcf5bd88fc7..58a9dc7705a5 100644
--- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
@@ -222,6 +222,22 @@ &mpss {
firmware-name = "qcom/sm8350/modem.mbn";
};
+&pcie0 {
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie1_phy {
+ status = "okay";
+};
+
&qupv3_id_0 {
status = "okay";
};
--
2.35.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable PCIe devices
2022-11-10 10:33 ` [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable " Dmitry Baryshkov
@ 2022-11-10 10:51 ` Johan Hovold
2022-11-10 13:31 ` Dmitry Baryshkov
0 siblings, 1 reply; 16+ messages in thread
From: Johan Hovold @ 2022-11-10 10:51 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I, Philipp Zabel, linux-arm-msm,
linux-pci, linux-phy, devicetree
On Thu, Nov 10, 2022 at 01:33:45PM +0300, Dmitry Baryshkov wrote:
> Enable PCIe0 and PCIe1 hosts found on SM8350 HDK board.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> index 0fcf5bd88fc7..58a9dc7705a5 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
> @@ -222,6 +222,22 @@ &mpss {
> firmware-name = "qcom/sm8350/modem.mbn";
> };
>
> +&pcie0 {
> + status = "okay";
> +};
> +
> +&pcie0_phy {
> + status = "okay";
> +};
Looks like the required regulators are missing from the PHY nodes.
Johan
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices
2022-11-10 10:33 ` [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices Dmitry Baryshkov
@ 2022-11-10 10:53 ` Johan Hovold
2022-11-10 14:20 ` Dmitry Baryshkov
0 siblings, 1 reply; 16+ messages in thread
From: Johan Hovold @ 2022-11-10 10:53 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I, Philipp Zabel, linux-arm-msm,
linux-pci, linux-phy, devicetree
On Thu, Nov 10, 2022 at 01:33:44PM +0300, Dmitry Baryshkov wrote:
> Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
> platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 ++++++++++++++++++++++++++-
> 1 file changed, 244 insertions(+), 2 deletions(-)
> @@ -1761,6 +1957,52 @@ tlmm: pinctrl@f100000 {
> gpio-ranges = <&tlmm 0 0 204>;
> wakeup-parent = <&pdc>;
>
> + pcie0_default_state: pcie0-default-state {
> + perst-pins {
> + pins = "gpio94";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + clkreq-pins {
> + pins = "gpio95";
> + function = "pcie0_clkreqn";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + wake-pins {
> + pins = "gpio96";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
The pinconfig should go in the board file.
Johan
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable PCIe devices
2022-11-10 10:51 ` Johan Hovold
@ 2022-11-10 13:31 ` Dmitry Baryshkov
0 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 13:31 UTC (permalink / raw)
To: Johan Hovold
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I, Philipp Zabel, linux-arm-msm,
linux-pci, linux-phy, devicetree
On 10/11/2022 13:51, Johan Hovold wrote:
> On Thu, Nov 10, 2022 at 01:33:45PM +0300, Dmitry Baryshkov wrote:
>> Enable PCIe0 and PCIe1 hosts found on SM8350 HDK board.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 16 ++++++++++++++++
>> 1 file changed, 16 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
>> index 0fcf5bd88fc7..58a9dc7705a5 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts
>> @@ -222,6 +222,22 @@ &mpss {
>> firmware-name = "qcom/sm8350/modem.mbn";
>> };
>>
>> +&pcie0 {
>> + status = "okay";
>> +};
>> +
>> +&pcie0_phy {
>> + status = "okay";
>> +};
>
> Looks like the required regulators are missing from the PHY nodes.
Ack, nice catch!
>
> Johan
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices
2022-11-10 10:53 ` Johan Hovold
@ 2022-11-10 14:20 ` Dmitry Baryshkov
2022-11-16 14:26 ` Johan Hovold
0 siblings, 1 reply; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 14:20 UTC (permalink / raw)
To: Johan Hovold
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I, Philipp Zabel, linux-arm-msm,
linux-pci, linux-phy, devicetree
On 10/11/2022 13:53, Johan Hovold wrote:
> On Thu, Nov 10, 2022 at 01:33:44PM +0300, Dmitry Baryshkov wrote:
>> Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
>> platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 ++++++++++++++++++++++++++-
>> 1 file changed, 244 insertions(+), 2 deletions(-)
>
>> @@ -1761,6 +1957,52 @@ tlmm: pinctrl@f100000 {
>> gpio-ranges = <&tlmm 0 0 204>;
>> wakeup-parent = <&pdc>;
>>
>> + pcie0_default_state: pcie0-default-state {
>> + perst-pins {
>> + pins = "gpio94";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-down;
>> + };
>> +
>> + clkreq-pins {
>> + pins = "gpio95";
>> + function = "pcie0_clkreqn";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> +
>> + wake-pins {
>> + pins = "gpio96";
>> + function = "gpio";
>> + drive-strength = <2>;
>> + bias-pull-up;
>> + };
>> + };
>
> The pinconfig should go in the board file.
Usually yes. However for the PCIe we usually put them into the main
.dtsi. See sm8[124]50.dtsi.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 6/8] phy: qcom-qmp-pcie: add support for sm8350 platform
2022-11-10 10:33 ` [PATCH v2 6/8] phy: qcom-qmp-pcie: add support for sm8350 platform Dmitry Baryshkov
@ 2022-11-10 18:24 ` Dmitry Baryshkov
0 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 18:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I
Cc: Philipp Zabel, Johan Hovold, linux-arm-msm, linux-pci, linux-phy,
devicetree
On 10/11/2022 13:33, Dmitry Baryshkov wrote:
> Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm
> SM8350 platform.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 120 ++++++++++++++++++++++-
> 1 file changed, 119 insertions(+), 1 deletion(-)
Argh, this will not compile against the current phy/next. I'll have to
send v3.
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 4a55b2439952..a1f5d31d161b 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices
2022-11-10 14:20 ` Dmitry Baryshkov
@ 2022-11-16 14:26 ` Johan Hovold
2022-11-18 22:22 ` Dmitry Baryshkov
0 siblings, 1 reply; 16+ messages in thread
From: Johan Hovold @ 2022-11-16 14:26 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I, Philipp Zabel, linux-arm-msm,
linux-pci, linux-phy, devicetree
On Thu, Nov 10, 2022 at 05:20:11PM +0300, Dmitry Baryshkov wrote:
> On 10/11/2022 13:53, Johan Hovold wrote:
> > On Thu, Nov 10, 2022 at 01:33:44PM +0300, Dmitry Baryshkov wrote:
> >> Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
> >> platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.
> >>
> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >> ---
> >> arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 ++++++++++++++++++++++++++-
> >> 1 file changed, 244 insertions(+), 2 deletions(-)
> >
> >> @@ -1761,6 +1957,52 @@ tlmm: pinctrl@f100000 {
> >> gpio-ranges = <&tlmm 0 0 204>;
> >> wakeup-parent = <&pdc>;
> >>
> >> + pcie0_default_state: pcie0-default-state {
> >> + perst-pins {
> >> + pins = "gpio94";
> >> + function = "gpio";
> >> + drive-strength = <2>;
> >> + bias-pull-down;
> >> + };
> >> +
> >> + clkreq-pins {
> >> + pins = "gpio95";
> >> + function = "pcie0_clkreqn";
> >> + drive-strength = <2>;
> >> + bias-pull-up;
> >> + };
> >> +
> >> + wake-pins {
> >> + pins = "gpio96";
> >> + function = "gpio";
> >> + drive-strength = <2>;
> >> + bias-pull-up;
> >> + };
> >> + };
> >
> > The pinconfig should go in the board file.
>
> Usually yes. However for the PCIe we usually put them into the main
> .dtsi. See sm8[124]50.dtsi.
Yeah, I noticed that too and had this discussion with Bjorn for
sc8280xp some months ago. Even if you may save a few lines by providing
defaults in a dtsi, the pin configuration is board specific and belongs
in the dts.
Also note that 'perst' and 'wake' above could in principle be connected
to other GPIOs on different boards.
Johan
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices
2022-11-16 14:26 ` Johan Hovold
@ 2022-11-18 22:22 ` Dmitry Baryshkov
0 siblings, 0 replies; 16+ messages in thread
From: Dmitry Baryshkov @ 2022-11-18 22:22 UTC (permalink / raw)
To: Johan Hovold
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Jingoo Han, Gustavo Pimentel,
Lorenzo Pieralisi, Krzysztof Wilczyński, Bjorn Helgaas,
Vinod Koul, Kishon Vijay Abraham I, Philipp Zabel, linux-arm-msm,
linux-pci, linux-phy, devicetree
On 16/11/2022 16:26, Johan Hovold wrote:
> On Thu, Nov 10, 2022 at 05:20:11PM +0300, Dmitry Baryshkov wrote:
>> On 10/11/2022 13:53, Johan Hovold wrote:
>>> On Thu, Nov 10, 2022 at 01:33:44PM +0300, Dmitry Baryshkov wrote:
>>>> Add PCIe0 and PCIe1 (and corresponding PHY) devices found on SM8350
>>>> platform. The PCIe0 is a 1-lane Gen3 host, PCIe1 is a 2-lane Gen3 host.
>>>>
>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm8350.dtsi | 246 ++++++++++++++++++++++++++-
>>>> 1 file changed, 244 insertions(+), 2 deletions(-)
>>>
>>>> @@ -1761,6 +1957,52 @@ tlmm: pinctrl@f100000 {
>>>> gpio-ranges = <&tlmm 0 0 204>;
>>>> wakeup-parent = <&pdc>;
>>>>
>>>> + pcie0_default_state: pcie0-default-state {
>>>> + perst-pins {
>>>> + pins = "gpio94";
>>>> + function = "gpio";
>>>> + drive-strength = <2>;
>>>> + bias-pull-down;
>>>> + };
>>>> +
>>>> + clkreq-pins {
>>>> + pins = "gpio95";
>>>> + function = "pcie0_clkreqn";
>>>> + drive-strength = <2>;
>>>> + bias-pull-up;
>>>> + };
>>>> +
>>>> + wake-pins {
>>>> + pins = "gpio96";
>>>> + function = "gpio";
>>>> + drive-strength = <2>;
>>>> + bias-pull-up;
>>>> + };
>>>> + };
>>>
>>> The pinconfig should go in the board file.
>>
>> Usually yes. However for the PCIe we usually put them into the main
>> .dtsi. See sm8[124]50.dtsi.
>
> Yeah, I noticed that too and had this discussion with Bjorn for
> sc8280xp some months ago. Even if you may save a few lines by providing
> defaults in a dtsi, the pin configuration is board specific and belongs
> in the dts.
I see that you've ended up with no pin configuration at all in
sc8280xp.dtsi. I must admit, this is an interesting approach. However I
fear that this might increase c&p amount. Let's see how it goes in the
long term.
>
> Also note that 'perst' and 'wake' above could in principle be connected
> to other GPIOs on different boards.
Yes. Do we see that in wild? No.
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-11-18 22:23 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-10 10:33 [PATCH v2 0/8] PCI/phy: Add support for PCI on sm8350 platform Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 1/8] dt-bindings: PCI: qcom: Add sm8350 to bindings Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 2/8] dt-bindings: phy: qcom,qmp-pcie: add sm8350 bindings Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 3/8] PCI: qcom: Add support for SM8350 Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 4/8] phy: qcom-qmp-pcie: split sm8450 gen3 PHY config tables Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 5/8] phy: qcom-qmp-pcie: rename the " Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 6/8] phy: qcom-qmp-pcie: add support for sm8350 platform Dmitry Baryshkov
2022-11-10 18:24 ` Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 7/8] arm64: dts: qcom: sm8350: add PCIe devices Dmitry Baryshkov
2022-11-10 10:53 ` Johan Hovold
2022-11-10 14:20 ` Dmitry Baryshkov
2022-11-16 14:26 ` Johan Hovold
2022-11-18 22:22 ` Dmitry Baryshkov
2022-11-10 10:33 ` [PATCH v2 8/8] arm64: dts: qcom: sm8350-hdk: enable " Dmitry Baryshkov
2022-11-10 10:51 ` Johan Hovold
2022-11-10 13:31 ` Dmitry Baryshkov
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