* [PATCH V3 01/11] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-07-05 6:14 ` Vinod Koul
2022-06-29 6:04 ` [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema Vidya Sagar
` (9 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue
module instantiated once for each PCIe lane between Synopsys DesignWare
core based PCIe IP and Universal PHY block.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
V3:
* Added 'Reviewed-by: Rob Herring <robh@kernel.org>'
V2:
* Addressed review comments from Rob and Raul
* Ran 'dt_binding_check' and 'dtbs_check' on this change
.../bindings/phy/phy-tegra194-p2u.yaml | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
index 9a89d05efbda..4dc5205d893b 100644
--- a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.yaml
@@ -4,7 +4,7 @@
$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: NVIDIA Tegra194 P2U binding
+title: NVIDIA Tegra194 & Tegra234 P2U binding
maintainers:
- Thierry Reding <treding@nvidia.com>
@@ -12,13 +12,17 @@ maintainers:
description: >
Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
Speed) each interfacing with 12 and 8 P2U instances respectively.
+ Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
+ each interfacing with 8, 8 and 8 P2U instances respectively.
A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
- interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
- lane.
+ interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
+ PCIe lane.
properties:
compatible:
- const: nvidia,tegra194-p2u
+ enum:
+ - nvidia,tegra194-p2u
+ - nvidia,tegra234-p2u
reg:
maxItems: 1
@@ -28,6 +32,11 @@ properties:
items:
- const: ctl
+ nvidia,skip-sz-protect-en:
+ description: Should be present if two PCIe retimers are present between
+ the root port and its immediate downstream device.
+ type: boolean
+
'#phy-cells':
const: 0
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH V3 01/11] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block
2022-06-29 6:04 ` [PATCH V3 01/11] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block Vidya Sagar
@ 2022-07-05 6:14 ` Vinod Koul
0 siblings, 0 replies; 27+ messages in thread
From: Vinod Koul @ 2022-07-05 6:14 UTC (permalink / raw)
To: Vidya Sagar
Cc: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh,
kishon, kw, krzk, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv
On 29-06-22, 11:34, Vidya Sagar wrote:
> Add support for Tegra234 P2U (PIPE to UPHY) module block which is a glue
> module instantiated once for each PCIe lane between Synopsys DesignWare
> core based PCIe IP and Universal PHY block.
Applied, thanks
>
--
~Vinod
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-06-29 6:04 ` [PATCH V3 01/11] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-06-29 6:29 ` Krzysztof Kozlowski
2022-06-30 21:04 ` Rob Herring
2022-06-29 6:04 ` [PATCH V3 03/11] dt-bindings: PCI: tegra234: Add schema for tegra234 rootport mode Vidya Sagar
` (8 subsequent siblings)
10 siblings, 2 replies; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv, Thierry Reding
From: Thierry Reding <treding@nvidia.com>
Convert the Tegra194 PCIe bindings from the free-form text format to
json-schema.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
V3:
* New patch in this series. Added as part of addressing Rob's review
comment to convert the existing .txt file to .yaml schema
.../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 239 ++++++++++++++++
.../bindings/pci/nvidia,tegra194-pcie.txt | 245 -----------------
.../bindings/pci/nvidia,tegra194-pcie.yaml | 254 ++++++++++++++++++
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
4 files changed, 494 insertions(+), 246 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
new file mode 100644
index 000000000000..4f7cb7fe378e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
@@ -0,0 +1,239 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra194 (and later) PCIe endpoint controller (Synopsys DesignWare Core based)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Vidya Sagar <vidyas@nvidia.com>
+
+description: |
+ This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
+ properties defined in snps,dw-pcie-ep.yaml. Some of the controller instances are dual mode where
+ in they can work either in root port mode or endpoint mode but one at a time.
+
+ On Tegra194, controllers C0, C4 and C5 support endpoint mode.
+
+ Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the
+ endpoint mode because of the way the platform is designed.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra194-pcie-ep
+
+ reg:
+ items:
+ - description: controller's application logic registers
+ - description: iATU and DMA registers. This is where the iATU (internal Address Translation
+ Unit) registers of the PCIe core are made available for software access.
+ - description: The aperture where the root port's own configuration registers are available.
+ - description: Aperture used to map the remote root-complex' address space.
+
+ reg-names:
+ items:
+ - const: appl
+ - const: atu_dma
+ - const: dbi
+ - const: addr_space
+
+ interrupts:
+ items:
+ - description: controller interrupt
+
+ interrupt-names:
+ items:
+ - const: intr
+
+ clocks:
+ items:
+ - description: module clock
+
+ clock-names:
+ items:
+ - const: core
+
+ resets:
+ items:
+ - description: APB bus interface reset
+ - description: module reset
+
+ reset-names:
+ items:
+ - const: apb
+ - const: core
+
+ reset-gpios:
+ description: Must contain a phandle to a GPIO controller followed by GPIO that is being used as
+ PERST input signal. Please refer to pci.txt document.
+
+ phys:
+ minItems: 1
+ maxItems: 16
+
+ phy-names:
+ minItems: 1
+ maxItems: 16
+ items:
+ pattern: "^p2u-[0-9]+$"
+
+ power-domains:
+ description: |
+ A phandle to the node that controls power to the respective PCIe controller and a specifier
+ name for the PCIe controller. Following are the specifiers for the different PCIe
+ controllers:
+
+ - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
+ - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
+ - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
+ - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
+ - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
+ - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
+
+ these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
+
+ interconnects:
+ items:
+ - description: memory read client
+ - description: memory write client
+
+ interconnect-names:
+ items:
+ - const: dma-mem # read
+ - const: write
+
+ dma-coherent: true
+
+ num-ib-windows:
+ description: number of inbound address translation windows
+ maxItems: 1
+ deprecated: true
+
+ num-ob-windows:
+ description: number of outbound address translation windows
+ maxItems: 1
+ deprecated: true
+
+ nvidia,bpmp:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
+ are the controller IDs for each controller:
+
+ 0: C0
+ 1: C1
+ 2: C2
+ 3: C3
+ 4: C4
+ 5: C5
+ items:
+ - items:
+ - minimum: 0
+ maximum: 0xffffffff
+ - enum: [ 0, 1, 2, 3, 4, 5 ]
+
+ nvidia,aspm-cmrt-us:
+ description: Common Mode Restore Time for proper operation of ASPM to be specified in
+ microseconds
+
+ nvidia,aspm-pwr-on-t-us:
+ description: Power On time for proper operation of ASPM to be specified in microseconds
+
+ nvidia,aspm-l0s-entrance-latency-us:
+ description: ASPM L0s entrance latency to be specified in microseconds
+
+ vddio-pex-ctl-supply:
+ description: A phandle to the regulator supply for PCIe side band signals.
+
+ nvidia,refclk-select-gpios:
+ description: Must contain a phandle to a GPIO controller followed by GPIO that is being used to
+ enable REFCLK to controller from host
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+allOf:
+ - $ref: "/schemas/pci/pci-ep.yaml#"
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - num-ib-windows
+ - num-ob-windows
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - reset-gpios
+ - num-lanes
+ - phys
+ - phy-names
+ - nvidia,bpmp
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra194-clock.h>
+ #include <dt-bindings/gpio/tegra194-gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/tegra194-powergate.h>
+ #include <dt-bindings/reset/tegra194-reset.h>
+
+ bus@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+ pcie-ep@141a0000 {
+ compatible = "nvidia,tegra194-pcie-ep";
+ reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "intr";
+
+ clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
+ <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
+ reset-names = "apb", "core";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkreq_c5_bi_dir_state>;
+
+ nvidia,bpmp = <&bpmp 5>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+ reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
+
+ nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
+ GPIO_ACTIVE_HIGH>;
+
+ num-lanes = <8>;
+ num-ib-windows = <2>;
+ num-ob-windows = <8>;
+
+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+ "p2u-5", "p2u-6", "p2u-7";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
deleted file mode 100644
index 8e4f9bfb316d..000000000000
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
+++ /dev/null
@@ -1,245 +0,0 @@
-NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
-
-This PCIe controller is based on the Synopsis Designware PCIe IP
-and thus inherits all the common properties defined in snps,dw-pcie.yaml and
-snps,dw-pcie-ep.yaml.
-Some of the controller instances are dual mode where in they can work either
-in root port mode or endpoint mode but one at a time.
-
-Required properties:
-- power-domains: A phandle to the node that controls power to the respective
- PCIe controller and a specifier name for the PCIe controller. Following are
- the specifiers for the different PCIe controllers
- TEGRA194_POWER_DOMAIN_PCIEX8B: C0
- TEGRA194_POWER_DOMAIN_PCIEX1A: C1
- TEGRA194_POWER_DOMAIN_PCIEX1A: C2
- TEGRA194_POWER_DOMAIN_PCIEX1A: C3
- TEGRA194_POWER_DOMAIN_PCIEX4A: C4
- TEGRA194_POWER_DOMAIN_PCIEX8A: C5
- these specifiers are defined in
- "include/dt-bindings/power/tegra194-powergate.h" file.
-- reg: A list of physical base address and length pairs for each set of
- controller registers. Must contain an entry for each entry in the reg-names
- property.
-- reg-names: Must include the following entries:
- "appl": Controller's application logic registers
- "config": As per the definition in snps,dw-pcie.yaml
- "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
- Translation Unit) registers of the PCIe core are made available
- for SW access.
- "dbi": The aperture where root port's own configuration registers are
- available
-- interrupts: A list of interrupt outputs of the controller. Must contain an
- entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
- "intr": The Tegra interrupt that is asserted for controller interrupts
-- clocks: Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - core
-- resets: Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - apb
- - core
-- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
-- phy-names: Must include an entry for each active lane.
- "p2u-N": where N ranges from 0 to one less than the total number of lanes
-- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
- by controller-id. Following are the controller ids for each controller.
- 0: C0
- 1: C1
- 2: C2
- 3: C3
- 4: C4
- 5: C5
-- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
-
-RC mode:
-- compatible: Tegra19x must contain "nvidia,tegra194-pcie"
-- device_type: Must be "pci" for RC mode
-- interrupt-names: Must include the following entries:
- "msi": The Tegra interrupt that is asserted when an MSI is received
-- bus-range: Range of bus numbers associated with this controller
-- #address-cells: Address representation for root ports (must be 3)
- - cell 0 specifies the bus and device numbers of the root port:
- [23:16]: bus number
- [15:11]: device number
- - cell 1 denotes the upper 32 address bits and should be 0
- - cell 2 contains the lower 32 address bits and is used to translate to the
- CPU address space
-- #size-cells: Size representation for root ports (must be 2)
-- ranges: Describes the translation of addresses for root ports and standard
- PCI regions. The entries must be 7 cells each, where the first three cells
- correspond to the address as described for the #address-cells property
- above, the fourth and fifth cells are for the physical CPU address to
- translate to and the sixth and seventh cells are as described for the
- #size-cells property above.
- - Entries setup the mapping for the standard I/O, memory and
- prefetchable PCI regions. The first cell determines the type of region
- that is setup:
- - 0x81000000: I/O memory region
- - 0x82000000: non-prefetchable memory region
- - 0xc2000000: prefetchable memory region
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-- #interrupt-cells: Size representation for interrupts (must be 1)
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
- Please refer to the standard PCI bus binding document for a more detailed
- explanation.
-
-EP mode:
-In Tegra194, Only controllers C0, C4 & C5 support EP mode.
-- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
-- reg-names: Must include the following entries:
- "addr_space": Used to map remote RC address space
-- reset-gpios: Must contain a phandle to a GPIO controller followed by
- GPIO that is being used as PERST input signal. Please refer to pci.txt
- document.
-
-Optional properties:
-- pinctrl-names: A list of pinctrl state names.
- It is mandatory for C5 controller and optional for other controllers.
- - "default": Configures PCIe I/O for proper operation.
-- pinctrl-0: phandle for the 'default' state of pin configuration.
- It is mandatory for C5 controller and optional for other controllers.
-- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
-- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
- improve performance when a platform is designed in such a way that it
- satisfies at least one of the following conditions thereby enabling root
- port to exchange optimum number of FC (Flow Control) credits with
- downstream devices
- 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
- 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
- a) speed is Gen-2 and MPS is 256B
- b) speed is >= Gen-3 with any MPS
-- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
- to be specified in microseconds
-- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
- specified in microseconds
-- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
- specified in microseconds
-
-RC mode:
-- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
- if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
- in p2972-0000 platform).
-- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
- if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
- in p2972-0000 platform).
-
-EP mode:
-- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
- followed by GPIO that is being used to enable REFCLK to controller from host
-
-NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
-operate in the endpoint mode because of the way the platform is designed.
-
-Examples:
-=========
-
-Tegra194 RC mode:
------------------
-
- pcie@14180000 {
- compatible = "nvidia,tegra194-pcie";
- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
- reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
- 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
- reg-names = "appl", "config", "atu_dma";
-
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- num-lanes = <8>;
- linux,pci-domain = <0>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
-
- clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
- clock-names = "core";
-
- resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
- <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
- reset-names = "apb", "core";
-
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
- interrupt-names = "intr", "msi";
-
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-
- nvidia,bpmp = <&bpmp 0>;
-
- supports-clkreq;
- nvidia,aspm-cmrt-us = <60>;
- nvidia,aspm-pwr-on-t-us = <20>;
- nvidia,aspm-l0s-entrance-latency-us = <3>;
-
- bus-range = <0x0 0xff>;
- ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
- 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
- 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
-
- vddio-pex-ctl-supply = <&vdd_1v8ao>;
- vpcie3v3-supply = <&vdd_3v3_pcie>;
- vpcie12v-supply = <&vdd_12v_pcie>;
-
- phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
- <&p2u_hsio_5>;
- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
- };
-
-Tegra194 EP mode:
------------------
-
- pcie-ep@141a0000 {
- compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
- power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
- reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
- 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
- 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
- 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
- reg-names = "appl", "atu_dma", "dbi", "addr_space";
-
- num-lanes = <8>;
- num-ib-windows = <2>;
- num-ob-windows = <8>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&clkreq_c5_bi_dir_state>;
-
- clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
- clock-names = "core";
-
- resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
- <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
- reset-names = "apb", "core";
-
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
- interrupt-names = "intr";
-
- nvidia,bpmp = <&bpmp 5>;
-
- nvidia,aspm-cmrt-us = <60>;
- nvidia,aspm-pwr-on-t-us = <20>;
- nvidia,aspm-l0s-entrance-latency-us = <3>;
-
- vddio-pex-ctl-supply = <&vdd_1v8ao>;
-
- reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
-
- nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
- GPIO_ACTIVE_HIGH>;
-
- phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
- <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
- <&p2u_nvhs_6>, <&p2u_nvhs_7>;
-
- phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
- "p2u-5", "p2u-6", "p2u-7";
- };
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
new file mode 100644
index 000000000000..4a49dddf33bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
@@ -0,0 +1,254 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
+
+maintainers:
+ - Thierry Reding <thierry.reding@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Vidya Sagar <vidyas@nvidia.com>
+
+description: |
+ This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
+ properties defined in snps,dw-pcie.yaml. Some of the controller instances are dual mode where in
+ they can work either in root port mode or endpoint mode but one at a time.
+
+ See nvidia,tegra194-pcie-ep.yaml for details on the endpoint mode device tree bindings.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra194-pcie
+
+ reg:
+ items:
+ - description: controller's application logic registers
+ - description: configuration registers
+ - description: iATU and DMA registers. This is where the iATU (internal Address Translation
+ Unit) registers of the PCIe core are made available for software access.
+ - description: The aperture where the root port's own configuration registers are available.
+
+ reg-names:
+ items:
+ - const: appl
+ - const: config
+ - const: atu_dma
+ - const: dbi
+
+ interrupts:
+ items:
+ - description: controller interrupt
+ - description: MSI interrupt
+
+ interrupt-names:
+ items:
+ - const: intr
+ - const: msi
+
+ clocks:
+ items:
+ - description: module clock
+
+ clock-names:
+ items:
+ - const: core
+
+ resets:
+ items:
+ - description: APB bus interface reset
+ - description: module reset
+
+ reset-names:
+ items:
+ - const: apb
+ - const: core
+
+ phys:
+ minItems: 1
+ maxItems: 16
+
+ phy-names:
+ minItems: 1
+ maxItems: 16
+ items:
+ pattern: "^p2u-[0-9]+$"
+
+ power-domains:
+ description: |
+ A phandle to the node that controls power to the respective PCIe controller and a specifier
+ name for the PCIe controller. Following are the specifiers for the different PCIe
+ controllers:
+
+ - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
+ - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
+ - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
+ - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
+ - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
+ - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
+
+ these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
+
+ interconnects:
+ items:
+ - description: memory read client
+ - description: memory write client
+
+ interconnect-names:
+ items:
+ - const: dma-mem # read
+ - const: write
+
+ dma-coherent: true
+
+ supports-clkreq:
+ description: see pci.txt for details
+
+ nvidia,bpmp:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
+ are the controller IDs for each controller:
+
+ 0: C0
+ 1: C1
+ 2: C2
+ 3: C3
+ 4: C4
+ 5: C5
+ items:
+ - items:
+ - minimum: 0
+ maximum: 0xffffffff
+ - enum: [ 0, 1, 2, 3, 4, 5 ]
+
+ nvidia,update-fc-fixup:
+ description: |
+ This is a boolean property and needs to be present to improve performance when a platform is
+ designed in such a way that it satisfies at least one of the following conditions thereby
+ enabling root port to exchange optimum number of FC (Flow Control) credits with downstream
+ devices:
+
+ 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
+ 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
+ a) speed is Gen-2 and MPS is 256B
+ b) speed is >= Gen-3 with any MPS
+
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ nvidia,aspm-cmrt-us:
+ description: Common Mode Restore Time for proper operation of ASPM to be specified in
+ microseconds
+
+ nvidia,aspm-pwr-on-t-us:
+ description: Power On time for proper operation of ASPM to be specified in microseconds
+
+ nvidia,aspm-l0s-entrance-latency-us:
+ description: ASPM L0s entrance latency to be specified in microseconds
+
+ vddio-pex-ctl-supply:
+ description: A phandle to the regulator supply for PCIe side band signals.
+
+ vpcie3v3-supply:
+ description: A phandle to the regulator node that supplies 3.3V to the slot if the platform has
+ one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
+
+ vpcie12v-supply:
+ description: A phandle to the regulator node that supplies 12V to the slot if the platform has
+ one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
+
+allOf:
+ - $ref: "/schemas/pci/pci-bus.yaml#"
+ - $ref: "/schemas/pci/snps,dw-pcie.yaml#"
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - interrupt-map
+ - interrupt-map-mask
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - bus-range
+ - ranges
+ - vddio-pex-ctl-supply
+ - num-lanes
+ - phys
+ - phy-names
+ - nvidia,bpmp
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra194-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/tegra194-powergate.h>
+ #include <dt-bindings/reset/tegra194-reset.h>
+
+ bus@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+ pcie@14180000 {
+ compatible = "nvidia,tegra194-pcie";
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
+ reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <8>;
+ linux,pci-domain = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
+
+ clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
+ <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 0>;
+
+ supports-clkreq;
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
+ <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
+ <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
+
+ vddio-pex-ctl-supply = <&vdd_1v8ao>;
+ vpcie3v3-supply = <&vdd_3v3_pcie>;
+ vpcie12v-supply = <&vdd_12v_pcie>;
+
+ phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
+ <&p2u_hsio_5>;
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
index c90e5e2d25f6..7e0bf941fbfe 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
@@ -35,7 +35,7 @@ properties:
maxItems: 5
items:
enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
- ulreg, smu, mpu, apb, phy ]
+ ulreg, smu, mpu, apb, phy, appl, atu_dma ]
num-lanes:
description: |
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-06-29 6:04 ` [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema Vidya Sagar
@ 2022-06-29 6:29 ` Krzysztof Kozlowski
2022-07-06 9:51 ` Vidya Sagar
2022-06-30 21:04 ` Rob Herring
1 sibling, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-29 6:29 UTC (permalink / raw)
To: Vidya Sagar, bhelgaas, lorenzo.pieralisi, robh+dt,
thierry.reding, jonathanh
Cc: kishon, vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv, Thierry Reding
On 29/06/2022 08:04, Vidya Sagar wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the Tegra194 PCIe bindings from the free-form text format to
> json-schema.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> V3:
> * New patch in this series. Added as part of addressing Rob's review
> comment to convert the existing .txt file to .yaml schema
You need to rebase on newer tree (judging by address list). Changes on
some old kernel are not accepted.
>
> .../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 239 ++++++++++++++++
> .../bindings/pci/nvidia,tegra194-pcie.txt | 245 -----------------
> .../bindings/pci/nvidia,tegra194-pcie.yaml | 254 ++++++++++++++++++
> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
> 4 files changed, 494 insertions(+), 246 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> new file mode 100644
> index 000000000000..4f7cb7fe378e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> @@ -0,0 +1,239 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra194 (and later) PCIe endpoint controller (Synopsys DesignWare Core based)
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> + - Vidya Sagar <vidyas@nvidia.com>
> +
> +description: |
> + This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
> + properties defined in snps,dw-pcie-ep.yaml. Some of the controller instances are dual mode where
> + in they can work either in root port mode or endpoint mode but one at a time.
Wrap according to Linux coding style, so at 80 character.
> +
> + On Tegra194, controllers C0, C4 and C5 support endpoint mode.
> +
> + Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the
> + endpoint mode because of the way the platform is designed.
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra194-pcie-ep
> +
> + reg:
> + items:
> + - description: controller's application logic registers
> + - description: iATU and DMA registers. This is where the iATU (internal Address Translation
> + Unit) registers of the PCIe core are made available for software access.
> + - description: The aperture where the root port's own configuration registers are available.
> + - description: Aperture used to map the remote root-complex' address space.
> +
> + reg-names:
> + items:
> + - const: appl
> + - const: atu_dma
> + - const: dbi
> + - const: addr_space
> +
> + interrupts:
> + items:
> + - description: controller interrupt
> +
> + interrupt-names:
> + items:
> + - const: intr
> +
> + clocks:
> + items:
> + - description: module clock
> +
> + clock-names:
> + items:
> + - const: core
> +
> + resets:
> + items:
> + - description: APB bus interface reset
> + - description: module reset
> +
> + reset-names:
> + items:
> + - const: apb
> + - const: core
> +
> + reset-gpios:
> + description: Must contain a phandle to a GPIO controller followed by GPIO that is being used as
> + PERST input signal. Please refer to pci.txt document.
> +
> + phys:
> + minItems: 1
> + maxItems: 16
> +
> + phy-names:
> + minItems: 1
> + maxItems: 16
> + items:
> + pattern: "^p2u-[0-9]+$"
No, because this allows any/unspecified order. Please list the items, so
the order is fixed.
> +
> + power-domains:
maxItems: 1
> + description: |
> + A phandle to the node that controls power to the respective PCIe controller and a specifier
> + name for the PCIe controller. Following are the specifiers for the different PCIe
> + controllers:
> +
> + - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
> + - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
> + - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
No need to list contents of the header file.
> +
> + these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
> +
> + interconnects:
> + items:
> + - description: memory read client
> + - description: memory write client
> +
> + interconnect-names:
> + items:
> + - const: dma-mem # read
> + - const: write
> +
> + dma-coherent: true
> +
> + num-ib-windows:
> + description: number of inbound address translation windows
> + maxItems: 1
> + deprecated: true
This property was not in old bindings and you did not mention any
changes done during conversion.
> +
> + num-ob-windows:
> + description: number of outbound address translation windows
> + maxItems: 1
> + deprecated: true
The same.
> +
> + nvidia,bpmp:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
> + are the controller IDs for each controller:
> +
> + 0: C0
> + 1: C1
> + 2: C2
> + 3: C3
> + 4: C4
> + 5: C5
> + items:
> + - items:
> + - minimum: 0
> + maximum: 0xffffffff
> + - enum: [ 0, 1, 2, 3, 4, 5 ]
> +
> + nvidia,aspm-cmrt-us:
> + description: Common Mode Restore Time for proper operation of ASPM to be specified in
> + microseconds
> +
> + nvidia,aspm-pwr-on-t-us:
> + description: Power On time for proper operation of ASPM to be specified in microseconds
> +
> + nvidia,aspm-l0s-entrance-latency-us:
> + description: ASPM L0s entrance latency to be specified in microseconds
> +
> + vddio-pex-ctl-supply:
> + description: A phandle to the regulator supply for PCIe side band signals.
> +
> + nvidia,refclk-select-gpios:
> + description: Must contain a phandle to a GPIO controller followed by GPIO that is being used to
> + enable REFCLK to controller from host
> + $ref: /schemas/types.yaml#/definitions/phandle-array
No need for ref. But you need maxItems.
> +
> +allOf:
> + - $ref: "/schemas/pci/pci-ep.yaml#"
No need for quotes.
> +
> +unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - num-ib-windows
> + - num-ob-windows
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - power-domains
> + - reset-gpios
> + - num-lanes
> + - phys
> + - phy-names
> + - nvidia,bpmp
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra194-clock.h>
> + #include <dt-bindings/gpio/tegra194-gpio.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/tegra194-powergate.h>
> + #include <dt-bindings/reset/tegra194-reset.h>
> +
> + bus@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x8 0x0>;
> +
> + pcie-ep@141a0000 {
> + compatible = "nvidia,tegra194-pcie-ep";
> + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
> + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
> + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
> + <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
> + reg-names = "appl", "atu_dma", "dbi", "addr_space";
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> + interrupt-names = "intr";
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
> + <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
> + reset-names = "apb", "core";
> +
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&clkreq_c5_bi_dir_state>;
> +
> + nvidia,bpmp = <&bpmp 5>;
> +
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
> +
> + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
> +
> + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
> + GPIO_ACTIVE_HIGH>;
> +
> + num-lanes = <8>;
> + num-ib-windows = <2>;
> + num-ob-windows = <8>;
Skip deprecated properties from example.
> +
> + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
> + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
> + <&p2u_nvhs_6>, <&p2u_nvhs_7>;
> +
> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
> + "p2u-5", "p2u-6", "p2u-7";
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> deleted file mode 100644
> index 8e4f9bfb316d..000000000000
> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> +++ /dev/null
> @@ -1,245 +0,0 @@
> -NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
> -
> -This PCIe controller is based on the Synopsis Designware PCIe IP
> -and thus inherits all the common properties defined in snps,dw-pcie.yaml and
> -snps,dw-pcie-ep.yaml.
> -Some of the controller instances are dual mode where in they can work either
> -in root port mode or endpoint mode but one at a time.
> -
> -Required properties:
> -- power-domains: A phandle to the node that controls power to the respective
> - PCIe controller and a specifier name for the PCIe controller. Following are
> - the specifiers for the different PCIe controllers
> - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
> - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
> - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
> - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
> - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
> - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
> - these specifiers are defined in
> - "include/dt-bindings/power/tegra194-powergate.h" file.
> -- reg: A list of physical base address and length pairs for each set of
> - controller registers. Must contain an entry for each entry in the reg-names
> - property.
> -- reg-names: Must include the following entries:
> - "appl": Controller's application logic registers
> - "config": As per the definition in snps,dw-pcie.yaml
> - "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
> - Translation Unit) registers of the PCIe core are made available
> - for SW access.
> - "dbi": The aperture where root port's own configuration registers are
> - available
> -- interrupts: A list of interrupt outputs of the controller. Must contain an
> - entry for each entry in the interrupt-names property.
> -- interrupt-names: Must include the following entries:
> - "intr": The Tegra interrupt that is asserted for controller interrupts
> -- clocks: Must contain an entry for each entry in clock-names.
> - See ../clocks/clock-bindings.txt for details.
> -- clock-names: Must include the following entries:
> - - core
> -- resets: Must contain an entry for each entry in reset-names.
> - See ../reset/reset.txt for details.
> -- reset-names: Must include the following entries:
> - - apb
> - - core
> -- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
> -- phy-names: Must include an entry for each active lane.
> - "p2u-N": where N ranges from 0 to one less than the total number of lanes
> -- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
> - by controller-id. Following are the controller ids for each controller.
> - 0: C0
> - 1: C1
> - 2: C2
> - 3: C3
> - 4: C4
> - 5: C5
> -- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
> -
> -RC mode:
> -- compatible: Tegra19x must contain "nvidia,tegra194-pcie"
> -- device_type: Must be "pci" for RC mode
> -- interrupt-names: Must include the following entries:
> - "msi": The Tegra interrupt that is asserted when an MSI is received
> -- bus-range: Range of bus numbers associated with this controller
> -- #address-cells: Address representation for root ports (must be 3)
> - - cell 0 specifies the bus and device numbers of the root port:
> - [23:16]: bus number
> - [15:11]: device number
> - - cell 1 denotes the upper 32 address bits and should be 0
> - - cell 2 contains the lower 32 address bits and is used to translate to the
> - CPU address space
> -- #size-cells: Size representation for root ports (must be 2)
> -- ranges: Describes the translation of addresses for root ports and standard
> - PCI regions. The entries must be 7 cells each, where the first three cells
> - correspond to the address as described for the #address-cells property
> - above, the fourth and fifth cells are for the physical CPU address to
> - translate to and the sixth and seventh cells are as described for the
> - #size-cells property above.
> - - Entries setup the mapping for the standard I/O, memory and
> - prefetchable PCI regions. The first cell determines the type of region
> - that is setup:
> - - 0x81000000: I/O memory region
> - - 0x82000000: non-prefetchable memory region
> - - 0xc2000000: prefetchable memory region
> - Please refer to the standard PCI bus binding document for a more detailed
> - explanation.
> -- #interrupt-cells: Size representation for interrupts (must be 1)
> -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> - Please refer to the standard PCI bus binding document for a more detailed
> - explanation.
> -
> -EP mode:
> -In Tegra194, Only controllers C0, C4 & C5 support EP mode.
> -- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
> -- reg-names: Must include the following entries:
> - "addr_space": Used to map remote RC address space
> -- reset-gpios: Must contain a phandle to a GPIO controller followed by
> - GPIO that is being used as PERST input signal. Please refer to pci.txt
> - document.
> -
> -Optional properties:
> -- pinctrl-names: A list of pinctrl state names.
> - It is mandatory for C5 controller and optional for other controllers.
> - - "default": Configures PCIe I/O for proper operation.
> -- pinctrl-0: phandle for the 'default' state of pin configuration.
> - It is mandatory for C5 controller and optional for other controllers.
> -- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
> -- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
> - improve performance when a platform is designed in such a way that it
> - satisfies at least one of the following conditions thereby enabling root
> - port to exchange optimum number of FC (Flow Control) credits with
> - downstream devices
> - 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
> - 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
> - a) speed is Gen-2 and MPS is 256B
> - b) speed is >= Gen-3 with any MPS
> -- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
> - to be specified in microseconds
> -- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
> - specified in microseconds
> -- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
> - specified in microseconds
> -
> -RC mode:
> -- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
> - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
> - in p2972-0000 platform).
> -- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
> - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
> - in p2972-0000 platform).
> -
> -EP mode:
> -- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
> - followed by GPIO that is being used to enable REFCLK to controller from host
> -
> -NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
> -operate in the endpoint mode because of the way the platform is designed.
> -
> -Examples:
> -=========
> -
> -Tegra194 RC mode:
> ------------------
> -
> - pcie@14180000 {
> - compatible = "nvidia,tegra194-pcie";
> - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
> - reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
> - 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
> - 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
> - reg-names = "appl", "config", "atu_dma";
> -
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - num-lanes = <8>;
> - linux,pci-domain = <0>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
> -
> - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
> - clock-names = "core";
> -
> - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
> - <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
> - reset-names = "apb", "core";
> -
> - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> - interrupt-names = "intr", "msi";
> -
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> -
> - nvidia,bpmp = <&bpmp 0>;
> -
> - supports-clkreq;
> - nvidia,aspm-cmrt-us = <60>;
> - nvidia,aspm-pwr-on-t-us = <20>;
> - nvidia,aspm-l0s-entrance-latency-us = <3>;
> -
> - bus-range = <0x0 0xff>;
> - ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
> - 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
> - 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
> -
> - vddio-pex-ctl-supply = <&vdd_1v8ao>;
> - vpcie3v3-supply = <&vdd_3v3_pcie>;
> - vpcie12v-supply = <&vdd_12v_pcie>;
> -
> - phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
> - <&p2u_hsio_5>;
> - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
> - };
> -
> -Tegra194 EP mode:
> ------------------
> -
> - pcie-ep@141a0000 {
> - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
> - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
> - reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
> - 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> - 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
> - 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
> - reg-names = "appl", "atu_dma", "dbi", "addr_space";
> -
> - num-lanes = <8>;
> - num-ib-windows = <2>;
> - num-ob-windows = <8>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&clkreq_c5_bi_dir_state>;
> -
> - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
> - clock-names = "core";
> -
> - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
> - <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
> - reset-names = "apb", "core";
> -
> - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> - interrupt-names = "intr";
> -
> - nvidia,bpmp = <&bpmp 5>;
> -
> - nvidia,aspm-cmrt-us = <60>;
> - nvidia,aspm-pwr-on-t-us = <20>;
> - nvidia,aspm-l0s-entrance-latency-us = <3>;
> -
> - vddio-pex-ctl-supply = <&vdd_1v8ao>;
> -
> - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
> -
> - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
> - GPIO_ACTIVE_HIGH>;
> -
> - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
> - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
> - <&p2u_nvhs_6>, <&p2u_nvhs_7>;
> -
> - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
> - "p2u-5", "p2u-6", "p2u-7";
> - };
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
> new file mode 100644
> index 000000000000..4a49dddf33bb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
> @@ -0,0 +1,254 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> + - Vidya Sagar <vidyas@nvidia.com>
> +
> +description: |
> + This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
> + properties defined in snps,dw-pcie.yaml. Some of the controller instances are dual mode where in
> + they can work either in root port mode or endpoint mode but one at a time.
Also not properly wrapped.
> +
> + See nvidia,tegra194-pcie-ep.yaml for details on the endpoint mode device tree bindings.
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra194-pcie
> +
> + reg:
> + items:
> + - description: controller's application logic registers
> + - description: configuration registers
> + - description: iATU and DMA registers. This is where the iATU (internal Address Translation
> + Unit) registers of the PCIe core are made available for software access.
> + - description: The aperture where the root port's own configuration registers are available.
> +
> + reg-names:
> + items:
> + - const: appl
> + - const: config
> + - const: atu_dma
> + - const: dbi
> +
> + interrupts:
> + items:
> + - description: controller interrupt
> + - description: MSI interrupt
> +
> + interrupt-names:
> + items:
> + - const: intr
> + - const: msi
> +
> + clocks:
> + items:
> + - description: module clock
> +
> + clock-names:
> + items:
> + - const: core
> +
> + resets:
> + items:
> + - description: APB bus interface reset
> + - description: module reset
> +
> + reset-names:
> + items:
> + - const: apb
> + - const: core
> +
> + phys:
> + minItems: 1
> + maxItems: 16
> +
> + phy-names:
> + minItems: 1
> + maxItems: 16
> + items:
> + pattern: "^p2u-[0-9]+$"
Same problem.
> +
> + power-domains:
> + description: |
> + A phandle to the node that controls power to the respective PCIe controller and a specifier
> + name for the PCIe controller. Following are the specifiers for the different PCIe
> + controllers:
> +
> + - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
> + - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
> + - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
Remove as well.
> +
> + these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
> +
> + interconnects:
> + items:
> + - description: memory read client
> + - description: memory write client
> +
> + interconnect-names:
> + items:
> + - const: dma-mem # read
> + - const: write
> +
> + dma-coherent: true
> +
> + supports-clkreq:
> + description: see pci.txt for details
This comes from schema (pci-bus.yaml). Remove here and in EP schema all
properties which are defined by pci-bus or any other referenced schemas,
unless you customize them more.
> +
> + nvidia,bpmp:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
> + are the controller IDs for each controller:
> +
> + 0: C0
> + 1: C1
> + 2: C2
> + 3: C3
> + 4: C4
> + 5: C5
> + items:
> + - items:
> + - minimum: 0
> + maximum: 0xffffffff
> + - enum: [ 0, 1, 2, 3, 4, 5 ]
> +
> + nvidia,update-fc-fixup:
> + description: |
> + This is a boolean property and needs to be present to improve performance when a platform is
> + designed in such a way that it satisfies at least one of the following conditions thereby
> + enabling root port to exchange optimum number of FC (Flow Control) credits with downstream
Not wrapped.
> + devices:
> +
> + 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
> + 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
> + a) speed is Gen-2 and MPS is 256B
> + b) speed is >= Gen-3 with any MPS
> +
> + $ref: /schemas/types.yaml#/definitions/flag
> +
> + nvidia,aspm-cmrt-us:
> + description: Common Mode Restore Time for proper operation of ASPM to be specified in
> + microseconds
> +
> + nvidia,aspm-pwr-on-t-us:
> + description: Power On time for proper operation of ASPM to be specified in microseconds
> +
> + nvidia,aspm-l0s-entrance-latency-us:
> + description: ASPM L0s entrance latency to be specified in microseconds
> +
> + vddio-pex-ctl-supply:
> + description: A phandle to the regulator supply for PCIe side band signals.
> +
> + vpcie3v3-supply:
> + description: A phandle to the regulator node that supplies 3.3V to the slot if the platform has
> + one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
> +
> + vpcie12v-supply:
> + description: A phandle to the regulator node that supplies 12V to the slot if the platform has
> + one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
> +
> +allOf:
> + - $ref: "/schemas/pci/pci-bus.yaml#"
> + - $ref: "/schemas/pci/snps,dw-pcie.yaml#"
No need for quotes.
> +
> +unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - interrupt-names
> + - interrupt-map
> + - interrupt-map-mask
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - power-domains
> + - bus-range
> + - ranges
> + - vddio-pex-ctl-supply
> + - num-lanes
> + - phys
> + - phy-names
> + - nvidia,bpmp
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra194-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/tegra194-powergate.h>
> + #include <dt-bindings/reset/tegra194-reset.h>
> +
> + bus@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x8 0x0>;
> +
> + pcie@14180000 {
> + compatible = "nvidia,tegra194-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
> + reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
> + <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
> + <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
> + <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <8>;
> + linux,pci-domain = <0>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 0>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
> + <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
> + <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
> +
> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
> + vpcie3v3-supply = <&vdd_3v3_pcie>;
> + vpcie12v-supply = <&vdd_12v_pcie>;
> +
> + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
> + <&p2u_hsio_5>;
> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> index c90e5e2d25f6..7e0bf941fbfe 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> @@ -35,7 +35,7 @@ properties:
> maxItems: 5
> items:
> enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
> - ulreg, smu, mpu, apb, phy ]
> + ulreg, smu, mpu, apb, phy, appl, atu_dma ]
>
> num-lanes:
> description: |
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-06-29 6:29 ` Krzysztof Kozlowski
@ 2022-07-06 9:51 ` Vidya Sagar
2022-07-06 9:58 ` Krzysztof Kozlowski
0 siblings, 1 reply; 27+ messages in thread
From: Vidya Sagar @ 2022-07-06 9:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, bhelgaas, lorenzo.pieralisi, robh+dt,
thierry.reding, jonathanh
Cc: kishon, vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv, Thierry Reding
On 6/29/2022 11:59 AM, Krzysztof Kozlowski wrote:
> External email: Use caution opening links or attachments
>
>
> On 29/06/2022 08:04, Vidya Sagar wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> Convert the Tegra194 PCIe bindings from the free-form text format to
>> json-schema.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> ---
>> V3:
>> * New patch in this series. Added as part of addressing Rob's review
>> comment to convert the existing .txt file to .yaml schema
>
> You need to rebase on newer tree (judging by address list). Changes on
> some old kernel are not accepted.
>
>>
>> .../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 239 ++++++++++++++++
>> .../bindings/pci/nvidia,tegra194-pcie.txt | 245 -----------------
>> .../bindings/pci/nvidia,tegra194-pcie.yaml | 254 ++++++++++++++++++
>> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
>> 4 files changed, 494 insertions(+), 246 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
>> delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
>> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
>> new file mode 100644
>> index 000000000000..4f7cb7fe378e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
>> @@ -0,0 +1,239 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: NVIDIA Tegra194 (and later) PCIe endpoint controller (Synopsys DesignWare Core based)
>> +
>> +maintainers:
>> + - Thierry Reding <thierry.reding@gmail.com>
>> + - Jon Hunter <jonathanh@nvidia.com>
>> + - Vidya Sagar <vidyas@nvidia.com>
>> +
>> +description: |
>> + This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
>> + properties defined in snps,dw-pcie-ep.yaml. Some of the controller instances are dual mode where
>> + in they can work either in root port mode or endpoint mode but one at a time.
>
> Wrap according to Linux coding style, so at 80 character.
>
>> +
>> + On Tegra194, controllers C0, C4 and C5 support endpoint mode.
>> +
>> + Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the
>> + endpoint mode because of the way the platform is designed.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - nvidia,tegra194-pcie-ep
>> +
>> + reg:
>> + items:
>> + - description: controller's application logic registers
>> + - description: iATU and DMA registers. This is where the iATU (internal Address Translation
>> + Unit) registers of the PCIe core are made available for software access.
>> + - description: The aperture where the root port's own configuration registers are available.
>> + - description: Aperture used to map the remote root-complex' address space.
>> +
>> + reg-names:
>> + items:
>> + - const: appl
>> + - const: atu_dma
>> + - const: dbi
>> + - const: addr_space
>> +
>> + interrupts:
>> + items:
>> + - description: controller interrupt
>> +
>> + interrupt-names:
>> + items:
>> + - const: intr
>> +
>> + clocks:
>> + items:
>> + - description: module clock
>> +
>> + clock-names:
>> + items:
>> + - const: core
>> +
>> + resets:
>> + items:
>> + - description: APB bus interface reset
>> + - description: module reset
>> +
>> + reset-names:
>> + items:
>> + - const: apb
>> + - const: core
>> +
>> + reset-gpios:
>> + description: Must contain a phandle to a GPIO controller followed by GPIO that is being used as
>> + PERST input signal. Please refer to pci.txt document.
>> +
>> + phys:
>> + minItems: 1
>> + maxItems: 16
>> +
>> + phy-names:
>> + minItems: 1
>> + maxItems: 16
>> + items:
>> + pattern: "^p2u-[0-9]+$"
>
> No, because this allows any/unspecified order. Please list the items, so
> the order is fixed.
Not all controllers are going to have all of them specified. Number of
these entries depend on the number of lanes assigned to that particular
controller. In this scenario, I thought specifying it using 'pattern'
should be fine. Please let me know if there is any other better way to
specify this.
>
>> +
>> + power-domains:
>
> maxItems: 1
>
>> + description: |
>> + A phandle to the node that controls power to the respective PCIe controller and a specifier
>> + name for the PCIe controller. Following are the specifiers for the different PCIe
>> + controllers:
>> +
>> + - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
>> + - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
>> + - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
>
> No need to list contents of the header file.
>
>> +
>> + these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
>> +
>> + interconnects:
>> + items:
>> + - description: memory read client
>> + - description: memory write client
>> +
>> + interconnect-names:
>> + items:
>> + - const: dma-mem # read
>> + - const: write
>> +
>> + dma-coherent: true
>> +
>> + num-ib-windows:
>> + description: number of inbound address translation windows
>> + maxItems: 1
>> + deprecated: true
>
> This property was not in old bindings and you did not mention any
> changes done during conversion.
>
>> +
>> + num-ob-windows:
>> + description: number of outbound address translation windows
>> + maxItems: 1
>> + deprecated: true
>
> The same.
>
>> +
>> + nvidia,bpmp:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description: |
>> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
>> + are the controller IDs for each controller:
>> +
>> + 0: C0
>> + 1: C1
>> + 2: C2
>> + 3: C3
>> + 4: C4
>> + 5: C5
>> + items:
>> + - items:
>> + - minimum: 0
>> + maximum: 0xffffffff
>> + - enum: [ 0, 1, 2, 3, 4, 5 ]
>> +
>> + nvidia,aspm-cmrt-us:
>> + description: Common Mode Restore Time for proper operation of ASPM to be specified in
>> + microseconds
>> +
>> + nvidia,aspm-pwr-on-t-us:
>> + description: Power On time for proper operation of ASPM to be specified in microseconds
>> +
>> + nvidia,aspm-l0s-entrance-latency-us:
>> + description: ASPM L0s entrance latency to be specified in microseconds
>> +
>> + vddio-pex-ctl-supply:
>> + description: A phandle to the regulator supply for PCIe side band signals.
>> +
>> + nvidia,refclk-select-gpios:
>> + description: Must contain a phandle to a GPIO controller followed by GPIO that is being used to
>> + enable REFCLK to controller from host
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>
> No need for ref. But you need maxItems.
>
>> +
>> +allOf:
>> + - $ref: "/schemas/pci/pci-ep.yaml#"
>
> No need for quotes.
>
>> +
>> +unevaluatedProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - num-ib-windows
>> + - num-ob-windows
>> + - interrupts
>> + - interrupt-names
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - power-domains
>> + - reset-gpios
>> + - num-lanes
>> + - phys
>> + - phy-names
>> + - nvidia,bpmp
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/tegra194-clock.h>
>> + #include <dt-bindings/gpio/tegra194-gpio.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/power/tegra194-powergate.h>
>> + #include <dt-bindings/reset/tegra194-reset.h>
>> +
>> + bus@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x0 0x0 0x0 0x8 0x0>;
>> +
>> + pcie-ep@141a0000 {
>> + compatible = "nvidia,tegra194-pcie-ep";
>> + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> + <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> + reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> + interrupt-names = "intr";
>> +
>> + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> + clock-names = "core";
>> +
>> + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> + <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> + reset-names = "apb", "core";
>> +
>> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&clkreq_c5_bi_dir_state>;
>> +
>> + nvidia,bpmp = <&bpmp 5>;
>> +
>> + nvidia,aspm-cmrt-us = <60>;
>> + nvidia,aspm-pwr-on-t-us = <20>;
>> + nvidia,aspm-l0s-entrance-latency-us = <3>;
>> +
>> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
>> +
>> + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
>> +
>> + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
>> + GPIO_ACTIVE_HIGH>;
>> +
>> + num-lanes = <8>;
>> + num-ib-windows = <2>;
>> + num-ob-windows = <8>;
>
> Skip deprecated properties from example.
>
>> +
>> + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
>> + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
>> + <&p2u_nvhs_6>, <&p2u_nvhs_7>;
>> +
>> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
>> + "p2u-5", "p2u-6", "p2u-7";
>> + };
>> + };
>> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
>> deleted file mode 100644
>> index 8e4f9bfb316d..000000000000
>> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
>> +++ /dev/null
>> @@ -1,245 +0,0 @@
>> -NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
>> -
>> -This PCIe controller is based on the Synopsis Designware PCIe IP
>> -and thus inherits all the common properties defined in snps,dw-pcie.yaml and
>> -snps,dw-pcie-ep.yaml.
>> -Some of the controller instances are dual mode where in they can work either
>> -in root port mode or endpoint mode but one at a time.
>> -
>> -Required properties:
>> -- power-domains: A phandle to the node that controls power to the respective
>> - PCIe controller and a specifier name for the PCIe controller. Following are
>> - the specifiers for the different PCIe controllers
>> - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
>> - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
>> - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
>> - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
>> - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
>> - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
>> - these specifiers are defined in
>> - "include/dt-bindings/power/tegra194-powergate.h" file.
>> -- reg: A list of physical base address and length pairs for each set of
>> - controller registers. Must contain an entry for each entry in the reg-names
>> - property.
>> -- reg-names: Must include the following entries:
>> - "appl": Controller's application logic registers
>> - "config": As per the definition in snps,dw-pcie.yaml
>> - "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
>> - Translation Unit) registers of the PCIe core are made available
>> - for SW access.
>> - "dbi": The aperture where root port's own configuration registers are
>> - available
>> -- interrupts: A list of interrupt outputs of the controller. Must contain an
>> - entry for each entry in the interrupt-names property.
>> -- interrupt-names: Must include the following entries:
>> - "intr": The Tegra interrupt that is asserted for controller interrupts
>> -- clocks: Must contain an entry for each entry in clock-names.
>> - See ../clocks/clock-bindings.txt for details.
>> -- clock-names: Must include the following entries:
>> - - core
>> -- resets: Must contain an entry for each entry in reset-names.
>> - See ../reset/reset.txt for details.
>> -- reset-names: Must include the following entries:
>> - - apb
>> - - core
>> -- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
>> -- phy-names: Must include an entry for each active lane.
>> - "p2u-N": where N ranges from 0 to one less than the total number of lanes
>> -- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
>> - by controller-id. Following are the controller ids for each controller.
>> - 0: C0
>> - 1: C1
>> - 2: C2
>> - 3: C3
>> - 4: C4
>> - 5: C5
>> -- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
>> -
>> -RC mode:
>> -- compatible: Tegra19x must contain "nvidia,tegra194-pcie"
>> -- device_type: Must be "pci" for RC mode
>> -- interrupt-names: Must include the following entries:
>> - "msi": The Tegra interrupt that is asserted when an MSI is received
>> -- bus-range: Range of bus numbers associated with this controller
>> -- #address-cells: Address representation for root ports (must be 3)
>> - - cell 0 specifies the bus and device numbers of the root port:
>> - [23:16]: bus number
>> - [15:11]: device number
>> - - cell 1 denotes the upper 32 address bits and should be 0
>> - - cell 2 contains the lower 32 address bits and is used to translate to the
>> - CPU address space
>> -- #size-cells: Size representation for root ports (must be 2)
>> -- ranges: Describes the translation of addresses for root ports and standard
>> - PCI regions. The entries must be 7 cells each, where the first three cells
>> - correspond to the address as described for the #address-cells property
>> - above, the fourth and fifth cells are for the physical CPU address to
>> - translate to and the sixth and seventh cells are as described for the
>> - #size-cells property above.
>> - - Entries setup the mapping for the standard I/O, memory and
>> - prefetchable PCI regions. The first cell determines the type of region
>> - that is setup:
>> - - 0x81000000: I/O memory region
>> - - 0x82000000: non-prefetchable memory region
>> - - 0xc2000000: prefetchable memory region
>> - Please refer to the standard PCI bus binding document for a more detailed
>> - explanation.
>> -- #interrupt-cells: Size representation for interrupts (must be 1)
>> -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
>> - Please refer to the standard PCI bus binding document for a more detailed
>> - explanation.
>> -
>> -EP mode:
>> -In Tegra194, Only controllers C0, C4 & C5 support EP mode.
>> -- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
>> -- reg-names: Must include the following entries:
>> - "addr_space": Used to map remote RC address space
>> -- reset-gpios: Must contain a phandle to a GPIO controller followed by
>> - GPIO that is being used as PERST input signal. Please refer to pci.txt
>> - document.
>> -
>> -Optional properties:
>> -- pinctrl-names: A list of pinctrl state names.
>> - It is mandatory for C5 controller and optional for other controllers.
>> - - "default": Configures PCIe I/O for proper operation.
>> -- pinctrl-0: phandle for the 'default' state of pin configuration.
>> - It is mandatory for C5 controller and optional for other controllers.
>> -- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
>> -- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
>> - improve performance when a platform is designed in such a way that it
>> - satisfies at least one of the following conditions thereby enabling root
>> - port to exchange optimum number of FC (Flow Control) credits with
>> - downstream devices
>> - 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
>> - 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
>> - a) speed is Gen-2 and MPS is 256B
>> - b) speed is >= Gen-3 with any MPS
>> -- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
>> - to be specified in microseconds
>> -- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
>> - specified in microseconds
>> -- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
>> - specified in microseconds
>> -
>> -RC mode:
>> -- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
>> - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
>> - in p2972-0000 platform).
>> -- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
>> - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
>> - in p2972-0000 platform).
>> -
>> -EP mode:
>> -- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
>> - followed by GPIO that is being used to enable REFCLK to controller from host
>> -
>> -NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
>> -operate in the endpoint mode because of the way the platform is designed.
>> -
>> -Examples:
>> -=========
>> -
>> -Tegra194 RC mode:
>> ------------------
>> -
>> - pcie@14180000 {
>> - compatible = "nvidia,tegra194-pcie";
>> - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> - reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
>> - 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
>> - 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
>> - reg-names = "appl", "config", "atu_dma";
>> -
>> - #address-cells = <3>;
>> - #size-cells = <2>;
>> - device_type = "pci";
>> - num-lanes = <8>;
>> - linux,pci-domain = <0>;
>> -
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
>> -
>> - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> - clock-names = "core";
>> -
>> - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> - <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> - reset-names = "apb", "core";
>> -
>> - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> - interrupt-names = "intr", "msi";
>> -
>> - #interrupt-cells = <1>;
>> - interrupt-map-mask = <0 0 0 0>;
>> - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> -
>> - nvidia,bpmp = <&bpmp 0>;
>> -
>> - supports-clkreq;
>> - nvidia,aspm-cmrt-us = <60>;
>> - nvidia,aspm-pwr-on-t-us = <20>;
>> - nvidia,aspm-l0s-entrance-latency-us = <3>;
>> -
>> - bus-range = <0x0 0xff>;
>> - ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
>> - 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
>> - 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
>> -
>> - vddio-pex-ctl-supply = <&vdd_1v8ao>;
>> - vpcie3v3-supply = <&vdd_3v3_pcie>;
>> - vpcie12v-supply = <&vdd_12v_pcie>;
>> -
>> - phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
>> - <&p2u_hsio_5>;
>> - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
>> - };
>> -
>> -Tegra194 EP mode:
>> ------------------
>> -
>> - pcie-ep@141a0000 {
>> - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
>> - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> - reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
>> - 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
>> - 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
>> - 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> - reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> -
>> - num-lanes = <8>;
>> - num-ib-windows = <2>;
>> - num-ob-windows = <8>;
>> -
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&clkreq_c5_bi_dir_state>;
>> -
>> - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> - clock-names = "core";
>> -
>> - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> - <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> - reset-names = "apb", "core";
>> -
>> - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> - interrupt-names = "intr";
>> -
>> - nvidia,bpmp = <&bpmp 5>;
>> -
>> - nvidia,aspm-cmrt-us = <60>;
>> - nvidia,aspm-pwr-on-t-us = <20>;
>> - nvidia,aspm-l0s-entrance-latency-us = <3>;
>> -
>> - vddio-pex-ctl-supply = <&vdd_1v8ao>;
>> -
>> - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
>> -
>> - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
>> - GPIO_ACTIVE_HIGH>;
>> -
>> - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
>> - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
>> - <&p2u_nvhs_6>, <&p2u_nvhs_7>;
>> -
>> - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
>> - "p2u-5", "p2u-6", "p2u-7";
>> - };
>> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
>> new file mode 100644
>> index 000000000000..4a49dddf33bb
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
>> @@ -0,0 +1,254 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
>> +
>> +maintainers:
>> + - Thierry Reding <thierry.reding@gmail.com>
>> + - Jon Hunter <jonathanh@nvidia.com>
>> + - Vidya Sagar <vidyas@nvidia.com>
>> +
>> +description: |
>> + This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
>> + properties defined in snps,dw-pcie.yaml. Some of the controller instances are dual mode where in
>> + they can work either in root port mode or endpoint mode but one at a time.
>
> Also not properly wrapped.
>
>> +
>> + See nvidia,tegra194-pcie-ep.yaml for details on the endpoint mode device tree bindings.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - nvidia,tegra194-pcie
>> +
>> + reg:
>> + items:
>> + - description: controller's application logic registers
>> + - description: configuration registers
>> + - description: iATU and DMA registers. This is where the iATU (internal Address Translation
>> + Unit) registers of the PCIe core are made available for software access.
>> + - description: The aperture where the root port's own configuration registers are available.
>> +
>> + reg-names:
>> + items:
>> + - const: appl
>> + - const: config
>> + - const: atu_dma
>> + - const: dbi
>> +
>> + interrupts:
>> + items:
>> + - description: controller interrupt
>> + - description: MSI interrupt
>> +
>> + interrupt-names:
>> + items:
>> + - const: intr
>> + - const: msi
>> +
>> + clocks:
>> + items:
>> + - description: module clock
>> +
>> + clock-names:
>> + items:
>> + - const: core
>> +
>> + resets:
>> + items:
>> + - description: APB bus interface reset
>> + - description: module reset
>> +
>> + reset-names:
>> + items:
>> + - const: apb
>> + - const: core
>> +
>> + phys:
>> + minItems: 1
>> + maxItems: 16
>> +
>> + phy-names:
>> + minItems: 1
>> + maxItems: 16
>> + items:
>> + pattern: "^p2u-[0-9]+$"
>
> Same problem.
>
>> +
>> + power-domains:
>> + description: |
>> + A phandle to the node that controls power to the respective PCIe controller and a specifier
>> + name for the PCIe controller. Following are the specifiers for the different PCIe
>> + controllers:
>> +
>> + - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
>> + - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
>> + - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
>
> Remove as well.
>
>> +
>> + these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
>> +
>> + interconnects:
>> + items:
>> + - description: memory read client
>> + - description: memory write client
>> +
>> + interconnect-names:
>> + items:
>> + - const: dma-mem # read
>> + - const: write
>> +
>> + dma-coherent: true
>> +
>> + supports-clkreq:
>> + description: see pci.txt for details
>
> This comes from schema (pci-bus.yaml). Remove here and in EP schema all
> properties which are defined by pci-bus or any other referenced schemas,
> unless you customize them more.
>
>> +
>> + nvidia,bpmp:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description: |
>> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
>> + are the controller IDs for each controller:
>> +
>> + 0: C0
>> + 1: C1
>> + 2: C2
>> + 3: C3
>> + 4: C4
>> + 5: C5
>> + items:
>> + - items:
>> + - minimum: 0
>> + maximum: 0xffffffff
>> + - enum: [ 0, 1, 2, 3, 4, 5 ]
>> +
>> + nvidia,update-fc-fixup:
>> + description: |
>> + This is a boolean property and needs to be present to improve performance when a platform is
>> + designed in such a way that it satisfies at least one of the following conditions thereby
>> + enabling root port to exchange optimum number of FC (Flow Control) credits with downstream
>
> Not wrapped.
>
>> + devices:
>> +
>> + 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
>> + 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
>> + a) speed is Gen-2 and MPS is 256B
>> + b) speed is >= Gen-3 with any MPS
>> +
>> + $ref: /schemas/types.yaml#/definitions/flag
>> +
>> + nvidia,aspm-cmrt-us:
>> + description: Common Mode Restore Time for proper operation of ASPM to be specified in
>> + microseconds
>> +
>> + nvidia,aspm-pwr-on-t-us:
>> + description: Power On time for proper operation of ASPM to be specified in microseconds
>> +
>> + nvidia,aspm-l0s-entrance-latency-us:
>> + description: ASPM L0s entrance latency to be specified in microseconds
>> +
>> + vddio-pex-ctl-supply:
>> + description: A phandle to the regulator supply for PCIe side band signals.
>> +
>> + vpcie3v3-supply:
>> + description: A phandle to the regulator node that supplies 3.3V to the slot if the platform has
>> + one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
>> +
>> + vpcie12v-supply:
>> + description: A phandle to the regulator node that supplies 12V to the slot if the platform has
>> + one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
>> +
>> +allOf:
>> + - $ref: "/schemas/pci/pci-bus.yaml#"
>> + - $ref: "/schemas/pci/snps,dw-pcie.yaml#"
>
> No need for quotes.
>
>> +
>> +unevaluatedProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - interrupts
>> + - interrupt-names
>> + - interrupt-map
>> + - interrupt-map-mask
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - power-domains
>> + - bus-range
>> + - ranges
>> + - vddio-pex-ctl-supply
>> + - num-lanes
>> + - phys
>> + - phy-names
>> + - nvidia,bpmp
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/tegra194-clock.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/power/tegra194-powergate.h>
>> + #include <dt-bindings/reset/tegra194-reset.h>
>> +
>> + bus@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x0 0x0 0x0 0x8 0x0>;
>> +
>> + pcie@14180000 {
>> + compatible = "nvidia,tegra194-pcie";
>> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> + reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> + <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
>> + <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> + <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> + reg-names = "appl", "config", "atu_dma", "dbi";
>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + device_type = "pci";
>> + num-lanes = <8>;
>> + linux,pci-domain = <0>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
>> +
>> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> + clock-names = "core";
>> +
>> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> + <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> + reset-names = "apb", "core";
>> +
>> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> + interrupt-names = "intr", "msi";
>> +
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0>;
>> + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + nvidia,bpmp = <&bpmp 0>;
>> +
>> + supports-clkreq;
>> + nvidia,aspm-cmrt-us = <60>;
>> + nvidia,aspm-pwr-on-t-us = <20>;
>> + nvidia,aspm-l0s-entrance-latency-us = <3>;
>> +
>> + bus-range = <0x0 0xff>;
>> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
>> + <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
>> + <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
>> +
>> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
>> + vpcie3v3-supply = <&vdd_3v3_pcie>;
>> + vpcie12v-supply = <&vdd_12v_pcie>;
>> +
>> + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
>> + <&p2u_hsio_5>;
>> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
>> + };
>> + };
>> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
>> index c90e5e2d25f6..7e0bf941fbfe 100644
>> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
>> @@ -35,7 +35,7 @@ properties:
>> maxItems: 5
>> items:
>> enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
>> - ulreg, smu, mpu, apb, phy ]
>> + ulreg, smu, mpu, apb, phy, appl, atu_dma ]
>>
>> num-lanes:
>> description: |
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-07-06 9:51 ` Vidya Sagar
@ 2022-07-06 9:58 ` Krzysztof Kozlowski
0 siblings, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-06 9:58 UTC (permalink / raw)
To: Vidya Sagar, bhelgaas, lorenzo.pieralisi, robh+dt,
thierry.reding, jonathanh
Cc: kishon, vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv, Thierry Reding
On 06/07/2022 11:51, Vidya Sagar wrote:
>>> + phy-names:
>>> + minItems: 1
>>> + maxItems: 16
>>> + items:
>>> + pattern: "^p2u-[0-9]+$"
>>
>> No, because this allows any/unspecified order. Please list the items, so
>> the order is fixed.
>
> Not all controllers are going to have all of them specified. Number of
> these entries depend on the number of lanes assigned to that particular
> controller. In this scenario, I thought specifying it using 'pattern'
> should be fine. Please let me know if there is any other better way to
> specify this.
As I understood previous bindings and your message above, these are all
incremented by one, so just list them and drop maxItems.
Trim the context, it makes it easier to spot the actual response. You
quoted a lot above and a lot below. I do not know if there is something
more to discuss? Usually quote means there is but I could not find... If
there is, use replying style matching mailing list.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-06-29 6:04 ` [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema Vidya Sagar
2022-06-29 6:29 ` Krzysztof Kozlowski
@ 2022-06-30 21:04 ` Rob Herring
2022-07-06 9:53 ` Vidya Sagar
1 sibling, 1 reply; 27+ messages in thread
From: Rob Herring @ 2022-06-30 21:04 UTC (permalink / raw)
To: Vidya Sagar
Cc: bhelgaas, lorenzo.pieralisi, thierry.reding, jonathanh, kishon,
vkoul, kw, krzk, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv, Thierry Reding
On Wed, Jun 29, 2022 at 11:34:26AM +0530, Vidya Sagar wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the Tegra194 PCIe bindings from the free-form text format to
> json-schema.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> V3:
> * New patch in this series. Added as part of addressing Rob's review
> comment to convert the existing .txt file to .yaml schema
>
> .../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 239 ++++++++++++++++
> .../bindings/pci/nvidia,tegra194-pcie.txt | 245 -----------------
> .../bindings/pci/nvidia,tegra194-pcie.yaml | 254 ++++++++++++++++++
> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
> 4 files changed, 494 insertions(+), 246 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> new file mode 100644
> index 000000000000..4f7cb7fe378e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> @@ -0,0 +1,239 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra194 (and later) PCIe endpoint controller (Synopsys DesignWare Core based)
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> + - Vidya Sagar <vidyas@nvidia.com>
> +
> +description: |
> + This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
Wrap lines at 80 unless there's a benefit to a longer line.
> + properties defined in snps,dw-pcie-ep.yaml. Some of the controller instances are dual mode where
> + in they can work either in root port mode or endpoint mode but one at a time.
> +
> + On Tegra194, controllers C0, C4 and C5 support endpoint mode.
> +
> + Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the
> + endpoint mode because of the way the platform is designed.
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra194-pcie-ep
> +
> + reg:
> + items:
> + - description: controller's application logic registers
> + - description: iATU and DMA registers. This is where the iATU (internal Address Translation
> + Unit) registers of the PCIe core are made available for software access.
> + - description: The aperture where the root port's own configuration registers are available.
> + - description: Aperture used to map the remote root-complex' address space.
> +
> + reg-names:
> + items:
> + - const: appl
> + - const: atu_dma
> + - const: dbi
> + - const: addr_space
> +
> + interrupts:
> + items:
> + - description: controller interrupt
Just 'maxItems: 1' is enough.
> +
> + interrupt-names:
> + items:
> + - const: intr
> +
> + clocks:
> + items:
> + - description: module clock
> +
> + clock-names:
> + items:
> + - const: core
> +
> + resets:
> + items:
> + - description: APB bus interface reset
> + - description: module reset
> +
> + reset-names:
> + items:
> + - const: apb
> + - const: core
> +
> + reset-gpios:
> + description: Must contain a phandle to a GPIO controller followed by GPIO that is being used as
> + PERST input signal. Please refer to pci.txt document.
> +
> + phys:
> + minItems: 1
> + maxItems: 16
One per lane?
> +
> + phy-names:
> + minItems: 1
> + maxItems: 16
> + items:
> + pattern: "^p2u-[0-9]+$"
> +
> + power-domains:
> + description: |
> + A phandle to the node that controls power to the respective PCIe controller and a specifier
> + name for the PCIe controller. Following are the specifiers for the different PCIe
> + controllers:
> +
> + - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
> + - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
> + - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
> +
> + these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
> +
> + interconnects:
> + items:
> + - description: memory read client
> + - description: memory write client
> +
> + interconnect-names:
> + items:
> + - const: dma-mem # read
> + - const: write
> +
> + dma-coherent: true
> +
> + num-ib-windows:
> + description: number of inbound address translation windows
> + maxItems: 1
> + deprecated: true
> +
> + num-ob-windows:
> + description: number of outbound address translation windows
> + maxItems: 1
> + deprecated: true
> +
> + nvidia,bpmp:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
> + are the controller IDs for each controller:
> +
> + 0: C0
> + 1: C1
> + 2: C2
> + 3: C3
> + 4: C4
> + 5: C5
> + items:
> + - items:
> + - minimum: 0
> + maximum: 0xffffffff
That's already the limit. Just a description is fine.
> + - enum: [ 0, 1, 2, 3, 4, 5 ]
maximum: 5
> +
> + nvidia,aspm-cmrt-us:
> + description: Common Mode Restore Time for proper operation of ASPM to be specified in
> + microseconds
> +
> + nvidia,aspm-pwr-on-t-us:
> + description: Power On time for proper operation of ASPM to be specified in microseconds
> +
> + nvidia,aspm-l0s-entrance-latency-us:
> + description: ASPM L0s entrance latency to be specified in microseconds
> +
> + vddio-pex-ctl-supply:
> + description: A phandle to the regulator supply for PCIe side band signals.
> +
> + nvidia,refclk-select-gpios:
> + description: Must contain a phandle to a GPIO controller followed by GPIO that is being used to
Don't need generic description of the GPIO binding.
> + enable REFCLK to controller from host
> + $ref: /schemas/types.yaml#/definitions/phandle-array
Already has a type.
> +
> +allOf:
> + - $ref: "/schemas/pci/pci-ep.yaml#"
> +
> +unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - num-ib-windows
> + - num-ob-windows
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - power-domains
> + - reset-gpios
> + - num-lanes
> + - phys
> + - phy-names
> + - nvidia,bpmp
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra194-clock.h>
> + #include <dt-bindings/gpio/tegra194-gpio.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/tegra194-powergate.h>
> + #include <dt-bindings/reset/tegra194-reset.h>
> +
> + bus@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x8 0x0>;
> +
> + pcie-ep@141a0000 {
> + compatible = "nvidia,tegra194-pcie-ep";
> + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
> + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
> + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
> + <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
> + reg-names = "appl", "atu_dma", "dbi", "addr_space";
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> + interrupt-names = "intr";
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
> + <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
> + reset-names = "apb", "core";
> +
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&clkreq_c5_bi_dir_state>;
> +
> + nvidia,bpmp = <&bpmp 5>;
> +
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
> +
> + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
> +
> + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
> + GPIO_ACTIVE_HIGH>;
> +
> + num-lanes = <8>;
> + num-ib-windows = <2>;
> + num-ob-windows = <8>;
> +
> + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
> + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
> + <&p2u_nvhs_6>, <&p2u_nvhs_7>;
> +
> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
> + "p2u-5", "p2u-6", "p2u-7";
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> deleted file mode 100644
> index 8e4f9bfb316d..000000000000
> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
> +++ /dev/null
> @@ -1,245 +0,0 @@
> -NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
> -
> -This PCIe controller is based on the Synopsis Designware PCIe IP
> -and thus inherits all the common properties defined in snps,dw-pcie.yaml and
> -snps,dw-pcie-ep.yaml.
> -Some of the controller instances are dual mode where in they can work either
> -in root port mode or endpoint mode but one at a time.
> -
> -Required properties:
> -- power-domains: A phandle to the node that controls power to the respective
> - PCIe controller and a specifier name for the PCIe controller. Following are
> - the specifiers for the different PCIe controllers
> - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
> - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
> - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
> - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
> - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
> - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
> - these specifiers are defined in
> - "include/dt-bindings/power/tegra194-powergate.h" file.
> -- reg: A list of physical base address and length pairs for each set of
> - controller registers. Must contain an entry for each entry in the reg-names
> - property.
> -- reg-names: Must include the following entries:
> - "appl": Controller's application logic registers
> - "config": As per the definition in snps,dw-pcie.yaml
> - "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
> - Translation Unit) registers of the PCIe core are made available
> - for SW access.
> - "dbi": The aperture where root port's own configuration registers are
> - available
> -- interrupts: A list of interrupt outputs of the controller. Must contain an
> - entry for each entry in the interrupt-names property.
> -- interrupt-names: Must include the following entries:
> - "intr": The Tegra interrupt that is asserted for controller interrupts
> -- clocks: Must contain an entry for each entry in clock-names.
> - See ../clocks/clock-bindings.txt for details.
> -- clock-names: Must include the following entries:
> - - core
> -- resets: Must contain an entry for each entry in reset-names.
> - See ../reset/reset.txt for details.
> -- reset-names: Must include the following entries:
> - - apb
> - - core
> -- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
> -- phy-names: Must include an entry for each active lane.
> - "p2u-N": where N ranges from 0 to one less than the total number of lanes
> -- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
> - by controller-id. Following are the controller ids for each controller.
> - 0: C0
> - 1: C1
> - 2: C2
> - 3: C3
> - 4: C4
> - 5: C5
> -- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
> -
> -RC mode:
> -- compatible: Tegra19x must contain "nvidia,tegra194-pcie"
> -- device_type: Must be "pci" for RC mode
> -- interrupt-names: Must include the following entries:
> - "msi": The Tegra interrupt that is asserted when an MSI is received
> -- bus-range: Range of bus numbers associated with this controller
> -- #address-cells: Address representation for root ports (must be 3)
> - - cell 0 specifies the bus and device numbers of the root port:
> - [23:16]: bus number
> - [15:11]: device number
> - - cell 1 denotes the upper 32 address bits and should be 0
> - - cell 2 contains the lower 32 address bits and is used to translate to the
> - CPU address space
> -- #size-cells: Size representation for root ports (must be 2)
> -- ranges: Describes the translation of addresses for root ports and standard
> - PCI regions. The entries must be 7 cells each, where the first three cells
> - correspond to the address as described for the #address-cells property
> - above, the fourth and fifth cells are for the physical CPU address to
> - translate to and the sixth and seventh cells are as described for the
> - #size-cells property above.
> - - Entries setup the mapping for the standard I/O, memory and
> - prefetchable PCI regions. The first cell determines the type of region
> - that is setup:
> - - 0x81000000: I/O memory region
> - - 0x82000000: non-prefetchable memory region
> - - 0xc2000000: prefetchable memory region
> - Please refer to the standard PCI bus binding document for a more detailed
> - explanation.
> -- #interrupt-cells: Size representation for interrupts (must be 1)
> -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> - Please refer to the standard PCI bus binding document for a more detailed
> - explanation.
> -
> -EP mode:
> -In Tegra194, Only controllers C0, C4 & C5 support EP mode.
> -- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
> -- reg-names: Must include the following entries:
> - "addr_space": Used to map remote RC address space
> -- reset-gpios: Must contain a phandle to a GPIO controller followed by
> - GPIO that is being used as PERST input signal. Please refer to pci.txt
> - document.
> -
> -Optional properties:
> -- pinctrl-names: A list of pinctrl state names.
> - It is mandatory for C5 controller and optional for other controllers.
> - - "default": Configures PCIe I/O for proper operation.
> -- pinctrl-0: phandle for the 'default' state of pin configuration.
> - It is mandatory for C5 controller and optional for other controllers.
> -- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
> -- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
> - improve performance when a platform is designed in such a way that it
> - satisfies at least one of the following conditions thereby enabling root
> - port to exchange optimum number of FC (Flow Control) credits with
> - downstream devices
> - 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
> - 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
> - a) speed is Gen-2 and MPS is 256B
> - b) speed is >= Gen-3 with any MPS
> -- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
> - to be specified in microseconds
> -- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
> - specified in microseconds
> -- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
> - specified in microseconds
> -
> -RC mode:
> -- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
> - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
> - in p2972-0000 platform).
> -- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
> - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
> - in p2972-0000 platform).
> -
> -EP mode:
> -- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
> - followed by GPIO that is being used to enable REFCLK to controller from host
> -
> -NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
> -operate in the endpoint mode because of the way the platform is designed.
> -
> -Examples:
> -=========
> -
> -Tegra194 RC mode:
> ------------------
> -
> - pcie@14180000 {
> - compatible = "nvidia,tegra194-pcie";
> - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
> - reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
> - 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
> - 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
> - reg-names = "appl", "config", "atu_dma";
> -
> - #address-cells = <3>;
> - #size-cells = <2>;
> - device_type = "pci";
> - num-lanes = <8>;
> - linux,pci-domain = <0>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
> -
> - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
> - clock-names = "core";
> -
> - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
> - <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
> - reset-names = "apb", "core";
> -
> - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> - interrupt-names = "intr", "msi";
> -
> - #interrupt-cells = <1>;
> - interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> -
> - nvidia,bpmp = <&bpmp 0>;
> -
> - supports-clkreq;
> - nvidia,aspm-cmrt-us = <60>;
> - nvidia,aspm-pwr-on-t-us = <20>;
> - nvidia,aspm-l0s-entrance-latency-us = <3>;
> -
> - bus-range = <0x0 0xff>;
> - ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
> - 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
> - 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
> -
> - vddio-pex-ctl-supply = <&vdd_1v8ao>;
> - vpcie3v3-supply = <&vdd_3v3_pcie>;
> - vpcie12v-supply = <&vdd_12v_pcie>;
> -
> - phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
> - <&p2u_hsio_5>;
> - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
> - };
> -
> -Tegra194 EP mode:
> ------------------
> -
> - pcie-ep@141a0000 {
> - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
> - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
> - reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
> - 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
> - 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
> - 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
> - reg-names = "appl", "atu_dma", "dbi", "addr_space";
> -
> - num-lanes = <8>;
> - num-ib-windows = <2>;
> - num-ob-windows = <8>;
> -
> - pinctrl-names = "default";
> - pinctrl-0 = <&clkreq_c5_bi_dir_state>;
> -
> - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
> - clock-names = "core";
> -
> - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
> - <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
> - reset-names = "apb", "core";
> -
> - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
> - interrupt-names = "intr";
> -
> - nvidia,bpmp = <&bpmp 5>;
> -
> - nvidia,aspm-cmrt-us = <60>;
> - nvidia,aspm-pwr-on-t-us = <20>;
> - nvidia,aspm-l0s-entrance-latency-us = <3>;
> -
> - vddio-pex-ctl-supply = <&vdd_1v8ao>;
> -
> - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
> -
> - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
> - GPIO_ACTIVE_HIGH>;
> -
> - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
> - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
> - <&p2u_nvhs_6>, <&p2u_nvhs_7>;
> -
> - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
> - "p2u-5", "p2u-6", "p2u-7";
> - };
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
> new file mode 100644
> index 000000000000..4a49dddf33bb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
> @@ -0,0 +1,254 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
> +
> +maintainers:
> + - Thierry Reding <thierry.reding@gmail.com>
> + - Jon Hunter <jonathanh@nvidia.com>
> + - Vidya Sagar <vidyas@nvidia.com>
> +
> +description: |
> + This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
> + properties defined in snps,dw-pcie.yaml. Some of the controller instances are dual mode where in
> + they can work either in root port mode or endpoint mode but one at a time.
> +
> + See nvidia,tegra194-pcie-ep.yaml for details on the endpoint mode device tree bindings.
> +
> +properties:
> + compatible:
> + enum:
> + - nvidia,tegra194-pcie
> +
> + reg:
> + items:
> + - description: controller's application logic registers
> + - description: configuration registers
> + - description: iATU and DMA registers. This is where the iATU (internal Address Translation
> + Unit) registers of the PCIe core are made available for software access.
> + - description: The aperture where the root port's own configuration registers are available.
> +
> + reg-names:
> + items:
> + - const: appl
> + - const: config
> + - const: atu_dma
> + - const: dbi
> +
> + interrupts:
> + items:
> + - description: controller interrupt
> + - description: MSI interrupt
> +
> + interrupt-names:
> + items:
> + - const: intr
> + - const: msi
> +
> + clocks:
> + items:
> + - description: module clock
> +
> + clock-names:
> + items:
> + - const: core
> +
> + resets:
> + items:
> + - description: APB bus interface reset
> + - description: module reset
> +
> + reset-names:
> + items:
> + - const: apb
> + - const: core
> +
> + phys:
> + minItems: 1
> + maxItems: 16
> +
> + phy-names:
> + minItems: 1
> + maxItems: 16
> + items:
> + pattern: "^p2u-[0-9]+$"
> +
> + power-domains:
> + description: |
> + A phandle to the node that controls power to the respective PCIe controller and a specifier
> + name for the PCIe controller. Following are the specifiers for the different PCIe
> + controllers:
> +
> + - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
> + - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
> + - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
> +
> + these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
> +
> + interconnects:
> + items:
> + - description: memory read client
> + - description: memory write client
> +
> + interconnect-names:
> + items:
> + - const: dma-mem # read
> + - const: write
> +
> + dma-coherent: true
> +
> + supports-clkreq:
> + description: see pci.txt for details
> +
> + nvidia,bpmp:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
> + are the controller IDs for each controller:
> +
> + 0: C0
> + 1: C1
> + 2: C2
> + 3: C3
> + 4: C4
> + 5: C5
> + items:
> + - items:
> + - minimum: 0
> + maximum: 0xffffffff
> + - enum: [ 0, 1, 2, 3, 4, 5 ]
> +
> + nvidia,update-fc-fixup:
> + description: |
> + This is a boolean property and needs to be present to improve performance when a platform is
> + designed in such a way that it satisfies at least one of the following conditions thereby
> + enabling root port to exchange optimum number of FC (Flow Control) credits with downstream
> + devices:
> +
> + 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
> + 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
> + a) speed is Gen-2 and MPS is 256B
> + b) speed is >= Gen-3 with any MPS
> +
> + $ref: /schemas/types.yaml#/definitions/flag
> +
> + nvidia,aspm-cmrt-us:
> + description: Common Mode Restore Time for proper operation of ASPM to be specified in
> + microseconds
> +
> + nvidia,aspm-pwr-on-t-us:
> + description: Power On time for proper operation of ASPM to be specified in microseconds
> +
> + nvidia,aspm-l0s-entrance-latency-us:
> + description: ASPM L0s entrance latency to be specified in microseconds
> +
> + vddio-pex-ctl-supply:
> + description: A phandle to the regulator supply for PCIe side band signals.
> +
> + vpcie3v3-supply:
> + description: A phandle to the regulator node that supplies 3.3V to the slot if the platform has
> + one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
> +
> + vpcie12v-supply:
> + description: A phandle to the regulator node that supplies 12V to the slot if the platform has
> + one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
> +
> +allOf:
> + - $ref: "/schemas/pci/pci-bus.yaml#"
> + - $ref: "/schemas/pci/snps,dw-pcie.yaml#"
> +
> +unevaluatedProperties: false
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - interrupt-names
> + - interrupt-map
> + - interrupt-map-mask
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - power-domains
> + - bus-range
> + - ranges
> + - vddio-pex-ctl-supply
> + - num-lanes
> + - phys
> + - phy-names
> + - nvidia,bpmp
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/tegra194-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/tegra194-powergate.h>
> + #include <dt-bindings/reset/tegra194-reset.h>
> +
> + bus@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x8 0x0>;
> +
> + pcie@14180000 {
> + compatible = "nvidia,tegra194-pcie";
> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
> + reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
> + <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
> + <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
> + <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <8>;
> + linux,pci-domain = <0>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
> +
> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
> + <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 0>;
> +
> + supports-clkreq;
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
> + <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
> + <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
> +
> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
> + vpcie3v3-supply = <&vdd_3v3_pcie>;
> + vpcie12v-supply = <&vdd_12v_pcie>;
> +
> + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
> + <&p2u_hsio_5>;
> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
> + };
> + };
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> index c90e5e2d25f6..7e0bf941fbfe 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> @@ -35,7 +35,7 @@ properties:
> maxItems: 5
> items:
> enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
> - ulreg, smu, mpu, apb, phy ]
> + ulreg, smu, mpu, apb, phy, appl, atu_dma ]
>
> num-lanes:
> description: |
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-06-30 21:04 ` Rob Herring
@ 2022-07-06 9:53 ` Vidya Sagar
2022-07-06 10:06 ` Krzysztof Kozlowski
2022-07-06 18:11 ` Rob Herring
0 siblings, 2 replies; 27+ messages in thread
From: Vidya Sagar @ 2022-07-06 9:53 UTC (permalink / raw)
To: Rob Herring
Cc: bhelgaas, lorenzo.pieralisi, thierry.reding, jonathanh, kishon,
vkoul, kw, krzk, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv, Thierry Reding
On 7/1/2022 2:34 AM, Rob Herring wrote:
> External email: Use caution opening links or attachments
>
>
> On Wed, Jun 29, 2022 at 11:34:26AM +0530, Vidya Sagar wrote:
>> From: Thierry Reding <treding@nvidia.com>
>>
>> Convert the Tegra194 PCIe bindings from the free-form text format to
>> json-schema.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> ---
>> V3:
>> * New patch in this series. Added as part of addressing Rob's review
>> comment to convert the existing .txt file to .yaml schema
>>
>> .../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 239 ++++++++++++++++
>> .../bindings/pci/nvidia,tegra194-pcie.txt | 245 -----------------
>> .../bindings/pci/nvidia,tegra194-pcie.yaml | 254 ++++++++++++++++++
>> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
>> 4 files changed, 494 insertions(+), 246 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
>> delete mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
>> create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
>> new file mode 100644
>> index 000000000000..4f7cb7fe378e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
>> @@ -0,0 +1,239 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: NVIDIA Tegra194 (and later) PCIe endpoint controller (Synopsys DesignWare Core based)
>> +
>> +maintainers:
>> + - Thierry Reding <thierry.reding@gmail.com>
>> + - Jon Hunter <jonathanh@nvidia.com>
>> + - Vidya Sagar <vidyas@nvidia.com>
>> +
>> +description: |
>> + This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
>
> Wrap lines at 80 unless there's a benefit to a longer line.
>
>> + properties defined in snps,dw-pcie-ep.yaml. Some of the controller instances are dual mode where
>> + in they can work either in root port mode or endpoint mode but one at a time.
>> +
>> + On Tegra194, controllers C0, C4 and C5 support endpoint mode.
>> +
>> + Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the
>> + endpoint mode because of the way the platform is designed.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - nvidia,tegra194-pcie-ep
>> +
>> + reg:
>> + items:
>> + - description: controller's application logic registers
>> + - description: iATU and DMA registers. This is where the iATU (internal Address Translation
>> + Unit) registers of the PCIe core are made available for software access.
>> + - description: The aperture where the root port's own configuration registers are available.
>> + - description: Aperture used to map the remote root-complex' address space.
>> +
>> + reg-names:
>> + items:
>> + - const: appl
>> + - const: atu_dma
>> + - const: dbi
>> + - const: addr_space
>> +
>> + interrupts:
>> + items:
>> + - description: controller interrupt
>
> Just 'maxItems: 1' is enough.
>
>> +
>> + interrupt-names:
>> + items:
>> + - const: intr
>> +
>> + clocks:
>> + items:
>> + - description: module clock
>> +
>> + clock-names:
>> + items:
>> + - const: core
>> +
>> + resets:
>> + items:
>> + - description: APB bus interface reset
>> + - description: module reset
>> +
>> + reset-names:
>> + items:
>> + - const: apb
>> + - const: core
>> +
>> + reset-gpios:
>> + description: Must contain a phandle to a GPIO controller followed by GPIO that is being used as
>> + PERST input signal. Please refer to pci.txt document.
>> +
>> + phys:
>> + minItems: 1
>> + maxItems: 16
>
> One per lane?
>
>> +
>> + phy-names:
>> + minItems: 1
>> + maxItems: 16
>> + items:
>> + pattern: "^p2u-[0-9]+$"
>> +
>> + power-domains:
>> + description: |
>> + A phandle to the node that controls power to the respective PCIe controller and a specifier
>> + name for the PCIe controller. Following are the specifiers for the different PCIe
>> + controllers:
>> +
>> + - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
>> + - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
>> + - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
>> +
>> + these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
>> +
>> + interconnects:
>> + items:
>> + - description: memory read client
>> + - description: memory write client
>> +
>> + interconnect-names:
>> + items:
>> + - const: dma-mem # read
>> + - const: write
>> +
>> + dma-coherent: true
>> +
>> + num-ib-windows:
>> + description: number of inbound address translation windows
>> + maxItems: 1
>> + deprecated: true
>> +
>> + num-ob-windows:
>> + description: number of outbound address translation windows
>> + maxItems: 1
>> + deprecated: true
>> +
>> + nvidia,bpmp:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description: |
>> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
>> + are the controller IDs for each controller:
>> +
>> + 0: C0
>> + 1: C1
>> + 2: C2
>> + 3: C3
>> + 4: C4
>> + 5: C5
>> + items:
>> + - items:
>> + - minimum: 0
>> + maximum: 0xffffffff
>
> That's already the limit. Just a description is fine.
>
>> + - enum: [ 0, 1, 2, 3, 4, 5 ]
>
> maximum: 5
Setting the maximum to '5' is resulting in the following error.
pcie-ep@141a0000: nvidia,bpmp:0:0: 4294967295 is greater than the
maximum of 5
Could you please help me understand why I'm seeing this error?
Thanks,
Vidya Sagar
>
>> +
>> + nvidia,aspm-cmrt-us:
>> + description: Common Mode Restore Time for proper operation of ASPM to be specified in
>> + microseconds
>> +
>> + nvidia,aspm-pwr-on-t-us:
>> + description: Power On time for proper operation of ASPM to be specified in microseconds
>> +
>> + nvidia,aspm-l0s-entrance-latency-us:
>> + description: ASPM L0s entrance latency to be specified in microseconds
>> +
>> + vddio-pex-ctl-supply:
>> + description: A phandle to the regulator supply for PCIe side band signals.
>> +
>> + nvidia,refclk-select-gpios:
>> + description: Must contain a phandle to a GPIO controller followed by GPIO that is being used to
>
> Don't need generic description of the GPIO binding.
>
>> + enable REFCLK to controller from host
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>
> Already has a type.
>
>> +
>> +allOf:
>> + - $ref: "/schemas/pci/pci-ep.yaml#"
>> +
>> +unevaluatedProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - num-ib-windows
>> + - num-ob-windows
>> + - interrupts
>> + - interrupt-names
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - power-domains
>> + - reset-gpios
>> + - num-lanes
>> + - phys
>> + - phy-names
>> + - nvidia,bpmp
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/tegra194-clock.h>
>> + #include <dt-bindings/gpio/tegra194-gpio.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/power/tegra194-powergate.h>
>> + #include <dt-bindings/reset/tegra194-reset.h>
>> +
>> + bus@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x0 0x0 0x0 0x8 0x0>;
>> +
>> + pcie-ep@141a0000 {
>> + compatible = "nvidia,tegra194-pcie-ep";
>> + reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
>> + <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> + <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
>> + <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> + reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> + interrupt-names = "intr";
>> +
>> + clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> + clock-names = "core";
>> +
>> + resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> + <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> + reset-names = "apb", "core";
>> +
>> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&clkreq_c5_bi_dir_state>;
>> +
>> + nvidia,bpmp = <&bpmp 5>;
>> +
>> + nvidia,aspm-cmrt-us = <60>;
>> + nvidia,aspm-pwr-on-t-us = <20>;
>> + nvidia,aspm-l0s-entrance-latency-us = <3>;
>> +
>> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
>> +
>> + reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
>> +
>> + nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
>> + GPIO_ACTIVE_HIGH>;
>> +
>> + num-lanes = <8>;
>> + num-ib-windows = <2>;
>> + num-ob-windows = <8>;
>> +
>> + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
>> + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
>> + <&p2u_nvhs_6>, <&p2u_nvhs_7>;
>> +
>> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
>> + "p2u-5", "p2u-6", "p2u-7";
>> + };
>> + };
>> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
>> deleted file mode 100644
>> index 8e4f9bfb316d..000000000000
>> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
>> +++ /dev/null
>> @@ -1,245 +0,0 @@
>> -NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
>> -
>> -This PCIe controller is based on the Synopsis Designware PCIe IP
>> -and thus inherits all the common properties defined in snps,dw-pcie.yaml and
>> -snps,dw-pcie-ep.yaml.
>> -Some of the controller instances are dual mode where in they can work either
>> -in root port mode or endpoint mode but one at a time.
>> -
>> -Required properties:
>> -- power-domains: A phandle to the node that controls power to the respective
>> - PCIe controller and a specifier name for the PCIe controller. Following are
>> - the specifiers for the different PCIe controllers
>> - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
>> - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
>> - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
>> - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
>> - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
>> - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
>> - these specifiers are defined in
>> - "include/dt-bindings/power/tegra194-powergate.h" file.
>> -- reg: A list of physical base address and length pairs for each set of
>> - controller registers. Must contain an entry for each entry in the reg-names
>> - property.
>> -- reg-names: Must include the following entries:
>> - "appl": Controller's application logic registers
>> - "config": As per the definition in snps,dw-pcie.yaml
>> - "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
>> - Translation Unit) registers of the PCIe core are made available
>> - for SW access.
>> - "dbi": The aperture where root port's own configuration registers are
>> - available
>> -- interrupts: A list of interrupt outputs of the controller. Must contain an
>> - entry for each entry in the interrupt-names property.
>> -- interrupt-names: Must include the following entries:
>> - "intr": The Tegra interrupt that is asserted for controller interrupts
>> -- clocks: Must contain an entry for each entry in clock-names.
>> - See ../clocks/clock-bindings.txt for details.
>> -- clock-names: Must include the following entries:
>> - - core
>> -- resets: Must contain an entry for each entry in reset-names.
>> - See ../reset/reset.txt for details.
>> -- reset-names: Must include the following entries:
>> - - apb
>> - - core
>> -- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
>> -- phy-names: Must include an entry for each active lane.
>> - "p2u-N": where N ranges from 0 to one less than the total number of lanes
>> -- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
>> - by controller-id. Following are the controller ids for each controller.
>> - 0: C0
>> - 1: C1
>> - 2: C2
>> - 3: C3
>> - 4: C4
>> - 5: C5
>> -- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
>> -
>> -RC mode:
>> -- compatible: Tegra19x must contain "nvidia,tegra194-pcie"
>> -- device_type: Must be "pci" for RC mode
>> -- interrupt-names: Must include the following entries:
>> - "msi": The Tegra interrupt that is asserted when an MSI is received
>> -- bus-range: Range of bus numbers associated with this controller
>> -- #address-cells: Address representation for root ports (must be 3)
>> - - cell 0 specifies the bus and device numbers of the root port:
>> - [23:16]: bus number
>> - [15:11]: device number
>> - - cell 1 denotes the upper 32 address bits and should be 0
>> - - cell 2 contains the lower 32 address bits and is used to translate to the
>> - CPU address space
>> -- #size-cells: Size representation for root ports (must be 2)
>> -- ranges: Describes the translation of addresses for root ports and standard
>> - PCI regions. The entries must be 7 cells each, where the first three cells
>> - correspond to the address as described for the #address-cells property
>> - above, the fourth and fifth cells are for the physical CPU address to
>> - translate to and the sixth and seventh cells are as described for the
>> - #size-cells property above.
>> - - Entries setup the mapping for the standard I/O, memory and
>> - prefetchable PCI regions. The first cell determines the type of region
>> - that is setup:
>> - - 0x81000000: I/O memory region
>> - - 0x82000000: non-prefetchable memory region
>> - - 0xc2000000: prefetchable memory region
>> - Please refer to the standard PCI bus binding document for a more detailed
>> - explanation.
>> -- #interrupt-cells: Size representation for interrupts (must be 1)
>> -- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
>> - Please refer to the standard PCI bus binding document for a more detailed
>> - explanation.
>> -
>> -EP mode:
>> -In Tegra194, Only controllers C0, C4 & C5 support EP mode.
>> -- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
>> -- reg-names: Must include the following entries:
>> - "addr_space": Used to map remote RC address space
>> -- reset-gpios: Must contain a phandle to a GPIO controller followed by
>> - GPIO that is being used as PERST input signal. Please refer to pci.txt
>> - document.
>> -
>> -Optional properties:
>> -- pinctrl-names: A list of pinctrl state names.
>> - It is mandatory for C5 controller and optional for other controllers.
>> - - "default": Configures PCIe I/O for proper operation.
>> -- pinctrl-0: phandle for the 'default' state of pin configuration.
>> - It is mandatory for C5 controller and optional for other controllers.
>> -- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
>> -- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
>> - improve performance when a platform is designed in such a way that it
>> - satisfies at least one of the following conditions thereby enabling root
>> - port to exchange optimum number of FC (Flow Control) credits with
>> - downstream devices
>> - 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
>> - 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
>> - a) speed is Gen-2 and MPS is 256B
>> - b) speed is >= Gen-3 with any MPS
>> -- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
>> - to be specified in microseconds
>> -- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
>> - specified in microseconds
>> -- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
>> - specified in microseconds
>> -
>> -RC mode:
>> -- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
>> - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
>> - in p2972-0000 platform).
>> -- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
>> - if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
>> - in p2972-0000 platform).
>> -
>> -EP mode:
>> -- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
>> - followed by GPIO that is being used to enable REFCLK to controller from host
>> -
>> -NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
>> -operate in the endpoint mode because of the way the platform is designed.
>> -
>> -Examples:
>> -=========
>> -
>> -Tegra194 RC mode:
>> ------------------
>> -
>> - pcie@14180000 {
>> - compatible = "nvidia,tegra194-pcie";
>> - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> - reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
>> - 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
>> - 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */
>> - reg-names = "appl", "config", "atu_dma";
>> -
>> - #address-cells = <3>;
>> - #size-cells = <2>;
>> - device_type = "pci";
>> - num-lanes = <8>;
>> - linux,pci-domain = <0>;
>> -
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
>> -
>> - clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> - clock-names = "core";
>> -
>> - resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> - <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> - reset-names = "apb", "core";
>> -
>> - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> - <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> - interrupt-names = "intr", "msi";
>> -
>> - #interrupt-cells = <1>;
>> - interrupt-map-mask = <0 0 0 0>;
>> - interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> -
>> - nvidia,bpmp = <&bpmp 0>;
>> -
>> - supports-clkreq;
>> - nvidia,aspm-cmrt-us = <60>;
>> - nvidia,aspm-pwr-on-t-us = <20>;
>> - nvidia,aspm-l0s-entrance-latency-us = <3>;
>> -
>> - bus-range = <0x0 0xff>;
>> - ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
>> - 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */
>> - 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */
>> -
>> - vddio-pex-ctl-supply = <&vdd_1v8ao>;
>> - vpcie3v3-supply = <&vdd_3v3_pcie>;
>> - vpcie12v-supply = <&vdd_12v_pcie>;
>> -
>> - phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
>> - <&p2u_hsio_5>;
>> - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
>> - };
>> -
>> -Tegra194 EP mode:
>> ------------------
>> -
>> - pcie-ep@141a0000 {
>> - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
>> - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
>> - reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
>> - 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
>> - 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
>> - 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
>> - reg-names = "appl", "atu_dma", "dbi", "addr_space";
>> -
>> - num-lanes = <8>;
>> - num-ib-windows = <2>;
>> - num-ob-windows = <8>;
>> -
>> - pinctrl-names = "default";
>> - pinctrl-0 = <&clkreq_c5_bi_dir_state>;
>> -
>> - clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
>> - clock-names = "core";
>> -
>> - resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
>> - <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
>> - reset-names = "apb", "core";
>> -
>> - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
>> - interrupt-names = "intr";
>> -
>> - nvidia,bpmp = <&bpmp 5>;
>> -
>> - nvidia,aspm-cmrt-us = <60>;
>> - nvidia,aspm-pwr-on-t-us = <20>;
>> - nvidia,aspm-l0s-entrance-latency-us = <3>;
>> -
>> - vddio-pex-ctl-supply = <&vdd_1v8ao>;
>> -
>> - reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
>> -
>> - nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
>> - GPIO_ACTIVE_HIGH>;
>> -
>> - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
>> - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
>> - <&p2u_nvhs_6>, <&p2u_nvhs_7>;
>> -
>> - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
>> - "p2u-5", "p2u-6", "p2u-7";
>> - };
>> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
>> new file mode 100644
>> index 000000000000..4a49dddf33bb
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
>> @@ -0,0 +1,254 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
>> +
>> +maintainers:
>> + - Thierry Reding <thierry.reding@gmail.com>
>> + - Jon Hunter <jonathanh@nvidia.com>
>> + - Vidya Sagar <vidyas@nvidia.com>
>> +
>> +description: |
>> + This PCIe controller is based on the Synopsis Designware PCIe IP and thus inherits all the common
>> + properties defined in snps,dw-pcie.yaml. Some of the controller instances are dual mode where in
>> + they can work either in root port mode or endpoint mode but one at a time.
>> +
>> + See nvidia,tegra194-pcie-ep.yaml for details on the endpoint mode device tree bindings.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - nvidia,tegra194-pcie
>> +
>> + reg:
>> + items:
>> + - description: controller's application logic registers
>> + - description: configuration registers
>> + - description: iATU and DMA registers. This is where the iATU (internal Address Translation
>> + Unit) registers of the PCIe core are made available for software access.
>> + - description: The aperture where the root port's own configuration registers are available.
>> +
>> + reg-names:
>> + items:
>> + - const: appl
>> + - const: config
>> + - const: atu_dma
>> + - const: dbi
>> +
>> + interrupts:
>> + items:
>> + - description: controller interrupt
>> + - description: MSI interrupt
>> +
>> + interrupt-names:
>> + items:
>> + - const: intr
>> + - const: msi
>> +
>> + clocks:
>> + items:
>> + - description: module clock
>> +
>> + clock-names:
>> + items:
>> + - const: core
>> +
>> + resets:
>> + items:
>> + - description: APB bus interface reset
>> + - description: module reset
>> +
>> + reset-names:
>> + items:
>> + - const: apb
>> + - const: core
>> +
>> + phys:
>> + minItems: 1
>> + maxItems: 16
>> +
>> + phy-names:
>> + minItems: 1
>> + maxItems: 16
>> + items:
>> + pattern: "^p2u-[0-9]+$"
>> +
>> + power-domains:
>> + description: |
>> + A phandle to the node that controls power to the respective PCIe controller and a specifier
>> + name for the PCIe controller. Following are the specifiers for the different PCIe
>> + controllers:
>> +
>> + - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
>> + - TEGRA194_POWER_DOMAIN_PCIEX1A: C3
>> + - TEGRA194_POWER_DOMAIN_PCIEX4A: C4
>> + - TEGRA194_POWER_DOMAIN_PCIEX8A: C5
>> +
>> + these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
>> +
>> + interconnects:
>> + items:
>> + - description: memory read client
>> + - description: memory write client
>> +
>> + interconnect-names:
>> + items:
>> + - const: dma-mem # read
>> + - const: write
>> +
>> + dma-coherent: true
>> +
>> + supports-clkreq:
>> + description: see pci.txt for details
>> +
>> + nvidia,bpmp:
>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>> + description: |
>> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
>> + are the controller IDs for each controller:
>> +
>> + 0: C0
>> + 1: C1
>> + 2: C2
>> + 3: C3
>> + 4: C4
>> + 5: C5
>> + items:
>> + - items:
>> + - minimum: 0
>> + maximum: 0xffffffff
>> + - enum: [ 0, 1, 2, 3, 4, 5 ]
>> +
>> + nvidia,update-fc-fixup:
>> + description: |
>> + This is a boolean property and needs to be present to improve performance when a platform is
>> + designed in such a way that it satisfies at least one of the following conditions thereby
>> + enabling root port to exchange optimum number of FC (Flow Control) credits with downstream
>> + devices:
>> +
>> + 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
>> + 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
>> + a) speed is Gen-2 and MPS is 256B
>> + b) speed is >= Gen-3 with any MPS
>> +
>> + $ref: /schemas/types.yaml#/definitions/flag
>> +
>> + nvidia,aspm-cmrt-us:
>> + description: Common Mode Restore Time for proper operation of ASPM to be specified in
>> + microseconds
>> +
>> + nvidia,aspm-pwr-on-t-us:
>> + description: Power On time for proper operation of ASPM to be specified in microseconds
>> +
>> + nvidia,aspm-l0s-entrance-latency-us:
>> + description: ASPM L0s entrance latency to be specified in microseconds
>> +
>> + vddio-pex-ctl-supply:
>> + description: A phandle to the regulator supply for PCIe side band signals.
>> +
>> + vpcie3v3-supply:
>> + description: A phandle to the regulator node that supplies 3.3V to the slot if the platform has
>> + one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
>> +
>> + vpcie12v-supply:
>> + description: A phandle to the regulator node that supplies 12V to the slot if the platform has
>> + one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
>> +
>> +allOf:
>> + - $ref: "/schemas/pci/pci-bus.yaml#"
>> + - $ref: "/schemas/pci/snps,dw-pcie.yaml#"
>> +
>> +unevaluatedProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - interrupts
>> + - interrupt-names
>> + - interrupt-map
>> + - interrupt-map-mask
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - power-domains
>> + - bus-range
>> + - ranges
>> + - vddio-pex-ctl-supply
>> + - num-lanes
>> + - phys
>> + - phy-names
>> + - nvidia,bpmp
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/tegra194-clock.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/power/tegra194-powergate.h>
>> + #include <dt-bindings/reset/tegra194-reset.h>
>> +
>> + bus@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x0 0x0 0x0 0x8 0x0>;
>> +
>> + pcie@14180000 {
>> + compatible = "nvidia,tegra194-pcie";
>> + power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
>> + reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
>> + <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
>> + <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
>> + <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
>> + reg-names = "appl", "config", "atu_dma", "dbi";
>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + device_type = "pci";
>> + num-lanes = <8>;
>> + linux,pci-domain = <0>;
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
>> +
>> + clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
>> + clock-names = "core";
>> +
>> + resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
>> + <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
>> + reset-names = "apb", "core";
>> +
>> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
>> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
>> + interrupt-names = "intr", "msi";
>> +
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0>;
>> + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + nvidia,bpmp = <&bpmp 0>;
>> +
>> + supports-clkreq;
>> + nvidia,aspm-cmrt-us = <60>;
>> + nvidia,aspm-pwr-on-t-us = <20>;
>> + nvidia,aspm-l0s-entrance-latency-us = <3>;
>> +
>> + bus-range = <0x0 0xff>;
>> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
>> + <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
>> + <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
>> +
>> + vddio-pex-ctl-supply = <&vdd_1v8ao>;
>> + vpcie3v3-supply = <&vdd_3v3_pcie>;
>> + vpcie12v-supply = <&vdd_12v_pcie>;
>> +
>> + phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
>> + <&p2u_hsio_5>;
>> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
>> + };
>> + };
>> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
>> index c90e5e2d25f6..7e0bf941fbfe 100644
>> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
>> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
>> @@ -35,7 +35,7 @@ properties:
>> maxItems: 5
>> items:
>> enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
>> - ulreg, smu, mpu, apb, phy ]
>> + ulreg, smu, mpu, apb, phy, appl, atu_dma ]
>>
>> num-lanes:
>> description: |
>> --
>> 2.17.1
>>
>>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-07-06 9:53 ` Vidya Sagar
@ 2022-07-06 10:06 ` Krzysztof Kozlowski
2022-07-06 10:46 ` Vidya Sagar
2022-07-06 18:11 ` Rob Herring
1 sibling, 1 reply; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-06 10:06 UTC (permalink / raw)
To: Vidya Sagar, Rob Herring
Cc: bhelgaas, lorenzo.pieralisi, thierry.reding, jonathanh, kishon,
vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv, Thierry Reding
On 06/07/2022 11:53, Vidya Sagar wrote:
>>> + nvidia,bpmp:
>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>> + description: |
>>> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
>>> + are the controller IDs for each controller:
>>> +
>>> + 0: C0
>>> + 1: C1
>>> + 2: C2
>>> + 3: C3
>>> + 4: C4
>>> + 5: C5
>>> + items:
>>> + - items:
>>> + - minimum: 0
>>> + maximum: 0xffffffff
>>
>> That's already the limit. Just a description is fine.
>>
>>> + - enum: [ 0, 1, 2, 3, 4, 5 ]
>>
>> maximum: 5
>
> Setting the maximum to '5' is resulting in the following error.
>
> pcie-ep@141a0000: nvidia,bpmp:0:0: 4294967295 is greater than the
> maximum of 5
>
> Could you please help me understand why I'm seeing this error?
Trim your replies.
Why adding minimum:5 to the phandle? Rob said add a description. Nothing
about minimum.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-07-06 10:06 ` Krzysztof Kozlowski
@ 2022-07-06 10:46 ` Vidya Sagar
2022-07-06 15:06 ` Krzysztof Kozlowski
0 siblings, 1 reply; 27+ messages in thread
From: Vidya Sagar @ 2022-07-06 10:46 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring
Cc: bhelgaas, lorenzo.pieralisi, thierry.reding, jonathanh, kishon,
vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv, Thierry Reding
On 7/6/2022 3:36 PM, Krzysztof Kozlowski wrote:
> External email: Use caution opening links or attachments
>
>
> On 06/07/2022 11:53, Vidya Sagar wrote:
>>>> + nvidia,bpmp:
>>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>>> + description: |
>>>> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
>>>> + are the controller IDs for each controller:
>>>> +
>>>> + 0: C0
>>>> + 1: C1
>>>> + 2: C2
>>>> + 3: C3
>>>> + 4: C4
>>>> + 5: C5
>>>> + items:
>>>> + - items:
>>>> + - minimum: 0
>>>> + maximum: 0xffffffff
>>>
>>> That's already the limit. Just a description is fine.
>>>
>>>> + - enum: [ 0, 1, 2, 3, 4, 5 ]
>>>
>>> maximum: 5
>>
>> Setting the maximum to '5' is resulting in the following error.
>>
>> pcie-ep@141a0000: nvidia,bpmp:0:0: 4294967295 is greater than the
>> maximum of 5
>>
>> Could you please help me understand why I'm seeing this error?
>
> Trim your replies.
>
> Why adding minimum:5 to the phandle? Rob said add a description. Nothing
> about minimum.
I'm sorry I didn't understand the review comment clearly.
There is one description added above already. Are you (and Rob) saying
that one more description is needed?
Thanks,
Vidya Sagar
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-07-06 10:46 ` Vidya Sagar
@ 2022-07-06 15:06 ` Krzysztof Kozlowski
0 siblings, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-06 15:06 UTC (permalink / raw)
To: Vidya Sagar, Rob Herring
Cc: bhelgaas, lorenzo.pieralisi, thierry.reding, jonathanh, kishon,
vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv, Thierry Reding
On 06/07/2022 12:46, Vidya Sagar wrote:
>
>
> On 7/6/2022 3:36 PM, Krzysztof Kozlowski wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On 06/07/2022 11:53, Vidya Sagar wrote:
>>>>> + nvidia,bpmp:
>>>>> + $ref: /schemas/types.yaml#/definitions/phandle-array
>>>>> + description: |
>>>>> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
>>>>> + are the controller IDs for each controller:
>>>>> +
>>>>> + 0: C0
>>>>> + 1: C1
>>>>> + 2: C2
>>>>> + 3: C3
>>>>> + 4: C4
>>>>> + 5: C5
>>>>> + items:
>>>>> + - items:
>>>>> + - minimum: 0
>>>>> + maximum: 0xffffffff
>>>>
>>>> That's already the limit. Just a description is fine.
>>>>
>>>>> + - enum: [ 0, 1, 2, 3, 4, 5 ]
>>>>
>>>> maximum: 5
>>>
>>> Setting the maximum to '5' is resulting in the following error.
>>>
>>> pcie-ep@141a0000: nvidia,bpmp:0:0: 4294967295 is greater than the
>>> maximum of 5
>>>
>>> Could you please help me understand why I'm seeing this error?
>>
>> Trim your replies.
>>
>> Why adding minimum:5 to the phandle? Rob said add a description. Nothing
>> about minimum.
>
> I'm sorry I didn't understand the review comment clearly.
> There is one description added above already. Are you (and Rob) saying
> that one more description is needed?
You have description of entire property. The property consists of
phandles ("items", with only one item) and each phandle of two items
(second nested "items"). The first item in phandle is actual phandle, so
it does not need any constraints/schema, just a description. This was
missing.
Something like this:
https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42
except that in your case second item (in the nested items) have actual
schema, not description, which is good.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema
2022-07-06 9:53 ` Vidya Sagar
2022-07-06 10:06 ` Krzysztof Kozlowski
@ 2022-07-06 18:11 ` Rob Herring
1 sibling, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-07-06 18:11 UTC (permalink / raw)
To: Vidya Sagar
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Thierry Reding, Jon Hunter,
Kishon Vijay Abraham I, Vinod, Krzysztof Wilczynski,
Krzysztof Kozlowski, Philipp Zabel, Mikko Perttunen, PCI,
devicetree, linux-tegra, linux-kernel,
open list:GENERIC PHY FRAMEWORK, Krishna Thota,
Manikanta Maddireddy, sagar.tv, Thierry Reding
On Wed, Jul 6, 2022 at 3:53 AM Vidya Sagar <vidyas@nvidia.com> wrote:
>
>
>
> On 7/1/2022 2:34 AM, Rob Herring wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Wed, Jun 29, 2022 at 11:34:26AM +0530, Vidya Sagar wrote:
> >> From: Thierry Reding <treding@nvidia.com>
> >>
> >> Convert the Tegra194 PCIe bindings from the free-form text format to
> >> json-schema.
> >>
> >> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> >> Signed-off-by: Thierry Reding <treding@nvidia.com>
> >> ---
> >> + nvidia,bpmp:
> >> + $ref: /schemas/types.yaml#/definitions/phandle-array
> >> + description: |
> >> + Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
> >> + are the controller IDs for each controller:
> >> +
> >> + 0: C0
> >> + 1: C1
> >> + 2: C2
> >> + 3: C3
> >> + 4: C4
> >> + 5: C5
> >> + items:
> >> + - items:
> >> + - minimum: 0
> >> + maximum: 0xffffffff
> >
> > That's already the limit. Just a description is fine.
> >
> >> + - enum: [ 0, 1, 2, 3, 4, 5 ]
> >
> > maximum: 5
>
> Setting the maximum to '5' is resulting in the following error.
>
> pcie-ep@141a0000: nvidia,bpmp:0:0: 4294967295 is greater than the
> maximum of 5
>
> Could you please help me understand why I'm seeing this error?
This is what you need:
items:
- items:
- description: phandle to BPMP controller node
- description: controller ID
maximum: 5
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V3 03/11] dt-bindings: PCI: tegra234: Add schema for tegra234 rootport mode
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
2022-06-29 6:04 ` [PATCH V3 01/11] dt-bindings: PHY: P2U: Add support for Tegra234 P2U block Vidya Sagar
2022-06-29 6:04 ` [PATCH V3 02/11] dt-bindings: pci: tegra: Convert to json-schema Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-06-29 6:32 ` Krzysztof Kozlowski
2022-06-29 6:04 ` [PATCH V3 04/11] dt-bindings: PCI: tegra234: Add schema for tegra234 endpoint mode Vidya Sagar
` (7 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
Add support for PCIe controllers that operate in the rootport mode
in tegra234 chipset.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* New patch in this series
.../bindings/pci/nvidia,tegra194-pcie.yaml | 151 +++++++++++++++++-
1 file changed, 146 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
index 4a49dddf33bb..ede53baa1d71 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
@@ -22,6 +22,7 @@ properties:
compatible:
enum:
- nvidia,tegra194-pcie
+ - nvidia,tegra234-pcie
reg:
items:
@@ -82,6 +83,8 @@ properties:
name for the PCIe controller. Following are the specifiers for the different PCIe
controllers:
+ Tegra194
+
- TEGRA194_POWER_DOMAIN_PCIEX8B: C0
- TEGRA194_POWER_DOMAIN_PCIEX1A: C1
- TEGRA194_POWER_DOMAIN_PCIEX1A: C2
@@ -91,6 +94,22 @@ properties:
these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
+ Tegra234
+
+ - TEGRA234_POWER_DOMAIN_PCIEX4BA: C0
+ - TEGRA234_POWER_DOMAIN_PCIEX1A : C1
+ - TEGRA234_POWER_DOMAIN_PCIEX1A : C2
+ - TEGRA234_POWER_DOMAIN_PCIEX1A : C3
+ - TEGRA234_POWER_DOMAIN_PCIEX4BB: C4
+ - TEGRA234_POWER_DOMAIN_PCIEX8A : C5
+ - TEGRA234_POWER_DOMAIN_PCIEX4A : C6
+ - TEGRA234_POWER_DOMAIN_PCIEX8B : C7
+ - TEGRA234_POWER_DOMAIN_PCIEX4CA: C8
+ - TEGRA234_POWER_DOMAIN_PCIEX4CB: C9
+ - TEGRA234_POWER_DOMAIN_PCIEX4CC: C10
+
+ these specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h" file.
+
interconnects:
items:
- description: memory read client
@@ -112,17 +131,30 @@ properties:
Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
are the controller IDs for each controller:
+ Tegra194
+
0: C0
1: C1
2: C2
3: C3
4: C4
5: C5
- items:
- - items:
- - minimum: 0
- maximum: 0xffffffff
- - enum: [ 0, 1, 2, 3, 4, 5 ]
+
+ Tegra234
+
+ 0 : C0
+ 1 : C1
+ 2 : C2
+ 3 : C3
+ 4 : C4
+ 5 : C5
+ 6 : C6
+ 7 : C7
+ 8 : C8
+ 9 : C9
+ 10: C10
+
+ Platform constraints are described later
nvidia,update-fc-fixup:
description: |
@@ -131,6 +163,8 @@ properties:
enabling root port to exchange optimum number of FC (Flow Control) credits with downstream
devices:
+ NOTE:- This is applicable only for Tegra194.
+
1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
a) speed is Gen-2 and MPS is 256B
@@ -159,10 +193,56 @@ properties:
description: A phandle to the regulator node that supplies 12V to the slot if the platform has
one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
+ nvidia,enable-srns:
+ description: |
+ This boolean property needs to be present if the controller is configured
+ to operate in SRNS (Separate Reference Clocks with No Spread-Spectrum Clocking).
+ NOTE:- This is applicable only for Tegra234.
+
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ nvidia,enable-ext-refclk:
+ description: |
+ This boolean property needs to be present if the controller is configured
+ to use the reference clocking coming in from an external clock source instead of
+ using the internal clock source.
+
+ $ref: /schemas/types.yaml#/definitions/flag
+
allOf:
- $ref: "/schemas/pci/pci-bus.yaml#"
- $ref: "/schemas/pci/snps,dw-pcie.yaml#"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra194-pcie
+ then:
+ properties:
+ nvidia,bpmp:
+ items:
+ - items:
+ - minimum: 0
+ maximum: 0xffffffff
+ - enum: [ 0, 1, 2, 3, 4, 5 ]
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra234-pcie
+ then:
+ properties:
+ nvidia,bpmp:
+ items:
+ - items:
+ - minimum: 0
+ maximum: 0xffffffff
+ - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ]
+
unevaluatedProperties: false
required:
@@ -252,3 +332,64 @@ examples:
phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
};
};
+
+ - |
+ #include <dt-bindings/clock/tegra234-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/tegra234-powergate.h>
+ #include <dt-bindings/reset/tegra234-reset.h>
+
+ bus@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+ pcie@14160000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
+ reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ linux,pci-domain = <4>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
+ <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 4>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+ ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */
+ <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
+ <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */
+
+ vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
+
+ phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+ <&p2u_hsio_7>;
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH V3 03/11] dt-bindings: PCI: tegra234: Add schema for tegra234 rootport mode
2022-06-29 6:04 ` [PATCH V3 03/11] dt-bindings: PCI: tegra234: Add schema for tegra234 rootport mode Vidya Sagar
@ 2022-06-29 6:32 ` Krzysztof Kozlowski
0 siblings, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-29 6:32 UTC (permalink / raw)
To: Vidya Sagar, bhelgaas, lorenzo.pieralisi, robh+dt,
thierry.reding, jonathanh
Cc: kishon, vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv
On 29/06/2022 08:04, Vidya Sagar wrote:
> Add support for PCIe controllers that operate in the rootport mode
> in tegra234 chipset.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V3:
> * New patch in this series
>
> .../bindings/pci/nvidia,tegra194-pcie.yaml | 151 +++++++++++++++++-
> 1 file changed, 146 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
> index 4a49dddf33bb..ede53baa1d71 100644
> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml
> @@ -22,6 +22,7 @@ properties:
> compatible:
> enum:
> - nvidia,tegra194-pcie
> + - nvidia,tegra234-pcie
>
> reg:
> items:
> @@ -82,6 +83,8 @@ properties:
> name for the PCIe controller. Following are the specifiers for the different PCIe
> controllers:
>
> + Tegra194
> +
> - TEGRA194_POWER_DOMAIN_PCIEX8B: C0
> - TEGRA194_POWER_DOMAIN_PCIEX1A: C1
> - TEGRA194_POWER_DOMAIN_PCIEX1A: C2
> @@ -91,6 +94,22 @@ properties:
>
> these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
>
> + Tegra234
> +
> + - TEGRA234_POWER_DOMAIN_PCIEX4BA: C0
> + - TEGRA234_POWER_DOMAIN_PCIEX1A : C1
> + - TEGRA234_POWER_DOMAIN_PCIEX1A : C2
> + - TEGRA234_POWER_DOMAIN_PCIEX1A : C3
> + - TEGRA234_POWER_DOMAIN_PCIEX4BB: C4
> + - TEGRA234_POWER_DOMAIN_PCIEX8A : C5
> + - TEGRA234_POWER_DOMAIN_PCIEX4A : C6
> + - TEGRA234_POWER_DOMAIN_PCIEX8B : C7
> + - TEGRA234_POWER_DOMAIN_PCIEX4CA: C8
> + - TEGRA234_POWER_DOMAIN_PCIEX4CB: C9
> + - TEGRA234_POWER_DOMAIN_PCIEX4CC: C10
Why duplicating header?
> +
> + these specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h" file.
> +
> interconnects:
> items:
> - description: memory read client
> @@ -112,17 +131,30 @@ properties:
> Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
> are the controller IDs for each controller:
>
> + Tegra194
> +
> 0: C0
> 1: C1
> 2: C2
> 3: C3
> 4: C4
> 5: C5
> - items:
> - - items:
> - - minimum: 0
> - maximum: 0xffffffff
> - - enum: [ 0, 1, 2, 3, 4, 5 ]
> +
> + Tegra234
> +
> + 0 : C0
> + 1 : C1
> + 2 : C2
> + 3 : C3
> + 4 : C4
> + 5 : C5
> + 6 : C6
> + 7 : C7
> + 8 : C8
> + 9 : C9
> + 10: C10
> +
> + Platform constraints are described later
>
> nvidia,update-fc-fixup:
> description: |
> @@ -131,6 +163,8 @@ properties:
> enabling root port to exchange optimum number of FC (Flow Control) credits with downstream
> devices:
>
> + NOTE:- This is applicable only for Tegra194.
> +
Then make it false in other variants in allOf:if:then
> 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
> 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
> a) speed is Gen-2 and MPS is 256B
> @@ -159,10 +193,56 @@ properties:
> description: A phandle to the regulator node that supplies 12V to the slot if the platform has
> one such slot. (Ex:- x16 slot owned by C5 controller in p2972-0000 platform).
>
> + nvidia,enable-srns:
> + description: |
> + This boolean property needs to be present if the controller is configured
Remove "This boolean property needs to be present" and instead describe
the feature behind, e.g. "Configure the controller to operate in SRNS
......".
There is no need to make descriptions longer than necessary.
> + to operate in SRNS (Separate Reference Clocks with No Spread-Spectrum Clocking).
> + NOTE:- This is applicable only for Tegra234.
Make it false on other variants (allOf:if:then)
> +
No need for such blank lines.
> + $ref: /schemas/types.yaml#/definitions/flag
type: boolean (the same in your patch #2)
> +
> + nvidia,enable-ext-refclk:
> + description: |
> + This boolean property needs to be present if the controller is configured
> + to use the reference clocking coming in from an external clock source instead of
> + using the internal clock source.
> +
> + $ref: /schemas/types.yaml#/definitions/flag
> +
> allOf:
> - $ref: "/schemas/pci/pci-bus.yaml#"
> - $ref: "/schemas/pci/snps,dw-pcie.yaml#"
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra194-pcie
> + then:
> + properties:
> + nvidia,bpmp:
> + items:
> + - items:
> + - minimum: 0
> + maximum: 0xffffffff
> + - enum: [ 0, 1, 2, 3, 4, 5 ]
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra234-pcie
> + then:
> + properties:
> + nvidia,bpmp:
> + items:
> + - items:
> + - minimum: 0
> + maximum: 0xffffffff
> + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ]
> +
> unevaluatedProperties: false
>
> required:
> @@ -252,3 +332,64 @@ examples:
> phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
> };
> };
> +
> + - |
> + #include <dt-bindings/clock/tegra234-clock.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/tegra234-powergate.h>
> + #include <dt-bindings/reset/tegra234-reset.h>
> +
> + bus@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0x8 0x0>;
> +
> + pcie@14160000 {
> + compatible = "nvidia,tegra234-pcie";
> + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
> + reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
> + <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
> + <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
> + <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + num-lanes = <4>;
> + num-viewport = <8>;
> + linux,pci-domain = <4>;
> +
> + clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
> + clock-names = "core";
> +
> + resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
> + <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
> + reset-names = "apb", "core";
> +
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
> + interrupt-names = "intr", "msi";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +
> + nvidia,bpmp = <&bpmp 4>;
> +
> + nvidia,aspm-cmrt-us = <60>;
> + nvidia,aspm-pwr-on-t-us = <20>;
> + nvidia,aspm-l0s-entrance-latency-us = <3>;
> +
> + bus-range = <0x0 0xff>;
> + ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */
> + <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
> + <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */
> +
> + vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
> +
> + phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
> + <&p2u_hsio_7>;
> + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
> + };
> + };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V3 04/11] dt-bindings: PCI: tegra234: Add schema for tegra234 endpoint mode
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
` (2 preceding siblings ...)
2022-06-29 6:04 ` [PATCH V3 03/11] dt-bindings: PCI: tegra234: Add schema for tegra234 rootport mode Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-06-29 6:33 ` Krzysztof Kozlowski
2022-06-29 6:04 ` [PATCH V3 05/11] arm64: tegra: Add regulators required for PCIe Vidya Sagar
` (6 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
Add support for PCIe controllers that operate in the endpoint mode
in tegra234 chipset.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* New patch in this series
.../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 141 +++++++++++++++++-
1 file changed, 136 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
index 4f7cb7fe378e..11778eb92c47 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
@@ -17,6 +17,7 @@ description: |
in they can work either in root port mode or endpoint mode but one at a time.
On Tegra194, controllers C0, C4 and C5 support endpoint mode.
+ On Tegra234, controllers C5, C6, C7 and C10 support endpoint mode.
Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the
endpoint mode because of the way the platform is designed.
@@ -25,6 +26,7 @@ properties:
compatible:
enum:
- nvidia,tegra194-pcie-ep
+ - nvidia,tegra234-pcie-ep
reg:
items:
@@ -87,6 +89,8 @@ properties:
name for the PCIe controller. Following are the specifiers for the different PCIe
controllers:
+ Tegra194
+
- TEGRA194_POWER_DOMAIN_PCIEX8B: C0
- TEGRA194_POWER_DOMAIN_PCIEX1A: C1
- TEGRA194_POWER_DOMAIN_PCIEX1A: C2
@@ -96,6 +100,22 @@ properties:
these specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" file.
+ Tegra234
+
+ - TEGRA234_POWER_DOMAIN_PCIEX4BA: C0
+ - TEGRA234_POWER_DOMAIN_PCIEX1A : C1
+ - TEGRA234_POWER_DOMAIN_PCIEX1A : C2
+ - TEGRA234_POWER_DOMAIN_PCIEX1A : C3
+ - TEGRA234_POWER_DOMAIN_PCIEX4BB: C4
+ - TEGRA234_POWER_DOMAIN_PCIEX8A : C5
+ - TEGRA234_POWER_DOMAIN_PCIEX4A : C6
+ - TEGRA234_POWER_DOMAIN_PCIEX8B : C7
+ - TEGRA234_POWER_DOMAIN_PCIEX4CA: C8
+ - TEGRA234_POWER_DOMAIN_PCIEX4CB: C9
+ - TEGRA234_POWER_DOMAIN_PCIEX4CC: C10
+
+ these specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h" file.
+
interconnects:
items:
- description: memory read client
@@ -124,17 +144,30 @@ properties:
Must contain a pair of phandle to BPMP controller node followed by controller ID. Following
are the controller IDs for each controller:
+ Tegra194
+
0: C0
1: C1
2: C2
3: C3
4: C4
5: C5
- items:
- - items:
- - minimum: 0
- maximum: 0xffffffff
- - enum: [ 0, 1, 2, 3, 4, 5 ]
+
+ Tegra234
+
+ 0 : C0
+ 1 : C1
+ 2 : C2
+ 3 : C3
+ 4 : C4
+ 5 : C5
+ 6 : C6
+ 7 : C7
+ 8 : C8
+ 9 : C9
+ 10: C10
+
+ Platform constraints are described later
nvidia,aspm-cmrt-us:
description: Common Mode Restore Time for proper operation of ASPM to be specified in
@@ -154,9 +187,47 @@ properties:
enable REFCLK to controller from host
$ref: /schemas/types.yaml#/definitions/phandle-array
+ nvidia,enable-srns:
+ description: |
+ This boolean property needs to be present if the controller is configured
+ to operate in SRNS (Separate Reference Clocks with No Spread-Spectrum Clocking).
+ NOTE:- This is applicable only for Tegra234.
+
+ $ref: /schemas/types.yaml#/definitions/flag
+
allOf:
- $ref: "/schemas/pci/pci-ep.yaml#"
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra194-pcie
+ then:
+ properties:
+ nvidia,bpmp:
+ items:
+ - items:
+ - minimum: 0
+ maximum: 0xffffffff
+ - enum: [ 0, 1, 2, 3, 4, 5 ]
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - nvidia,tegra234-pcie
+ then:
+ properties:
+ nvidia,bpmp:
+ items:
+ - items:
+ - minimum: 0
+ maximum: 0xffffffff
+ - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ]
+
unevaluatedProperties: false
required:
@@ -174,6 +245,7 @@ required:
- power-domains
- reset-gpios
- num-lanes
+ - vddio-pex-ctl-supply
- phys
- phy-names
- nvidia,bpmp
@@ -237,3 +309,62 @@ examples:
"p2u-5", "p2u-6", "p2u-7";
};
};
+
+ - |
+ #include <dt-bindings/clock/tegra234-clock.h>
+ #include <dt-bindings/gpio/tegra234-gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/tegra234-powergate.h>
+ #include <dt-bindings/reset/tegra234-reset.h>
+
+ bus@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+ pcie-ep@141a0000 {
+ compatible = "nvidia,tegra234-pcie-ep";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
+ reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
+
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "intr";
+
+ clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
+ <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
+ reset-names = "apb", "core";
+
+ nvidia,bpmp = <&bpmp 5>;
+
+ nvidia,enable-ext-refclk;
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
+
+ reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
+
+ nvidia,refclk-select-gpios = <&gpio_aon
+ TEGRA234_AON_GPIO(AA, 4)
+ GPIO_ACTIVE_HIGH>;
+
+ num-lanes = <8>;
+ num-ib-windows = <2>;
+ num-ob-windows = <8>;
+
+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+ "p2u-5", "p2u-6", "p2u-7";
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH V3 04/11] dt-bindings: PCI: tegra234: Add schema for tegra234 endpoint mode
2022-06-29 6:04 ` [PATCH V3 04/11] dt-bindings: PCI: tegra234: Add schema for tegra234 endpoint mode Vidya Sagar
@ 2022-06-29 6:33 ` Krzysztof Kozlowski
0 siblings, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-29 6:33 UTC (permalink / raw)
To: Vidya Sagar, bhelgaas, lorenzo.pieralisi, robh+dt,
thierry.reding, jonathanh
Cc: kishon, vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv
On 29/06/2022 08:04, Vidya Sagar wrote:
> Add support for PCIe controllers that operate in the endpoint mode
> in tegra234 chipset.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V3:
> * New patch in this series
>
> .../bindings/pci/nvidia,tegra194-pcie-ep.yaml | 141 +++++++++++++++++-
> 1 file changed, 136 insertions(+), 5 deletions(-)
>
All comments from patch #3 apply.
> diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> index 4f7cb7fe378e..11778eb92c47 100644
> --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml
> @@ -17,6 +17,7 @@ description: |
> in they can work either in root port mode or endpoint mode but one at a time.
>
> On Tegra194, controllers C0, C4 and C5 support endpoint mode.
> + On Tegra234, controllers C5, C6, C7 and C10 support endpoint mode.
>
> Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to operate in the
> endpoint mode because of the way the platform is designed.
> @@ -25,6 +26,7 @@ properties:
> compatible:
> enum:
> - nvidia,tegra194-pcie-ep
> + - nvidia,tegra234-pcie-ep
>
> reg:
(...)
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - nvidia,tegra234-pcie
> + then:
> + properties:
> + nvidia,bpmp:
> + items:
> + - items:
> + - minimum: 0
> + maximum: 0xffffffff
> + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 ]
> +
> unevaluatedProperties: false
>
> required:
> @@ -174,6 +245,7 @@ required:
> - power-domains
> - reset-gpios
> - num-lanes
> + - vddio-pex-ctl-supply
This is unexpected and looks unrelated.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V3 05/11] arm64: tegra: Add regulators required for PCIe
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
` (3 preceding siblings ...)
2022-06-29 6:04 ` [PATCH V3 04/11] dt-bindings: PCI: tegra234: Add schema for tegra234 endpoint mode Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-06-29 6:34 ` Krzysztof Kozlowski
2022-06-29 6:04 ` [PATCH V3 06/11] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT Vidya Sagar
` (5 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
Add regulator supplies required for PCIe functionality. The supplies
include 1.8V, 3.3V and 12V.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* New patch in this series
.../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 24 +++++++++++++++++++
.../boot/dts/nvidia/tegra234-p3737-0000.dtsi | 23 ++++++++++++++++++
2 files changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
index 798de9226ba5..d53901ba45f6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
@@ -6,6 +6,30 @@
model = "NVIDIA Jetson AGX Orin";
compatible = "nvidia,p3701-0000", "nvidia,tegra234";
+ fixed-regulators {
+ compatible = "simple-bus";
+ device_type = "fixed-regulators";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+
+ p3701_vdd_1v8_ls: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "vdd-1v8-ls-sw5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ p3701_vdd_AO_1v8: regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "vdd-AO-1v8-sw2";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+ };
+
bus@0 {
spi@3270000 {
status = "okay";
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
index a85993c85e45..bb503643dd38 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
@@ -2,4 +2,27 @@
/ {
compatible = "nvidia,p3737-0000";
+
+ fixed-regulators {
+ p3737_vdd_3v3_pcie: regulator@105 {
+ compatible = "regulator-fixed";
+ reg = <105>;
+ regulator-name = "vdd-3v3-pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) 0>;
+ enable-active-high;
+ regulator-boot-on;
+ };
+ p3737_vdd_12v_pcie: regulator@114 {
+ compatible = "regulator-fixed";
+ reg = <114>;
+ regulator-name = "vdd-12v-pcie";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) 1>;
+ regulator-boot-on;
+ enable-active-low;
+ };
+ };
};
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH V3 05/11] arm64: tegra: Add regulators required for PCIe
2022-06-29 6:04 ` [PATCH V3 05/11] arm64: tegra: Add regulators required for PCIe Vidya Sagar
@ 2022-06-29 6:34 ` Krzysztof Kozlowski
0 siblings, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-29 6:34 UTC (permalink / raw)
To: Vidya Sagar, bhelgaas, lorenzo.pieralisi, robh+dt,
thierry.reding, jonathanh
Cc: kishon, vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv
On 29/06/2022 08:04, Vidya Sagar wrote:
> Add regulator supplies required for PCIe functionality. The supplies
> include 1.8V, 3.3V and 12V.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V3:
> * New patch in this series
>
> .../boot/dts/nvidia/tegra234-p3701-0000.dtsi | 24 +++++++++++++++++++
> .../boot/dts/nvidia/tegra234-p3737-0000.dtsi | 23 ++++++++++++++++++
> 2 files changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
> index 798de9226ba5..d53901ba45f6 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi
> @@ -6,6 +6,30 @@
> model = "NVIDIA Jetson AGX Orin";
> compatible = "nvidia,p3701-0000", "nvidia,tegra234";
>
> + fixed-regulators {
> + compatible = "simple-bus";
> + device_type = "fixed-regulators";
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
This is not a bus, fixed regulators are not part of some bus.
> +
> + p3701_vdd_1v8_ls: regulator@3 {
> + compatible = "regulator-fixed";
> + reg = <3>;
This fails schema. No.
> + regulator-name = "vdd-1v8-ls-sw5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
Missing blank line.
> + p3701_vdd_AO_1v8: regulator@5 {
> + compatible = "regulator-fixed";
> + reg = <5>;
> + regulator-name = "vdd-AO-1v8-sw2";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> + };
> +
> bus@0 {
> spi@3270000 {
> status = "okay";
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
> index a85993c85e45..bb503643dd38 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi
> @@ -2,4 +2,27 @@
>
> / {
> compatible = "nvidia,p3737-0000";
> +
> + fixed-regulators {
> + p3737_vdd_3v3_pcie: regulator@105 {
> + compatible = "regulator-fixed";
> + reg = <105>;
> + regulator-name = "vdd-3v3-pcie";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio TEGRA234_MAIN_GPIO(Z, 2) 0>;
> + enable-active-high;
> + regulator-boot-on;
> + };
Same comments.
> + p3737_vdd_12v_pcie: regulator@114 {
> + compatible = "regulator-fixed";
> + reg = <114>;
> + regulator-name = "vdd-12v-pcie";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + gpio = <&gpio TEGRA234_MAIN_GPIO(A, 1) 1>;
> + regulator-boot-on;
> + enable-active-low;
> + };
> + };
> };
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V3 06/11] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
` (4 preceding siblings ...)
2022-06-29 6:04 ` [PATCH V3 05/11] arm64: tegra: Add regulators required for PCIe Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-06-29 6:35 ` Krzysztof Kozlowski
2022-06-29 6:04 ` [PATCH V3 07/11] arm64: tegra: Enable PCIe slots in P3737-0000 board Vidya Sagar
` (4 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra234 SoC contains 10 PCIe controllers and 24 P2U instances
grouped into three different PHY bricks namely High-Speed IO (HSIO-8 P2Us)
NVIDIA High Speed (NVHS-8 P2Us) and Gigabit Ethernet (GBE-8 P2Us)
respectively.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* Added entries for all controllers that can operate in EndPoint mode
V2:
* Added 'iommu-map', 'iommu-map-mask' and 'dma-coherent' entries for each
PCIe controller node
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 935 +++++++++++++++++++++++
1 file changed, 935 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 2ae2f11f289c..062417e3ede5 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -998,6 +998,198 @@
status = "okay";
};
+ p2u_hsio_0: phy@3e00000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e00000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_1: phy@3e10000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e10000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_2: phy@3e20000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e20000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_3: phy@3e30000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e30000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_4: phy@3e40000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e40000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_5: phy@3e50000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e50000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_6: phy@3e60000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e60000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_hsio_7: phy@3e70000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e70000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_0: phy@3e90000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03e90000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_1: phy@3ea0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ea0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_2: phy@3eb0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03eb0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_3: phy@3ec0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ec0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_4: phy@3ed0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ed0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_5: phy@3ee0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ee0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_6: phy@3ef0000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03ef0000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_nvhs_7: phy@3f00000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f00000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_0: phy@3f20000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f20000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_1: phy@3f30000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f30000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_2: phy@3f40000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f40000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_3: phy@3f50000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f50000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_4: phy@3f60000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f60000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_5: phy@3f70000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f70000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_6: phy@3f80000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f80000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
+ p2u_gbe_7: phy@3f90000 {
+ compatible = "nvidia,tegra234-p2u";
+ reg = <0x03f90000 0x10000>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+ };
+
hsp_aon: hsp@c150000 {
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
reg = <0x0c150000 0x90000>;
@@ -1384,6 +1576,749 @@
status = "okay";
};
+ pcie@140a0000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
+ reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ linux,pci-domain = <8>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
+ <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 8>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
+ <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@140c0000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
+ reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ linux,pci-domain = <9>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
+ <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 9>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
+ <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@140e0000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
+ reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ linux,pci-domain = <10>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
+ <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 10>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
+ <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@14100000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
+ reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ linux,pci-domain = <1>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
+ <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 1>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
+ <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@14120000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
+ reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ linux,pci-domain = <2>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
+ <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 2>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
+ <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@14140000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
+ reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ linux,pci-domain = <3>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
+ <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 3>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
+ <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@14160000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
+ reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ linux,pci-domain = <4>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
+ <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 4>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
+ <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@14180000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
+ reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ linux,pci-domain = <0>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
+ <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 0>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
+ <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@141a0000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
+ reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <8>;
+ num-viewport = <8>;
+ linux,pci-domain = <5>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
+ <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 5>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x27 0x40000000 0x27 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */
+ <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@141c0000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
+ reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ linux,pci-domain = <6>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
+ <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 6>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
+ <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie@141e0000 {
+ compatible = "nvidia,tegra234-pcie";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
+ reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
+ <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */
+ reg-names = "appl", "config", "atu_dma", "dbi";
+
+ status = "disabled";
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <8>;
+ num-viewport = <8>;
+ linux,pci-domain = <7>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
+ <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+ interrupt-names = "intr", "msi";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+
+ nvidia,bpmp = <&bpmp 7>;
+
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ bus-range = <0x0 0xff>;
+
+ ranges = <0x43000000 0x2e 0x40000000 0x2e 0x40000000 0x3 0xe8000000>, /* prefetchable memory (16000 MB) */
+ <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
+ <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie-ep@141a0000 {
+ compatible = "nvidia,tegra234-pcie-ep";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
+ reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
+ <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
+
+ status = "disabled";
+
+ num-lanes = <8>;
+ num-ib-windows = <2>;
+ num-ob-windows = <8>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
+ <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 5>;
+
+ nvidia,enable-ext-refclk;
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie-ep@141c0000{
+ compatible = "nvidia,tegra234-pcie-ep";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
+ reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
+ <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
+
+ status = "disabled";
+
+ num-lanes = <4>;
+ num-ib-windows = <2>;
+ num-ob-windows = <8>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
+ <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 6>;
+
+ nvidia,enable-ext-refclk;
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie-ep@141e0000{
+ compatible = "nvidia,tegra234-pcie-ep";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
+ reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
+ <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
+
+ status = "disabled";
+
+ num-lanes = <8>;
+ num-ib-windows = <2>;
+ num-ob-windows = <8>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
+ <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 7>;
+
+ nvidia,enable-ext-refclk;
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
+ pcie-ep@140e0000{
+ compatible = "nvidia,tegra234-pcie-ep";
+ power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
+ reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
+ <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
+ <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
+ <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
+ reg-names = "appl", "atu_dma", "dbi", "addr_space";
+
+ status = "disabled";
+
+ num-lanes = <4>;
+ num-ib-windows = <2>;
+ num-ob-windows = <8>;
+
+ clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
+ clock-names = "core";
+
+ resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
+ <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
+ reset-names = "apb", "core";
+
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+ interrupt-names = "intr";
+
+ nvidia,bpmp = <&bpmp 10>;
+
+ nvidia,enable-ext-refclk;
+ nvidia,aspm-cmrt-us = <60>;
+ nvidia,aspm-pwr-on-t-us = <20>;
+ nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
+ iommu-map-mask = <0x0>;
+ dma-coherent;
+ };
+
sram@40000000 {
compatible = "nvidia,tegra234-sysram", "mmio-sram";
reg = <0x0 0x40000000 0x0 0x80000>;
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH V3 06/11] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT
2022-06-29 6:04 ` [PATCH V3 06/11] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT Vidya Sagar
@ 2022-06-29 6:35 ` Krzysztof Kozlowski
0 siblings, 0 replies; 27+ messages in thread
From: Krzysztof Kozlowski @ 2022-06-29 6:35 UTC (permalink / raw)
To: Vidya Sagar, bhelgaas, lorenzo.pieralisi, robh+dt,
thierry.reding, jonathanh
Cc: kishon, vkoul, kw, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv
On 29/06/2022 08:04, Vidya Sagar wrote:
> Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
> The Tegra234 SoC contains 10 PCIe controllers and 24 P2U instances
> grouped into three different PHY bricks namely High-Speed IO (HSIO-8 P2Us)
> NVIDIA High Speed (NVHS-8 P2Us) and Gigabit Ethernet (GBE-8 P2Us)
> respectively.
>
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
> V3:
> * Added entries for all controllers that can operate in EndPoint mode
>
> V2:
> * Added 'iommu-map', 'iommu-map-mask' and 'dma-coherent' entries for each
> PCIe controller node
>
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 935 +++++++++++++++++++++++
> 1 file changed, 935 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index 2ae2f11f289c..062417e3ede5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -998,6 +998,198 @@
> status = "okay";
> };
>
> + p2u_hsio_0: phy@3e00000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e00000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_1: phy@3e10000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e10000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_2: phy@3e20000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e20000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_3: phy@3e30000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e30000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_4: phy@3e40000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e40000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_5: phy@3e50000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e50000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_6: phy@3e60000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e60000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_7: phy@3e70000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e70000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_0: phy@3e90000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e90000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_1: phy@3ea0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ea0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_2: phy@3eb0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03eb0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_3: phy@3ec0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ec0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_4: phy@3ed0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ed0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_5: phy@3ee0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ee0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_6: phy@3ef0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ef0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_7: phy@3f00000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f00000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_0: phy@3f20000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f20000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_1: phy@3f30000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f30000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_2: phy@3f40000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f40000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_3: phy@3f50000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f50000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_4: phy@3f60000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f60000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_5: phy@3f70000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f70000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_6: phy@3f80000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f80000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_7: phy@3f90000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f90000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> hsp_aon: hsp@c150000 {
> compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
> reg = <0x0c150000 0x90000>;
> @@ -1384,6 +1576,749 @@
> status = "okay";
> };
>
> + pcie@140a0000 {
> + compatible = "nvidia,tegra234-pcie";
> + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
> + reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
> + <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
> + <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
> + <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
Status goes to the end, not somewhere in the middle of properties.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V3 07/11] arm64: tegra: Enable PCIe slots in P3737-0000 board
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
` (5 preceding siblings ...)
2022-06-29 6:04 ` [PATCH V3 06/11] arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-06-29 6:04 ` [PATCH V3 08/11] phy: tegra: Add PCIe PIPE2UPHY support for Tegra234 Vidya Sagar
` (3 subsequent siblings)
10 siblings, 0 replies; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
Enable PCIe controller nodes to enable respective PCIe slots on
P3737-0000 board. Following is the ownership of slots by different
PCIe controllers.
Controller-1 : On-board Broadcom WiFi controller
Controller-4 : M.2 Key-M slot
Controller-5 : CEM form-factor x8 slot
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* Added 'vddio-pex-ctl-supply' property
* Added a node for C5 controller's EndPoint mode
V2:
* Addressed review comment from Krzysztof
.../nvidia/tegra234-p3737-0000+p3701-0000.dts | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
index 3f6c399e3371..56bd97ec9ae4 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts
@@ -2111,4 +2111,56 @@
label = "NVIDIA Jetson AGX Orin APE";
};
+
+ pcie@14100000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
+
+ phys = <&p2u_hsio_3>;
+ phy-names = "p2u-0";
+ };
+
+ pcie@14160000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
+
+ phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+ <&p2u_hsio_7>;
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+ };
+
+ pcie@141a0000 {
+ status = "okay";
+
+ vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
+
+ vpcie3v3-supply = <&p3737_vdd_3v3_pcie>;
+ vpcie12v-supply = <&p3737_vdd_12v_pcie>;
+
+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+ "p2u-5", "p2u-6", "p2u-7";
+ };
+
+ pcie-ep@141a0000 {
+ status = "disabled";
+
+ vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
+
+ reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
+
+ nvidia,refclk-select-gpios = <&gpio_aon
+ TEGRA234_AON_GPIO(AA, 4)
+ GPIO_ACTIVE_HIGH>;
+
+ phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+ <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+ <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+ "p2u-5", "p2u-6", "p2u-7";
+ };
};
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V3 08/11] phy: tegra: Add PCIe PIPE2UPHY support for Tegra234
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
` (6 preceding siblings ...)
2022-06-29 6:04 ` [PATCH V3 07/11] arm64: tegra: Enable PCIe slots in P3737-0000 board Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-07-05 6:15 ` Vinod Koul
2022-06-29 6:04 ` [PATCH V3 09/11] PCI: Disable MSI for Tegra234 root ports Vidya Sagar
` (2 subsequent siblings)
10 siblings, 1 reply; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
Synopsys DesignWare core based PCIe controllers in Tegra234 SoC
interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U)
module. For each PCIe lane of a controller, there is a P2U unit
instantiated at hardware level. This driver provides support for the
programming required for each P2U that is going to be used for a PCIe
controller.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* None
V2:
* None
drivers/phy/tegra/phy-tegra194-p2u.c | 48 +++++++++++++++++++++++++++-
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c
index 3ee02b9eb04f..1415ca71de38 100644
--- a/drivers/phy/tegra/phy-tegra194-p2u.c
+++ b/drivers/phy/tegra/phy-tegra194-p2u.c
@@ -2,7 +2,7 @@
/*
* P2U (PIPE to UPHY) driver for Tegra T194 SoC
*
- * Copyright (C) 2019 NVIDIA Corporation.
+ * Copyright (C) 2019-2022 NVIDIA Corporation.
*
* Author: Vidya Sagar <vidyas@nvidia.com>
*/
@@ -14,6 +14,9 @@
#include <linux/of_platform.h>
#include <linux/phy/phy.h>
+#define P2U_CONTROL_CMN 0x74
+#define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20)
+
#define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
#define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
#define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)
@@ -24,8 +27,17 @@
#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff
#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160
+#define P2U_DIR_SEARCH_CTRL 0xd4
+#define P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE BIT(18)
+
+struct tegra_p2u_of_data {
+ bool one_dir_search;
+};
+
struct tegra_p2u {
void __iomem *base;
+ bool skip_sz_protection_en; /* Needed to support two retimers */
+ struct tegra_p2u_of_data *of_data;
};
static inline void p2u_writel(struct tegra_p2u *phy, const u32 value,
@@ -44,6 +56,12 @@ static int tegra_p2u_power_on(struct phy *x)
struct tegra_p2u *phy = phy_get_drvdata(x);
u32 val;
+ if (phy->skip_sz_protection_en) {
+ val = p2u_readl(phy, P2U_CONTROL_CMN);
+ val |= P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN;
+ p2u_writel(phy, val, P2U_CONTROL_CMN);
+ }
+
val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);
val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
@@ -58,6 +76,12 @@ static int tegra_p2u_power_on(struct phy *x)
val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME);
+ if (phy->of_data->one_dir_search) {
+ val = p2u_readl(phy, P2U_DIR_SEARCH_CTRL);
+ val &= ~P2U_DIR_SEARCH_CTRL_GEN4_FINE_GRAIN_SEARCH_TWICE;
+ p2u_writel(phy, val, P2U_DIR_SEARCH_CTRL);
+ }
+
return 0;
}
@@ -77,10 +101,19 @@ static int tegra_p2u_probe(struct platform_device *pdev)
if (!phy)
return -ENOMEM;
+ phy->of_data =
+ (struct tegra_p2u_of_data *)of_device_get_match_data(dev);
+ if (!phy->of_data)
+ return -EINVAL;
+
phy->base = devm_platform_ioremap_resource_byname(pdev, "ctl");
if (IS_ERR(phy->base))
return PTR_ERR(phy->base);
+ phy->skip_sz_protection_en =
+ of_property_read_bool(dev->of_node,
+ "nvidia,skip-sz-protect-en");
+
platform_set_drvdata(pdev, phy);
generic_phy = devm_phy_create(dev, NULL, &ops);
@@ -96,9 +129,22 @@ static int tegra_p2u_probe(struct platform_device *pdev)
return 0;
}
+static const struct tegra_p2u_of_data tegra194_p2u_of_data = {
+ .one_dir_search = false,
+};
+
+static const struct tegra_p2u_of_data tegra234_p2u_of_data = {
+ .one_dir_search = true,
+};
+
static const struct of_device_id tegra_p2u_id_table[] = {
{
.compatible = "nvidia,tegra194-p2u",
+ .data = &tegra194_p2u_of_data,
+ },
+ {
+ .compatible = "nvidia,tegra234-p2u",
+ .data = &tegra234_p2u_of_data,
},
{}
};
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH V3 08/11] phy: tegra: Add PCIe PIPE2UPHY support for Tegra234
2022-06-29 6:04 ` [PATCH V3 08/11] phy: tegra: Add PCIe PIPE2UPHY support for Tegra234 Vidya Sagar
@ 2022-07-05 6:15 ` Vinod Koul
0 siblings, 0 replies; 27+ messages in thread
From: Vinod Koul @ 2022-07-05 6:15 UTC (permalink / raw)
To: Vidya Sagar
Cc: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh,
kishon, kw, krzk, p.zabel, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-phy, kthota, mmaddireddy,
sagar.tv
On 29-06-22, 11:34, Vidya Sagar wrote:
> Synopsys DesignWare core based PCIe controllers in Tegra234 SoC
> interface with Universal PHY (UPHY) module through a PIPE2UPHY (P2U)
> module. For each PCIe lane of a controller, there is a P2U unit
> instantiated at hardware level. This driver provides support for the
> programming required for each P2U that is going to be used for a PCIe
> controller.
Applied, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH V3 09/11] PCI: Disable MSI for Tegra234 root ports
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
` (7 preceding siblings ...)
2022-06-29 6:04 ` [PATCH V3 08/11] phy: tegra: Add PCIe PIPE2UPHY support for Tegra234 Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-06-29 6:04 ` [PATCH V3 10/11] Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie" Vidya Sagar
2022-06-29 6:04 ` [PATCH V3 11/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
10 siblings, 0 replies; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
Tegra234 PCIe rootports don't generate MSI interrupts for PME and AER
events. Since PCIe spec (Ref: r4.0 sec 6.1.4.3) doesn't support using
a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root
ports service drivers registering their respective ISRs with MSI interrupt
and to let only INTx be used for all events.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* None
V2:
* Addressed review comments from Bjorn i.e. changed the PCIe spec reference
to a more relevant section and modified commit message accordingly
drivers/pci/quirks.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 2e68f50bc7ae..5b532449ac4f 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2709,8 +2709,8 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
nvenet_msi_disable);
/*
- * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
- * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
+ * PCIe spec r4.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled,then the
+ * device can't use INTx interrupts. Tegra's PCIe root ports don't
* generate MSI interrupts for PME and AER events instead only INTx interrupts
* are generated. Though Tegra's PCIe root ports can generate MSI interrupts
* for other events, since PCIe specification doesn't support using a mix of
@@ -2760,6 +2760,15 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
PCI_CLASS_BRIDGE_PCI, 8,
pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
/*
* Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V3 10/11] Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie"
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
` (8 preceding siblings ...)
2022-06-29 6:04 ` [PATCH V3 09/11] PCI: Disable MSI for Tegra234 root ports Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
2022-06-29 6:04 ` [PATCH V3 11/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
10 siblings, 0 replies; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
This reverts commit b572569183993b68dec0e990b33641e6f77744ba.
It keeps the names of data structures generic and not contain
any one particular chip name. This is a preparatory change for the
upcoming changes that add support for Tegra234.
This has no functional impact.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* None
V2:
* New addition in V2 based on Bjorn's review comment
drivers/pci/controller/dwc/pcie-tegra194.c | 222 ++++++++++-----------
1 file changed, 111 insertions(+), 111 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index d992371a36e6..bd16245fc2c4 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -243,7 +243,7 @@ static const unsigned int pcie_gen_freq[] = {
GEN4_CORE_CLK_FREQ
};
-struct tegra194_pcie {
+struct tegra_pcie_dw {
struct device *dev;
struct resource *appl_res;
struct resource *dbi_res;
@@ -287,22 +287,22 @@ struct tegra194_pcie {
int ep_state;
};
-struct tegra194_pcie_of_data {
+struct tegra_pcie_dw_of_data {
enum dw_pcie_device_mode mode;
};
-static inline struct tegra194_pcie *to_tegra_pcie(struct dw_pcie *pci)
+static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
{
- return container_of(pci, struct tegra194_pcie, pci);
+ return container_of(pci, struct tegra_pcie_dw, pci);
}
-static inline void appl_writel(struct tegra194_pcie *pcie, const u32 value,
+static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
const u32 reg)
{
writel_relaxed(value, pcie->appl_base + reg);
}
-static inline u32 appl_readl(struct tegra194_pcie *pcie, const u32 reg)
+static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
{
return readl_relaxed(pcie->appl_base + reg);
}
@@ -314,7 +314,7 @@ struct tegra_pcie_soc {
static void apply_bad_link_workaround(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 current_link_width;
u16 val;
@@ -347,7 +347,7 @@ static void apply_bad_link_workaround(struct pcie_port *pp)
static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
{
- struct tegra194_pcie *pcie = arg;
+ struct tegra_pcie_dw *pcie = arg;
struct dw_pcie *pci = &pcie->pci;
struct pcie_port *pp = &pci->pp;
u32 val, tmp;
@@ -418,7 +418,7 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
return IRQ_HANDLED;
}
-static void pex_ep_event_hot_rst_done(struct tegra194_pcie *pcie)
+static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie)
{
u32 val;
@@ -446,7 +446,7 @@ static void pex_ep_event_hot_rst_done(struct tegra194_pcie *pcie)
static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
{
- struct tegra194_pcie *pcie = arg;
+ struct tegra_pcie_dw *pcie = arg;
struct dw_pcie *pci = &pcie->pci;
u32 val, speed;
@@ -492,7 +492,7 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
{
- struct tegra194_pcie *pcie = arg;
+ struct tegra_pcie_dw *pcie = arg;
struct dw_pcie_ep *ep = &pcie->pci.ep;
int spurious = 1;
u32 status_l0, status_l1, link_status;
@@ -535,7 +535,7 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
return IRQ_HANDLED;
}
-static int tegra194_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, int where,
+static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
/*
@@ -552,7 +552,7 @@ static int tegra194_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, int where,
return pci_generic_config_read(bus, devfn, where, size, val);
}
-static int tegra194_pcie_wr_own_conf(struct pci_bus *bus, u32 devfn, int where,
+static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 val)
{
/*
@@ -569,8 +569,8 @@ static int tegra194_pcie_wr_own_conf(struct pci_bus *bus, u32 devfn, int where,
static struct pci_ops tegra_pci_ops = {
.map_bus = dw_pcie_own_conf_map_bus,
- .read = tegra194_pcie_rd_own_conf,
- .write = tegra194_pcie_wr_own_conf,
+ .read = tegra_pcie_dw_rd_own_conf,
+ .write = tegra_pcie_dw_wr_own_conf,
};
#if defined(CONFIG_PCIEASPM)
@@ -592,7 +592,7 @@ static const u32 event_cntr_data_offset[] = {
0x1dc
};
-static void disable_aspm_l11(struct tegra194_pcie *pcie)
+static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
{
u32 val;
@@ -601,7 +601,7 @@ static void disable_aspm_l11(struct tegra194_pcie *pcie)
dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
}
-static void disable_aspm_l12(struct tegra194_pcie *pcie)
+static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
{
u32 val;
@@ -610,7 +610,7 @@ static void disable_aspm_l12(struct tegra194_pcie *pcie)
dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
}
-static inline u32 event_counter_prog(struct tegra194_pcie *pcie, u32 event)
+static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
{
u32 val;
@@ -627,7 +627,7 @@ static inline u32 event_counter_prog(struct tegra194_pcie *pcie, u32 event)
static int aspm_state_cnt(struct seq_file *s, void *data)
{
- struct tegra194_pcie *pcie = (struct tegra194_pcie *)
+ struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)
dev_get_drvdata(s->private);
u32 val;
@@ -658,7 +658,7 @@ static int aspm_state_cnt(struct seq_file *s, void *data)
return 0;
}
-static void init_host_aspm(struct tegra194_pcie *pcie)
+static void init_host_aspm(struct tegra_pcie_dw *pcie)
{
struct dw_pcie *pci = &pcie->pci;
u32 val;
@@ -686,22 +686,22 @@ static void init_host_aspm(struct tegra194_pcie *pcie)
dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
}
-static void init_debugfs(struct tegra194_pcie *pcie)
+static void init_debugfs(struct tegra_pcie_dw *pcie)
{
debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs,
aspm_state_cnt);
}
#else
-static inline void disable_aspm_l12(struct tegra194_pcie *pcie) { return; }
-static inline void disable_aspm_l11(struct tegra194_pcie *pcie) { return; }
-static inline void init_host_aspm(struct tegra194_pcie *pcie) { return; }
-static inline void init_debugfs(struct tegra194_pcie *pcie) { return; }
+static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; }
+static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; }
+static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; }
+static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; }
#endif
static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val;
u16 val_w;
@@ -739,7 +739,7 @@ static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val;
/* Enable legacy interrupt generation */
@@ -760,7 +760,7 @@ static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val;
/* Enable MSI interrupt generation */
@@ -773,7 +773,7 @@ static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
/* Clear interrupt statuses before enabling interrupts */
appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
@@ -798,7 +798,7 @@ static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
tegra_pcie_enable_msi_interrupts(pp);
}
-static void config_gen3_gen4_eq_presets(struct tegra194_pcie *pcie)
+static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
{
struct dw_pcie *pci = &pcie->pci;
u32 val, offset, i;
@@ -851,10 +851,10 @@ static void config_gen3_gen4_eq_presets(struct tegra194_pcie *pcie)
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
}
-static int tegra194_pcie_host_init(struct pcie_port *pp)
+static int tegra_pcie_dw_host_init(struct pcie_port *pp)
{
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val;
pp->bridge->ops = &tegra_pci_ops;
@@ -912,10 +912,10 @@ static int tegra194_pcie_host_init(struct pcie_port *pp)
return 0;
}
-static int tegra194_pcie_start_link(struct dw_pcie *pci)
+static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
{
u32 val, offset, speed, tmp;
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
struct pcie_port *pp = &pci->pp;
bool retry = true;
@@ -980,7 +980,7 @@ static int tegra194_pcie_start_link(struct dw_pcie *pci)
val &= ~PCI_DLF_EXCHANGE_ENABLE;
dw_pcie_writel_dbi(pci, offset, val);
- tegra194_pcie_host_init(pp);
+ tegra_pcie_dw_host_init(pp);
dw_pcie_setup_rc(pp);
retry = false;
@@ -996,32 +996,32 @@ static int tegra194_pcie_start_link(struct dw_pcie *pci)
return 0;
}
-static int tegra194_pcie_link_up(struct dw_pcie *pci)
+static int tegra_pcie_dw_link_up(struct dw_pcie *pci)
{
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
return !!(val & PCI_EXP_LNKSTA_DLLLA);
}
-static void tegra194_pcie_stop_link(struct dw_pcie *pci)
+static void tegra_pcie_dw_stop_link(struct dw_pcie *pci)
{
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
disable_irq(pcie->pex_rst_irq);
}
static const struct dw_pcie_ops tegra_dw_pcie_ops = {
- .link_up = tegra194_pcie_link_up,
- .start_link = tegra194_pcie_start_link,
- .stop_link = tegra194_pcie_stop_link,
+ .link_up = tegra_pcie_dw_link_up,
+ .start_link = tegra_pcie_dw_start_link,
+ .stop_link = tegra_pcie_dw_stop_link,
};
-static const struct dw_pcie_host_ops tegra194_pcie_host_ops = {
- .host_init = tegra194_pcie_host_init,
+static const struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
+ .host_init = tegra_pcie_dw_host_init,
};
-static void tegra_pcie_disable_phy(struct tegra194_pcie *pcie)
+static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
{
unsigned int phy_count = pcie->phy_count;
@@ -1031,7 +1031,7 @@ static void tegra_pcie_disable_phy(struct tegra194_pcie *pcie)
}
}
-static int tegra_pcie_enable_phy(struct tegra194_pcie *pcie)
+static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
{
unsigned int i;
int ret;
@@ -1058,7 +1058,7 @@ static int tegra_pcie_enable_phy(struct tegra194_pcie *pcie)
return ret;
}
-static int tegra194_pcie_parse_dt(struct tegra194_pcie *pcie)
+static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
{
struct platform_device *pdev = to_platform_device(pcie->dev);
struct device_node *np = pcie->dev->of_node;
@@ -1154,7 +1154,7 @@ static int tegra194_pcie_parse_dt(struct tegra194_pcie *pcie)
return 0;
}
-static int tegra_pcie_bpmp_set_ctrl_state(struct tegra194_pcie *pcie,
+static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
bool enable)
{
struct mrq_uphy_response resp;
@@ -1182,7 +1182,7 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra194_pcie *pcie,
return tegra_bpmp_transfer(pcie->bpmp, &msg);
}
-static int tegra_pcie_bpmp_set_pll_state(struct tegra194_pcie *pcie,
+static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
bool enable)
{
struct mrq_uphy_response resp;
@@ -1210,7 +1210,7 @@ static int tegra_pcie_bpmp_set_pll_state(struct tegra194_pcie *pcie,
return tegra_bpmp_transfer(pcie->bpmp, &msg);
}
-static void tegra_pcie_downstream_dev_to_D0(struct tegra194_pcie *pcie)
+static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
{
struct pcie_port *pp = &pcie->pci.pp;
struct pci_bus *child, *root_bus = NULL;
@@ -1248,7 +1248,7 @@ static void tegra_pcie_downstream_dev_to_D0(struct tegra194_pcie *pcie)
}
}
-static int tegra_pcie_get_slot_regulators(struct tegra194_pcie *pcie)
+static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
{
pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
if (IS_ERR(pcie->slot_ctl_3v3)) {
@@ -1269,7 +1269,7 @@ static int tegra_pcie_get_slot_regulators(struct tegra194_pcie *pcie)
return 0;
}
-static int tegra_pcie_enable_slot_regulators(struct tegra194_pcie *pcie)
+static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
{
int ret;
@@ -1307,7 +1307,7 @@ static int tegra_pcie_enable_slot_regulators(struct tegra194_pcie *pcie)
return ret;
}
-static void tegra_pcie_disable_slot_regulators(struct tegra194_pcie *pcie)
+static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)
{
if (pcie->slot_ctl_12v)
regulator_disable(pcie->slot_ctl_12v);
@@ -1315,7 +1315,7 @@ static void tegra_pcie_disable_slot_regulators(struct tegra194_pcie *pcie)
regulator_disable(pcie->slot_ctl_3v3);
}
-static int tegra_pcie_config_controller(struct tegra194_pcie *pcie,
+static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
bool en_hw_hot_rst)
{
int ret;
@@ -1412,7 +1412,7 @@ static int tegra_pcie_config_controller(struct tegra194_pcie *pcie,
return ret;
}
-static void tegra_pcie_unconfig_controller(struct tegra194_pcie *pcie)
+static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie)
{
int ret;
@@ -1440,7 +1440,7 @@ static void tegra_pcie_unconfig_controller(struct tegra194_pcie *pcie)
pcie->cid, ret);
}
-static int tegra_pcie_init_controller(struct tegra194_pcie *pcie)
+static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
{
struct dw_pcie *pci = &pcie->pci;
struct pcie_port *pp = &pci->pp;
@@ -1450,7 +1450,7 @@ static int tegra_pcie_init_controller(struct tegra194_pcie *pcie)
if (ret < 0)
return ret;
- pp->ops = &tegra194_pcie_host_ops;
+ pp->ops = &tegra_pcie_dw_host_ops;
ret = dw_pcie_host_init(pp);
if (ret < 0) {
@@ -1465,11 +1465,11 @@ static int tegra_pcie_init_controller(struct tegra194_pcie *pcie)
return ret;
}
-static int tegra_pcie_try_link_l2(struct tegra194_pcie *pcie)
+static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
{
u32 val;
- if (!tegra194_pcie_link_up(&pcie->pci))
+ if (!tegra_pcie_dw_link_up(&pcie->pci))
return 0;
val = appl_readl(pcie, APPL_RADM_STATUS);
@@ -1481,12 +1481,12 @@ static int tegra_pcie_try_link_l2(struct tegra194_pcie *pcie)
1, PME_ACK_TIMEOUT);
}
-static void tegra194_pcie_pme_turnoff(struct tegra194_pcie *pcie)
+static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
{
u32 data;
int err;
- if (!tegra194_pcie_link_up(&pcie->pci)) {
+ if (!tegra_pcie_dw_link_up(&pcie->pci)) {
dev_dbg(pcie->dev, "PCIe link is not up...!\n");
return;
}
@@ -1543,15 +1543,15 @@ static void tegra194_pcie_pme_turnoff(struct tegra194_pcie *pcie)
appl_writel(pcie, data, APPL_PINMUX);
}
-static void tegra_pcie_deinit_controller(struct tegra194_pcie *pcie)
+static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
{
tegra_pcie_downstream_dev_to_D0(pcie);
dw_pcie_host_deinit(&pcie->pci.pp);
- tegra194_pcie_pme_turnoff(pcie);
+ tegra_pcie_dw_pme_turnoff(pcie);
tegra_pcie_unconfig_controller(pcie);
}
-static int tegra_pcie_config_rp(struct tegra194_pcie *pcie)
+static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
{
struct device *dev = pcie->dev;
char *name;
@@ -1578,7 +1578,7 @@ static int tegra_pcie_config_rp(struct tegra194_pcie *pcie)
goto fail_pm_get_sync;
}
- pcie->link_state = tegra194_pcie_link_up(&pcie->pci);
+ pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
if (!pcie->link_state) {
ret = -ENOMEDIUM;
goto fail_host_init;
@@ -1603,7 +1603,7 @@ static int tegra_pcie_config_rp(struct tegra194_pcie *pcie)
return ret;
}
-static void pex_ep_event_pex_rst_assert(struct tegra194_pcie *pcie)
+static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
{
u32 val;
int ret;
@@ -1642,7 +1642,7 @@ static void pex_ep_event_pex_rst_assert(struct tegra194_pcie *pcie)
dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
}
-static void pex_ep_event_pex_rst_deassert(struct tegra194_pcie *pcie)
+static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
{
struct dw_pcie *pci = &pcie->pci;
struct dw_pcie_ep *ep = &pci->ep;
@@ -1807,7 +1807,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra194_pcie *pcie)
static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
{
- struct tegra194_pcie *pcie = arg;
+ struct tegra_pcie_dw *pcie = arg;
if (gpiod_get_value(pcie->pex_rst_gpiod))
pex_ep_event_pex_rst_assert(pcie);
@@ -1817,7 +1817,7 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
return IRQ_HANDLED;
}
-static int tegra_pcie_ep_raise_legacy_irq(struct tegra194_pcie *pcie, u16 irq)
+static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq)
{
/* Tegra194 supports only INTA */
if (irq > 1)
@@ -1829,7 +1829,7 @@ static int tegra_pcie_ep_raise_legacy_irq(struct tegra194_pcie *pcie, u16 irq)
return 0;
}
-static int tegra_pcie_ep_raise_msi_irq(struct tegra194_pcie *pcie, u16 irq)
+static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
{
if (unlikely(irq > 31))
return -EINVAL;
@@ -1839,7 +1839,7 @@ static int tegra_pcie_ep_raise_msi_irq(struct tegra194_pcie *pcie, u16 irq)
return 0;
}
-static int tegra_pcie_ep_raise_msix_irq(struct tegra194_pcie *pcie, u16 irq)
+static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
{
struct dw_pcie_ep *ep = &pcie->pci.ep;
@@ -1853,7 +1853,7 @@ static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
u16 interrupt_num)
{
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
- struct tegra194_pcie *pcie = to_tegra_pcie(pci);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
switch (type) {
case PCI_EPC_IRQ_LEGACY:
@@ -1894,7 +1894,7 @@ static const struct dw_pcie_ep_ops pcie_ep_ops = {
.get_features = tegra_pcie_ep_get_features,
};
-static int tegra_pcie_config_ep(struct tegra194_pcie *pcie,
+static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
struct platform_device *pdev)
{
struct dw_pcie *pci = &pcie->pci;
@@ -1956,12 +1956,12 @@ static int tegra_pcie_config_ep(struct tegra194_pcie *pcie,
return 0;
}
-static int tegra194_pcie_probe(struct platform_device *pdev)
+static int tegra_pcie_dw_probe(struct platform_device *pdev)
{
- const struct tegra194_pcie_of_data *data;
+ const struct tegra_pcie_dw_of_data *data;
struct device *dev = &pdev->dev;
struct resource *atu_dma_res;
- struct tegra194_pcie *pcie;
+ struct tegra_pcie_dw *pcie;
struct pcie_port *pp;
struct dw_pcie *pci;
struct phy **phys;
@@ -1987,7 +1987,7 @@ static int tegra194_pcie_probe(struct platform_device *pdev)
pcie->dev = &pdev->dev;
pcie->mode = (enum dw_pcie_device_mode)data->mode;
- ret = tegra194_pcie_parse_dt(pcie);
+ ret = tegra_pcie_dw_parse_dt(pcie);
if (ret < 0) {
const char *level = KERN_ERR;
@@ -2145,9 +2145,9 @@ static int tegra194_pcie_probe(struct platform_device *pdev)
return ret;
}
-static int tegra194_pcie_remove(struct platform_device *pdev)
+static int tegra_pcie_dw_remove(struct platform_device *pdev)
{
- struct tegra194_pcie *pcie = platform_get_drvdata(pdev);
+ struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
if (!pcie->link_state)
return 0;
@@ -2163,9 +2163,9 @@ static int tegra194_pcie_remove(struct platform_device *pdev)
return 0;
}
-static int tegra194_pcie_suspend_late(struct device *dev)
+static int tegra_pcie_dw_suspend_late(struct device *dev)
{
- struct tegra194_pcie *pcie = dev_get_drvdata(dev);
+ struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
u32 val;
if (!pcie->link_state)
@@ -2181,23 +2181,23 @@ static int tegra194_pcie_suspend_late(struct device *dev)
return 0;
}
-static int tegra194_pcie_suspend_noirq(struct device *dev)
+static int tegra_pcie_dw_suspend_noirq(struct device *dev)
{
- struct tegra194_pcie *pcie = dev_get_drvdata(dev);
+ struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
if (!pcie->link_state)
return 0;
tegra_pcie_downstream_dev_to_D0(pcie);
- tegra194_pcie_pme_turnoff(pcie);
+ tegra_pcie_dw_pme_turnoff(pcie);
tegra_pcie_unconfig_controller(pcie);
return 0;
}
-static int tegra194_pcie_resume_noirq(struct device *dev)
+static int tegra_pcie_dw_resume_noirq(struct device *dev)
{
- struct tegra194_pcie *pcie = dev_get_drvdata(dev);
+ struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
int ret;
if (!pcie->link_state)
@@ -2207,7 +2207,7 @@ static int tegra194_pcie_resume_noirq(struct device *dev)
if (ret < 0)
return ret;
- ret = tegra194_pcie_host_init(&pcie->pci.pp);
+ ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
if (ret < 0) {
dev_err(dev, "Failed to init host: %d\n", ret);
goto fail_host_init;
@@ -2215,7 +2215,7 @@ static int tegra194_pcie_resume_noirq(struct device *dev)
dw_pcie_setup_rc(&pcie->pci.pp);
- ret = tegra194_pcie_start_link(&pcie->pci);
+ ret = tegra_pcie_dw_start_link(&pcie->pci);
if (ret < 0)
goto fail_host_init;
@@ -2226,9 +2226,9 @@ static int tegra194_pcie_resume_noirq(struct device *dev)
return ret;
}
-static int tegra194_pcie_resume_early(struct device *dev)
+static int tegra_pcie_dw_resume_early(struct device *dev)
{
- struct tegra194_pcie *pcie = dev_get_drvdata(dev);
+ struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
u32 val;
if (pcie->mode == DW_PCIE_EP_TYPE) {
@@ -2251,9 +2251,9 @@ static int tegra194_pcie_resume_early(struct device *dev)
return 0;
}
-static void tegra194_pcie_shutdown(struct platform_device *pdev)
+static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
{
- struct tegra194_pcie *pcie = platform_get_drvdata(pdev);
+ struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
if (!pcie->link_state)
return;
@@ -2265,50 +2265,50 @@ static void tegra194_pcie_shutdown(struct platform_device *pdev)
if (IS_ENABLED(CONFIG_PCI_MSI))
disable_irq(pcie->pci.pp.msi_irq);
- tegra194_pcie_pme_turnoff(pcie);
+ tegra_pcie_dw_pme_turnoff(pcie);
tegra_pcie_unconfig_controller(pcie);
}
-static const struct tegra194_pcie_of_data tegra194_pcie_rc_of_data = {
+static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = {
.mode = DW_PCIE_RC_TYPE,
};
-static const struct tegra194_pcie_of_data tegra194_pcie_ep_of_data = {
+static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data = {
.mode = DW_PCIE_EP_TYPE,
};
-static const struct of_device_id tegra194_pcie_of_match[] = {
+static const struct of_device_id tegra_pcie_dw_of_match[] = {
{
.compatible = "nvidia,tegra194-pcie",
- .data = &tegra194_pcie_rc_of_data,
+ .data = &tegra_pcie_dw_rc_of_data,
},
{
.compatible = "nvidia,tegra194-pcie-ep",
- .data = &tegra194_pcie_ep_of_data,
+ .data = &tegra_pcie_dw_ep_of_data,
},
{},
};
-static const struct dev_pm_ops tegra194_pcie_pm_ops = {
- .suspend_late = tegra194_pcie_suspend_late,
- .suspend_noirq = tegra194_pcie_suspend_noirq,
- .resume_noirq = tegra194_pcie_resume_noirq,
- .resume_early = tegra194_pcie_resume_early,
+static const struct dev_pm_ops tegra_pcie_dw_pm_ops = {
+ .suspend_late = tegra_pcie_dw_suspend_late,
+ .suspend_noirq = tegra_pcie_dw_suspend_noirq,
+ .resume_noirq = tegra_pcie_dw_resume_noirq,
+ .resume_early = tegra_pcie_dw_resume_early,
};
-static struct platform_driver tegra194_pcie_driver = {
- .probe = tegra194_pcie_probe,
- .remove = tegra194_pcie_remove,
- .shutdown = tegra194_pcie_shutdown,
+static struct platform_driver tegra_pcie_dw_driver = {
+ .probe = tegra_pcie_dw_probe,
+ .remove = tegra_pcie_dw_remove,
+ .shutdown = tegra_pcie_dw_shutdown,
.driver = {
.name = "tegra194-pcie",
- .pm = &tegra194_pcie_pm_ops,
- .of_match_table = tegra194_pcie_of_match,
+ .pm = &tegra_pcie_dw_pm_ops,
+ .of_match_table = tegra_pcie_dw_of_match,
},
};
-module_platform_driver(tegra194_pcie_driver);
+module_platform_driver(tegra_pcie_dw_driver);
-MODULE_DEVICE_TABLE(of, tegra194_pcie_of_match);
+MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
--
2.17.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH V3 11/11] PCI: tegra: Add Tegra234 PCIe support
2022-06-29 6:04 [PATCH V3 00/11] PCI: tegra: Add Tegra234 PCIe support Vidya Sagar
` (9 preceding siblings ...)
2022-06-29 6:04 ` [PATCH V3 10/11] Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie" Vidya Sagar
@ 2022-06-29 6:04 ` Vidya Sagar
10 siblings, 0 replies; 27+ messages in thread
From: Vidya Sagar @ 2022-06-29 6:04 UTC (permalink / raw)
To: bhelgaas, lorenzo.pieralisi, robh+dt, thierry.reding, jonathanh
Cc: kishon, vkoul, kw, krzk, p.zabel, mperttunen, linux-pci,
devicetree, linux-tegra, linux-kernel, linux-phy, kthota,
mmaddireddy, vidyas, sagar.tv
Add support for Synopsys DesignWare core IP based PCIe host controllers
present in the Tegra234 SoC.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
V3:
* Addressed review comment from Raul Tambre
V2:
* Rebased on top of patch-7
drivers/pci/controller/dwc/pcie-tegra194.c | 412 ++++++++++++++++-----
1 file changed, 319 insertions(+), 93 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index bd16245fc2c4..f5dbfdfe3887 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1,8 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * PCIe host controller driver for Tegra194 SoC
+ * PCIe host controller driver for the following SoCs
+ * Tegra194
+ * Tegra234
*
- * Copyright (C) 2019 NVIDIA Corporation.
+ * Copyright (C) 2019-2022 NVIDIA Corporation.
*
* Author: Vidya Sagar <vidyas@nvidia.com>
*/
@@ -35,6 +37,9 @@
#include <soc/tegra/bpmp-abi.h>
#include "../../pci.h"
+#define TEGRA194_DWC_IP_VER 0x490A
+#define TEGRA234_DWC_IP_VER 0x562A
+
#define APPL_PINMUX 0x0
#define APPL_PINMUX_PEX_RST BIT(0)
#define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2)
@@ -49,6 +54,7 @@
#define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0)
#define APPL_CTRL_HW_HOT_RST_MODE_SHIFT 22
#define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1
+#define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN 0x2
#define APPL_INTR_EN_L0_0 0x8
#define APPL_INTR_EN_L0_0_LINK_STATE_INT_EN BIT(0)
@@ -243,6 +249,18 @@ static const unsigned int pcie_gen_freq[] = {
GEN4_CORE_CLK_FREQ
};
+struct tegra_pcie_dw_of_data {
+ u32 version;
+ enum dw_pcie_device_mode mode;
+ bool msix_doorbell_access_fixup;
+ bool sbr_reset_fixup;
+ bool l1ss_exit_fixup;
+ bool ltr_req_fixup;
+ u32 cdm_chk_int_en;
+ u32 gen4_preset_vec;
+ u8 n_fts[2];
+};
+
struct tegra_pcie_dw {
struct device *dev;
struct resource *appl_res;
@@ -255,12 +273,14 @@ struct tegra_pcie_dw {
struct dw_pcie pci;
struct tegra_bpmp *bpmp;
- enum dw_pcie_device_mode mode;
+ struct tegra_pcie_dw_of_data *of_data;
bool supports_clkreq;
bool enable_cdm_check;
+ bool enable_srns;
bool link_state;
bool update_fc_fixup;
+ bool enable_ext_refclk;
u8 init_link_width;
u32 msi_ctrl_int;
u32 num_lanes;
@@ -284,13 +304,10 @@ struct tegra_pcie_dw {
struct gpio_desc *pex_rst_gpiod;
struct gpio_desc *pex_refclk_sel_gpiod;
unsigned int pex_rst_irq;
+ bool pex_rst_irq_enabled;
int ep_state;
};
-struct tegra_pcie_dw_of_data {
- enum dw_pcie_device_mode mode;
-};
-
static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
{
return container_of(pci, struct tegra_pcie_dw, pci);
@@ -350,15 +367,15 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
struct tegra_pcie_dw *pcie = arg;
struct dw_pcie *pci = &pcie->pci;
struct pcie_port *pp = &pci->pp;
- u32 val, tmp;
+ u32 val, status_l0, status_l1;
u16 val_w;
- val = appl_readl(pcie, APPL_INTR_STATUS_L0);
- if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
- val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
- if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
- appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
-
+ status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
+ if (status_l0 & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
+ status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
+ appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
+ if (pcie->of_data->sbr_reset_fixup &&
+ status_l1 & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
/* SBR & Surprise Link Down WAR */
val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
@@ -374,15 +391,21 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
}
}
- if (val & APPL_INTR_STATUS_L0_INT_INT) {
- val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
- if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
+ if (status_l0 & APPL_INTR_STATUS_L0_INT_INT) {
+ status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
+ if (status_l1 & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
appl_writel(pcie,
APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,
APPL_INTR_STATUS_L1_8_0);
apply_bad_link_workaround(pp);
}
- if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
+ if (status_l1 & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
+ val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
+ PCI_EXP_LNKSTA);
+ val_w |= PCI_EXP_LNKSTA_LBMS;
+ dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
+ PCI_EXP_LNKSTA, val_w);
+
appl_writel(pcie,
APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,
APPL_INTR_STATUS_L1_8_0);
@@ -394,25 +417,24 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg)
}
}
- val = appl_readl(pcie, APPL_INTR_STATUS_L0);
- if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
- val = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
- tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
- if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
+ if (status_l0 & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
+ status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
+ val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
+ if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
dev_info(pci->dev, "CDM check complete\n");
- tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
+ val |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
}
- if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
+ if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
dev_err(pci->dev, "CDM comparison mismatch\n");
- tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
+ val |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
}
- if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
+ if (status_l1 & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
dev_err(pci->dev, "CDM Logic error\n");
- tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
+ val |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
}
- dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp);
- tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
- dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp);
+ dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
+ val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
+ dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val);
}
return IRQ_HANDLED;
@@ -454,6 +476,9 @@ static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg)
PCI_EXP_LNKSTA_CLS;
clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
+ if (!pcie->of_data->ltr_req_fixup)
+ return IRQ_HANDLED;
+
/* If EP doesn't advertise L1SS, just return */
val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2)))
@@ -538,13 +563,18 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg)
static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
+ struct pcie_port *pp = bus->sysdata;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
+
/*
* This is an endpoint mode specific register happen to appear even
* when controller is operating in root port mode and system hangs
* when it is accessed with link being in ASPM-L1 state.
* So skip accessing it altogether
*/
- if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) {
+ if (pcie->of_data->msix_doorbell_access_fixup &&
+ !PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) {
*val = 0x00000000;
return PCIBIOS_SUCCESSFUL;
}
@@ -555,13 +585,18 @@ static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where,
static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 val)
{
+ struct pcie_port *pp = bus->sysdata;
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
+
/*
* This is an endpoint mode specific register happen to appear even
* when controller is operating in root port mode and system hangs
* when it is accessed with link being in ASPM-L1 state.
* So skip accessing it altogether
*/
- if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL)
+ if (pcie->of_data->msix_doorbell_access_fixup &&
+ !PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL)
return PCIBIOS_SUCCESSFUL;
return pci_generic_config_write(bus, devfn, where, size, val);
@@ -709,13 +744,15 @@ static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
appl_writel(pcie, val, APPL_INTR_EN_L0_0);
- val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
- val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN;
- appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
+ if (pcie->of_data->sbr_reset_fixup) {
+ val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
+ val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN;
+ appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
+ }
if (pcie->enable_cdm_check) {
val = appl_readl(pcie, APPL_INTR_EN_L0_0);
- val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN;
+ val |= pcie->of_data->cdm_chk_int_en;
appl_writel(pcie, val, APPL_INTR_EN_L0_0);
val = appl_readl(pcie, APPL_INTR_EN_L1_18);
@@ -842,7 +879,8 @@ static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
- val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
+ val |= (pcie->of_data->gen4_preset_vec <<
+ GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
@@ -856,6 +894,7 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
u32 val;
+ u16 val_16;
pp->bridge->ops = &tegra_pci_ops;
@@ -863,6 +902,11 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
PCI_CAP_ID_EXP);
+ val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
+ val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
+ val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
+ dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
+
val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
@@ -887,6 +931,15 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
+ /* Clear Slot Clock Configuration bit if SRNS configuration */
+ if (pcie->enable_srns) {
+ val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
+ PCI_EXP_LNKSTA);
+ val_16 &= ~PCI_EXP_LNKSTA_SLC;
+ dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
+ val_16);
+ }
+
config_gen3_gen4_eq_presets(pcie);
init_host_aspm(pcie);
@@ -897,9 +950,11 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp)
disable_aspm_l12(pcie);
}
- val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
- val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
- dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+ if (pcie->of_data->l1ss_exit_fixup) {
+ val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
+ val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
+ dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+ }
if (pcie->update_fc_fixup) {
val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
@@ -919,8 +974,11 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
struct pcie_port *pp = &pci->pp;
bool retry = true;
- if (pcie->mode == DW_PCIE_EP_TYPE) {
- enable_irq(pcie->pex_rst_irq);
+ if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
+ if (!pcie->pex_rst_irq_enabled) {
+ enable_irq(pcie->pex_rst_irq);
+ pcie->pex_rst_irq_enabled = true;
+ }
return 0;
}
@@ -978,7 +1036,7 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci)
offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF);
val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
val &= ~PCI_DLF_EXCHANGE_ENABLE;
- dw_pcie_writel_dbi(pci, offset, val);
+ dw_pcie_writel_dbi(pci, offset + PCI_DLF_CAP, val);
tegra_pcie_dw_host_init(pp);
dw_pcie_setup_rc(pp);
@@ -1111,13 +1169,26 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
if (of_property_read_bool(np, "nvidia,update-fc-fixup"))
pcie->update_fc_fixup = true;
+ pcie->enable_ext_refclk =
+ of_property_read_bool(pcie->dev->of_node,
+ "nvidia,enable-ext-refclk");
+ /* RP using an external REFCLK is supported only in Tegra234 */
+ if (pcie->of_data->version == TEGRA194_DWC_IP_VER) {
+ if (pcie->of_data->mode == DW_PCIE_RC_TYPE)
+ pcie->enable_ext_refclk = false;
+ else
+ pcie->enable_ext_refclk = true;
+ }
+
pcie->supports_clkreq =
of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
pcie->enable_cdm_check =
of_property_read_bool(np, "snps,enable-cdm-check");
- if (pcie->mode == DW_PCIE_RC_TYPE)
+ pcie->enable_srns = of_property_read_bool(np, "nvidia,enable-srns");
+
+ if (pcie->of_data->mode == DW_PCIE_RC_TYPE)
return 0;
/* Endpoint mode specific DT entries */
@@ -1161,8 +1232,11 @@ static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
struct tegra_bpmp_message msg;
struct mrq_uphy_request req;
- /* Controller-5 doesn't need to have its state set by BPMP-FW */
- if (pcie->cid == 5)
+ /*
+ * Controller-5 doesn't need to have its state set by BPMP-FW in
+ * Tegra194
+ */
+ if (pcie->cid == 5 && pcie->of_data->version == TEGRA194_DWC_IP_VER)
return 0;
memset(&req, 0, sizeof(req));
@@ -1328,6 +1402,14 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
return ret;
}
+ if (pcie->enable_ext_refclk) {
+ ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
+ if (ret) {
+ dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret);
+ goto fail_pll_init;
+ }
+ }
+
ret = tegra_pcie_enable_slot_regulators(pcie);
if (ret < 0)
goto fail_slot_reg_en;
@@ -1351,11 +1433,13 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
goto fail_core_apb_rst;
}
- if (en_hw_hot_rst) {
+ if (en_hw_hot_rst || !pcie->of_data->sbr_reset_fixup) {
/* Enable HW_HOT_RST mode */
val = appl_readl(pcie, APPL_CTRL);
val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
+ val |= (APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST_LTSSM_EN <<
+ APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
val |= APPL_CTRL_HW_HOT_RST_EN;
appl_writel(pcie, val, APPL_CTRL);
}
@@ -1382,6 +1466,19 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
appl_writel(pcie, val, APPL_CFG_MISC);
+ if (pcie->enable_srns || pcie->enable_ext_refclk) {
+ /*
+ * When Tegra PCIe RP is using external clock, it cannot
+ * supply same clock to its downstream hierarchy.
+ * Hence, gate PCIe RP REFCLK out pads when RP & EP are
+ * using separate clocks or RP is using an external REFCLK.
+ */
+ val = appl_readl(pcie, APPL_PINMUX);
+ val |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
+ val &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
+ appl_writel(pcie, val, APPL_PINMUX);
+ }
+
if (!pcie->supports_clkreq) {
val = appl_readl(pcie, APPL_PINMUX);
val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
@@ -1407,6 +1504,9 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
fail_reg_en:
tegra_pcie_disable_slot_regulators(pcie);
fail_slot_reg_en:
+ if (pcie->enable_ext_refclk)
+ tegra_pcie_bpmp_set_pll_state(pcie, false);
+fail_pll_init:
tegra_pcie_bpmp_set_ctrl_state(pcie, false);
return ret;
@@ -1434,6 +1534,12 @@ static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie)
tegra_pcie_disable_slot_regulators(pcie);
+ if (pcie->enable_ext_refclk) {
+ ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
+ if (ret)
+ dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret);
+ }
+
ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
if (ret)
dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
@@ -1634,6 +1740,13 @@ static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
pm_runtime_put_sync(pcie->dev);
+ if (pcie->enable_ext_refclk) {
+ ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
+ if (ret)
+ dev_err(pcie->dev, "Failed to turn off UPHY: %d\n",
+ ret);
+ }
+
ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
if (ret)
dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
@@ -1649,6 +1762,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
struct device *dev = pcie->dev;
u32 val;
int ret;
+ u16 val_16;
if (pcie->ep_state == EP_STATE_ENABLED)
return;
@@ -1660,10 +1774,20 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
return;
}
- ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
+ ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
if (ret) {
- dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n", ret);
- goto fail_pll_init;
+ dev_err(pcie->dev, "Failed to enable controller %u: %d\n",
+ pcie->cid, ret);
+ goto fail_set_ctrl_state;
+ }
+
+ if (pcie->enable_ext_refclk) {
+ ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
+ if (ret) {
+ dev_err(dev, "Failed to init UPHY for PCIe EP: %d\n",
+ ret);
+ goto fail_pll_init;
+ }
}
ret = clk_prepare_enable(pcie->core_clk);
@@ -1760,12 +1884,29 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
disable_aspm_l12(pcie);
}
- val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
- val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
- dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+ if (pcie->of_data->l1ss_exit_fixup) {
+ val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
+ val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
+ dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
+ }
pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
PCI_CAP_ID_EXP);
+
+ val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL);
+ val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
+ val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B;
+ dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16);
+
+ /* Clear Slot Clock Configuration bit if SRNS configuration */
+ if (pcie->enable_srns) {
+ val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
+ PCI_EXP_LNKSTA);
+ val_16 &= ~PCI_EXP_LNKSTA_SLC;
+ dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
+ val_16);
+ }
+
clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
@@ -1782,6 +1923,13 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
dw_pcie_ep_init_notify(ep);
+ /* Send LTR upstream */
+ if (!pcie->of_data->ltr_req_fixup) {
+ val = appl_readl(pcie, APPL_LTR_MSG_2);
+ val |= APPL_LTR_MSG_2_LTR_MSG_REQ_STATE;
+ appl_writel(pcie, val, APPL_LTR_MSG_2);
+ }
+
/* Enable LTSSM */
val = appl_readl(pcie, APPL_CTRL);
val |= APPL_CTRL_LTSSM_EN;
@@ -1802,6 +1950,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
fail_core_clk_enable:
tegra_pcie_bpmp_set_pll_state(pcie, false);
fail_pll_init:
+ tegra_pcie_bpmp_set_ctrl_state(pcie, false);
+fail_set_ctrl_state:
pm_runtime_put_sync(dev);
}
@@ -1931,6 +2081,7 @@ static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN);
+ pcie->pex_rst_irq_enabled = false;
pcie->ep_state = EP_STATE_DISABLED;
ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL,
@@ -1978,14 +2129,13 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
pci = &pcie->pci;
pci->dev = &pdev->dev;
pci->ops = &tegra_dw_pcie_ops;
- pci->n_fts[0] = N_FTS_VAL;
- pci->n_fts[1] = FTS_VAL;
- pci->version = 0x490A;
-
+ pcie->dev = &pdev->dev;
+ pcie->of_data = (struct tegra_pcie_dw_of_data *)data;
+ pci->n_fts[0] = pcie->of_data->n_fts[0];
+ pci->n_fts[1] = pcie->of_data->n_fts[1];
+ pci->version = pcie->of_data->version;
pp = &pci->pp;
pp->num_vectors = MAX_MSI_IRQS;
- pcie->dev = &pdev->dev;
- pcie->mode = (enum dw_pcie_device_mode)data->mode;
ret = tegra_pcie_dw_parse_dt(pcie);
if (ret < 0) {
@@ -2102,7 +2252,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, pcie);
- switch (pcie->mode) {
+ switch (pcie->of_data->mode) {
case DW_PCIE_RC_TYPE:
ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler,
IRQF_SHARED, "tegra-pcie-intr", pcie);
@@ -2137,7 +2287,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
break;
default:
- dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode);
+ dev_err(dev, "Invalid PCIe device type %d\n",
+ pcie->of_data->mode);
}
fail:
@@ -2149,12 +2300,19 @@ static int tegra_pcie_dw_remove(struct platform_device *pdev)
{
struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
- if (!pcie->link_state)
- return 0;
+ if (pcie->of_data->mode == DW_PCIE_RC_TYPE) {
+ if (!pcie->link_state)
+ return 0;
+
+ debugfs_remove_recursive(pcie->debugfs);
+ tegra_pcie_deinit_controller(pcie);
+ pm_runtime_put_sync(pcie->dev);
+ } else {
+ if (pcie->pex_rst_irq_enabled)
+ disable_irq(pcie->pex_rst_irq);
+ pex_ep_event_pex_rst_assert(pcie);
+ }
- debugfs_remove_recursive(pcie->debugfs);
- tegra_pcie_deinit_controller(pcie);
- pm_runtime_put_sync(pcie->dev);
pm_runtime_disable(pcie->dev);
tegra_bpmp_put(pcie->bpmp);
if (pcie->pex_refclk_sel_gpiod)
@@ -2168,15 +2326,22 @@ static int tegra_pcie_dw_suspend_late(struct device *dev)
struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
u32 val;
+ if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
+ dev_err(dev, "Failed to Suspend as Tegra PCIe is in EP mode\n");
+ return -EPERM;
+ }
+
if (!pcie->link_state)
return 0;
/* Enable HW_HOT_RST mode */
- val = appl_readl(pcie, APPL_CTRL);
- val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
- APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
- val |= APPL_CTRL_HW_HOT_RST_EN;
- appl_writel(pcie, val, APPL_CTRL);
+ if (pcie->of_data->sbr_reset_fixup) {
+ val = appl_readl(pcie, APPL_CTRL);
+ val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
+ APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
+ val |= APPL_CTRL_HW_HOT_RST_EN;
+ appl_writel(pcie, val, APPL_CTRL);
+ }
return 0;
}
@@ -2231,7 +2396,7 @@ static int tegra_pcie_dw_resume_early(struct device *dev)
struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
u32 val;
- if (pcie->mode == DW_PCIE_EP_TYPE) {
+ if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
dev_err(dev, "Suspend is not supported in EP mode");
return -ENOTSUPP;
}
@@ -2240,13 +2405,15 @@ static int tegra_pcie_dw_resume_early(struct device *dev)
return 0;
/* Disable HW_HOT_RST mode */
- val = appl_readl(pcie, APPL_CTRL);
- val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
- APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
- val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
- APPL_CTRL_HW_HOT_RST_MODE_SHIFT;
- val &= ~APPL_CTRL_HW_HOT_RST_EN;
- appl_writel(pcie, val, APPL_CTRL);
+ if (pcie->of_data->sbr_reset_fixup) {
+ val = appl_readl(pcie, APPL_CTRL);
+ val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
+ APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
+ val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
+ APPL_CTRL_HW_HOT_RST_MODE_SHIFT;
+ val &= ~APPL_CTRL_HW_HOT_RST_EN;
+ appl_writel(pcie, val, APPL_CTRL);
+ }
return 0;
}
@@ -2255,36 +2422,95 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
{
struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
- if (!pcie->link_state)
- return;
+ if (pcie->of_data->mode == DW_PCIE_RC_TYPE) {
+ if (!pcie->link_state)
+ return;
- debugfs_remove_recursive(pcie->debugfs);
- tegra_pcie_downstream_dev_to_D0(pcie);
+ debugfs_remove_recursive(pcie->debugfs);
+ tegra_pcie_downstream_dev_to_D0(pcie);
- disable_irq(pcie->pci.pp.irq);
- if (IS_ENABLED(CONFIG_PCI_MSI))
- disable_irq(pcie->pci.pp.msi_irq);
+ disable_irq(pcie->pci.pp.irq);
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ disable_irq(pcie->pci.pp.msi_irq);
- tegra_pcie_dw_pme_turnoff(pcie);
- tegra_pcie_unconfig_controller(pcie);
+ tegra_pcie_dw_pme_turnoff(pcie);
+ tegra_pcie_unconfig_controller(pcie);
+ pm_runtime_put_sync(pcie->dev);
+ } else {
+ if (pcie->pex_rst_irq_enabled)
+ disable_irq(pcie->pex_rst_irq);
+ pex_ep_event_pex_rst_assert(pcie);
+ }
}
-static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = {
+static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_rc_of_data = {
+ .version = TEGRA194_DWC_IP_VER,
+ .mode = DW_PCIE_RC_TYPE,
+ .msix_doorbell_access_fixup = true,
+ .sbr_reset_fixup = true,
+ .l1ss_exit_fixup = true,
+ .ltr_req_fixup = false,
+ .cdm_chk_int_en = BIT(19),
+ /* Gen4 - 5, 6, 8 and 9 presets enabled */
+ .gen4_preset_vec = 0x360,
+ .n_fts = { 52, 52 },
+};
+
+static const struct tegra_pcie_dw_of_data tegra194_pcie_dw_ep_of_data = {
+ .version = TEGRA194_DWC_IP_VER,
+ .mode = DW_PCIE_EP_TYPE,
+ .msix_doorbell_access_fixup = false,
+ .sbr_reset_fixup = false,
+ .l1ss_exit_fixup = true,
+ .ltr_req_fixup = true,
+ .cdm_chk_int_en = BIT(19),
+ /* Gen4 - 5, 6, 8 and 9 presets enabled */
+ .gen4_preset_vec = 0x360,
+ .n_fts = { 52, 52 },
+};
+
+static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_rc_of_data = {
+ .version = TEGRA234_DWC_IP_VER,
.mode = DW_PCIE_RC_TYPE,
+ .msix_doorbell_access_fixup = false,
+ .sbr_reset_fixup = false,
+ .l1ss_exit_fixup = false,
+ .ltr_req_fixup = false,
+ .cdm_chk_int_en = BIT(18),
+ /* Gen4 - 6, 8 and 9 presets enabled */
+ .gen4_preset_vec = 0x340,
+ .n_fts = { 52, 80 },
};
-static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data = {
+static const struct tegra_pcie_dw_of_data tegra234_pcie_dw_ep_of_data = {
+ .version = TEGRA234_DWC_IP_VER,
.mode = DW_PCIE_EP_TYPE,
+ .msix_doorbell_access_fixup = false,
+ .sbr_reset_fixup = false,
+ .l1ss_exit_fixup = false,
+ .ltr_req_fixup = false,
+ .cdm_chk_int_en = BIT(18),
+ /* Gen4 - 6, 8 and 9 presets enabled */
+ .gen4_preset_vec = 0x340,
+ .n_fts = { 52, 80 },
};
static const struct of_device_id tegra_pcie_dw_of_match[] = {
{
.compatible = "nvidia,tegra194-pcie",
- .data = &tegra_pcie_dw_rc_of_data,
+ .data = &tegra194_pcie_dw_rc_of_data,
},
{
.compatible = "nvidia,tegra194-pcie-ep",
- .data = &tegra_pcie_dw_ep_of_data,
+ .data = &tegra194_pcie_dw_ep_of_data,
+ },
+ {
+ .compatible = "nvidia,tegra234-pcie",
+ .data = &tegra234_pcie_dw_rc_of_data,
+ },
+ {
+ .compatible = "nvidia,tegra234-pcie-ep",
+ .data = &tegra234_pcie_dw_ep_of_data,
},
{},
};
--
2.17.1
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