[PATCH] PCI: tegra194: Set address alignment for endpoint mode

[PATCH] PCI: tegra194: Set address alignment for endpoint mode

[Jon Hunter]

Tegra194 and Tegra234 devices require that the endpoint address is
aligned on a 64kB boundary and therefore, set the endpoint address
alignment to 64kB in the Tegra194 PCIe driver.

Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
Suggested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 93f5433c5c55..4537313ef37a 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -2015,6 +2015,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
 	.bar[BAR_3] = { .type = BAR_RESERVED, },
 	.bar[BAR_4] = { .type = BAR_RESERVED, },
 	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.align = SZ_64K,
 };
 
 static const struct pci_epc_features*
-- 
2.34.1

Re: [PATCH] PCI: tegra194: Set address alignment for endpoint mode

[Niklas Cassel]

On Fri, Apr 26, 2024 at 01:27:31PM +0100, Jon Hunter wrote:
> Tegra194 and Tegra234 devices require that the endpoint address is
> aligned on a 64kB boundary and therefore, set the endpoint address
> alignment to 64kB in the Tegra194 PCIe driver.

Hello Jon,

While I think the change in this patch looks good,
I think you need to rephrase your commit message.

The 'align' of pci_epc_features represents inbound ATU constraints.
(So for BAR access.)
See Kishon reply at:
https://lore.kernel.org/linux-pci/dccb87db-d826-43fa-a499-cf36ea9b10d5@amd.com/T/#m7697d1d745d8499fc6b8db855b7f93dafd7ed5b3


Kind regards,
Niklas

> 
> Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194")
> Suggested-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 93f5433c5c55..4537313ef37a 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -2015,6 +2015,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
>  	.bar[BAR_3] = { .type = BAR_RESERVED, },
>  	.bar[BAR_4] = { .type = BAR_RESERVED, },
>  	.bar[BAR_5] = { .type = BAR_RESERVED, },
> +	.align = SZ_64K,
>  };
>  
>  static const struct pci_epc_features*
> -- 
> 2.34.1
> 

Re: [PATCH] PCI: tegra194: Set address alignment for endpoint mode

[Jon Hunter]

On 26/04/2024 13:54, Niklas Cassel wrote:
> On Fri, Apr 26, 2024 at 01:27:31PM +0100, Jon Hunter wrote:
>> Tegra194 and Tegra234 devices require that the endpoint address is
>> aligned on a 64kB boundary and therefore, set the endpoint address
>> alignment to 64kB in the Tegra194 PCIe driver.
> 
> Hello Jon,
> 
> While I think the change in this patch looks good,
> I think you need to rephrase your commit message.
> 
> The 'align' of pci_epc_features represents inbound ATU constraints.
> (So for BAR access.)
> See Kishon reply at:
> https://lore.kernel.org/linux-pci/dccb87db-d826-43fa-a499-cf36ea9b10d5@amd.com/T/#m7697d1d745d8499fc6b8db855b7f93dafd7ed5b3


Thanks! I will fix up the commit message and re-send.

Jon