From: Marek Szyprowski <m.szyprowski@samsung.com>
To: Rob Herring <robh@kernel.org>
Cc: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Jaehoon Chung <jh80.chung@samsung.com>,
Jingoo Han <jingoohan1@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>
Subject: Re: [PATCH v3 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding
Date: Thu, 5 Nov 2020 09:33:18 +0100 [thread overview]
Message-ID: <d89f5f0a-c45e-0bda-4db7-7b0cf9cd49fe@samsung.com> (raw)
In-Reply-To: <20201104213539.GA4144654@bogus>
Hi Rob,
On 04.11.2020 22:35, Rob Herring wrote:
> On Thu, Oct 29, 2020 at 02:40:13PM +0100, Marek Szyprowski wrote:
>> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
>> variant). Based on the text dt-binding posted by Jaehoon Chung.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
>> ---
>> .../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++++++++++++++
>> 1 file changed, 119 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>> ...
>> + num-viewport:
>> + const: 3
> I'm confused why you need this. This is only used with the iATU except
> for keystone. Platforms like Exynos with their own child bus config
> space accessors don't have an iATU.
Frankly I have no idea, I don't know much about the PCI internals. After
rebasing onto your latest DW PCI changes I've noticed a following
warning message:
exynos-pcie 15700000.pcie: Resources exceed number of ATU entries (2)
Here is a complete log:
# dmesg | grep pci
ehci-pci: EHCI PCI platform driver
ohci-pci: OHCI PCI platform driver
exynos-pcie 15700000.pcie: host bridge /soc@0/pcie@15700000 ranges:
exynos-pcie 15700000.pcie: IO 0x000c001000..0x000c010fff ->
0x0000000000
exynos-pcie 15700000.pcie: MEM 0x000c011000..0x000ffffffe ->
0x000c011000
exynos-pcie 15700000.pcie: Resources exceed number of ATU entries (2)
exynos-pcie 15700000.pcie: Link up
exynos-pcie 15700000.pcie: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [bus 00-ff]
pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
pci_bus 0000:00: root bus resource [mem 0x0c011000-0x0ffffffe]
pci 0000:00:00.0: [144d:a5e3] type 01 class 0x060400
pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
pci 0000:01:00.0: [14e4:43e9] type 00 class 0x028000
pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]
pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x003fffff 64bit]
pci 0000:01:00.0: supports D1 D2
pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
pci 0000:00:00.0: BAR 14: assigned [mem 0x0c200000-0x0c7fffff]
pci 0000:01:00.0: BAR 2: assigned [mem 0x0c400000-0x0c7fffff 64bit]
pci 0000:01:00.0: BAR 0: assigned [mem 0x0c200000-0x0c207fff 64bit]
pci 0000:00:00.0: PCI bridge to [bus 01-ff]
pci 0000:00:00.0: bridge window [mem 0x0c200000-0x0c7fffff]
pci 0000:00:00.0: MSI quirk detected; MSI disabled
pcieport 0000:00:00.0: PME: Signaling with IRQ 97
brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac4358-pcie for chip
BCM4358/1
When I've increased the numer of viewports it has gone.
If this is not the proper solution, I will removed it.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
next prev parent reply other threads:[~2020-11-05 8:33 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20201029134037eucas1p17f861adc0858e8a80d516dc0f2733f84@eucas1p1.samsung.com>
2020-10-29 13:40 ` [PATCH v3 0/6] Add DW PCIe support for Exynos5433 SoCs Marek Szyprowski
[not found] ` <CGME20201029134037eucas1p275bad9fe08eff145711cc36ac8c685f7@eucas1p2.samsung.com>
2020-10-29 13:40 ` [PATCH v3 1/6] dt-bindings: pci: drop samsung,exynos5440-pcie binding Marek Szyprowski
[not found] ` <CGME20201029134038eucas1p28d9bd33bc9e36b960b021a40ef299b47@eucas1p2.samsung.com>
2020-10-29 13:40 ` [PATCH v3 2/6] dt-bindings: pci: add the samsung,exynos-pcie binding Marek Szyprowski
2020-11-04 21:35 ` Rob Herring
2020-11-05 8:33 ` Marek Szyprowski [this message]
2020-11-05 15:27 ` Rob Herring
2020-11-05 17:14 ` Jingoo Han
[not found] ` <CGME20201029134038eucas1p2d550a45ff3222ccb72d15d5c89d4f938@eucas1p2.samsung.com>
2020-10-29 13:40 ` [PATCH v3 3/6] dt-bindings: phy: add the samsung,exynos-pcie-phy binding Marek Szyprowski
2020-11-04 21:39 ` Rob Herring
[not found] ` <CGME20201029134039eucas1p2270e5f4ecea05b17f4d9107300ce946d@eucas1p2.samsung.com>
2020-10-29 13:40 ` [PATCH v3 4/6] phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY Marek Szyprowski
[not found] ` <CGME20201029134040eucas1p1d9ab30c75ac9243346b4786e7048d6be@eucas1p1.samsung.com>
2020-10-29 13:40 ` [PATCH v3 5/6] pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant Marek Szyprowski
2020-10-29 21:59 ` Jingoo Han
2020-11-04 21:39 ` Rob Herring
[not found] ` <CGME20201029134040eucas1p2a8958b44842a8a4647e3aa4521c75725@eucas1p2.samsung.com>
2020-10-29 13:40 ` [PATCH v3 6/6] arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards Marek Szyprowski
2020-11-05 19:14 ` Krzysztof Kozlowski
2020-11-03 22:44 ` [PATCH v3 0/6] Add DW PCIe support for Exynos5433 SoCs Bjorn Helgaas
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