[PATCH v3 0/2] PCI: mediatek-gen3: Add support for disable dvfsrc

[PATCH v3 0/2] PCI: mediatek-gen3: Add support for disable dvfsrc

[Jianjun Wang]

These series patches add support for disable dvfsrc voltage request.

Changes in v3:
Fix typo.

Changes in v2:
Fix typo.

Jianjun Wang (2):
  dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc
    voltage request
  PCI: mediatek-gen3: Add support for disable dvfsrc voltage request

 .../bindings/pci/mediatek-pcie-gen3.yaml      |  8 +++++
 drivers/pci/controller/pcie-mediatek-gen3.c   | 31 +++++++++++++++++++
 2 files changed, 39 insertions(+)

-- 
2.18.0

[PATCH v3 1/2] dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc voltage request

[Jianjun Wang]

Add property to disable dvfsrc voltage request, if this property
is presented, we assume that the requested voltage is always
higher enough to keep the PCIe controller active.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
---
 .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml       | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index e7b1f9892da4..3e26c032cea9 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -96,6 +96,12 @@ properties:
   phys:
     maxItems: 1
 
+  disable-dvfsrc-vlt-req:
+    description: Disable dvfsrc voltage request, if this property is presented,
+      we assume that the requested voltage is always higher enough to keep
+      the PCIe controller active.
+    type: boolean
+
   '#interrupt-cells':
     const: 1
 
@@ -166,6 +172,8 @@ examples:
                      <&infracfg_rst 3>;
             reset-names = "phy", "mac";
 
+            disable-dvfsrc-vlt-req;
+
             #interrupt-cells = <1>;
             interrupt-map-mask = <0 0 0 0x7>;
             interrupt-map = <0 0 0 1 &pcie_intc 0>,
-- 
2.18.0

Re: [PATCH v3 1/2] dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc voltage request

[Qizhong Cheng]

Reviewed-by: Qizhong Cheng <qizhong.cheng@mediatek.com>
Tested-by: Qizhong Cheng <qizhong.cheng@mediatek.com>

On Wed, 2021-06-30 at 10:49 +0800, Jianjun Wang wrote:
> Add property to disable dvfsrc voltage request, if this property
> is presented, we assume that the requested voltage is always
> higher enough to keep the PCIe controller active.
> 
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> ---
>  .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml       | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> index e7b1f9892da4..3e26c032cea9 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> @@ -96,6 +96,12 @@ properties:
>    phys:
>      maxItems: 1
>  
> +  disable-dvfsrc-vlt-req:
> +    description: Disable dvfsrc voltage request, if this property is presented,
> +      we assume that the requested voltage is always higher enough to keep
> +      the PCIe controller active.
> +    type: boolean
> +
>    '#interrupt-cells':
>      const: 1
>  
> @@ -166,6 +172,8 @@ examples:
>                       <&infracfg_rst 3>;
>              reset-names = "phy", "mac";
>  
> +            disable-dvfsrc-vlt-req;
> +
>              #interrupt-cells = <1>;
>              interrupt-map-mask = <0 0 0 0x7>;
>              interrupt-map = <0 0 0 1 &pcie_intc 0>,

Re: [PATCH v3 1/2] dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc voltage request

[Jianjun Wang]

Hi,

Just gentle ping for this patch set, please kindly let me know your
comments about this patch set.

Thanks.

On Wed, 2021-06-30 at 11:40 +0800, Qizhong Cheng wrote:
> Reviewed-by: Qizhong Cheng <qizhong.cheng@mediatek.com>
> Tested-by: Qizhong Cheng <qizhong.cheng@mediatek.com>
> 
> On Wed, 2021-06-30 at 10:49 +0800, Jianjun Wang wrote:
> > Add property to disable dvfsrc voltage request, if this property
> > is presented, we assume that the requested voltage is always
> > higher enough to keep the PCIe controller active.
> > 
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > ---
> >  .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml       | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > index e7b1f9892da4..3e26c032cea9 100644
> > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -96,6 +96,12 @@ properties:
> >    phys:
> >      maxItems: 1
> >  
> > +  disable-dvfsrc-vlt-req:
> > +    description: Disable dvfsrc voltage request, if this property is presented,
> > +      we assume that the requested voltage is always higher enough to keep
> > +      the PCIe controller active.
> > +    type: boolean
> > +
> >    '#interrupt-cells':
> >      const: 1
> >  
> > @@ -166,6 +172,8 @@ examples:
> >                       <&infracfg_rst 3>;
> >              reset-names = "phy", "mac";
> >  
> > +            disable-dvfsrc-vlt-req;
> > +
> >              #interrupt-cells = <1>;
> >              interrupt-map-mask = <0 0 0 0x7>;
> >              interrupt-map = <0 0 0 1 &pcie_intc 0>,
> 
> 

Re: [PATCH v3 1/2] dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc voltage request

[Rob Herring]

On Wed, Jun 30, 2021 at 10:49:33AM +0800, Jianjun Wang wrote:
> Add property to disable dvfsrc voltage request, if this property
> is presented, we assume that the requested voltage is always
> higher enough to keep the PCIe controller active.
> 
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> ---
>  .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml       | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> index e7b1f9892da4..3e26c032cea9 100644
> --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> @@ -96,6 +96,12 @@ properties:
>    phys:
>      maxItems: 1
>  
> +  disable-dvfsrc-vlt-req:
> +    description: Disable dvfsrc voltage request, if this property is presented,
> +      we assume that the requested voltage is always higher enough to keep
> +      the PCIe controller active.
> +    type: boolean

What determines setting this property? Can it be implied by the 
compatible (which should be SoC specific).

Is this property specific to PCIe controller? 

Wouldn't the request be harmless to make the voltage request even if not 
needed?

I think this probably should be addressed in a common way as part of 
other QoS, devfreq, etc. requirements for devices.

Rob

Re: [PATCH v3 1/2] dt-bindings: PCI: mediatek-gen3: Add property to disable dvfsrc voltage request

[Jianjun Wang (王建军)]

On Fri, 2021-07-16 at 11:33 -0600, Rob Herring wrote:
> On Wed, Jun 30, 2021 at 10:49:33AM +0800, Jianjun Wang wrote:
> > Add property to disable dvfsrc voltage request, if this property
> > is presented, we assume that the requested voltage is always
> > higher enough to keep the PCIe controller active.
> > 
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > ---
> >  .../devicetree/bindings/pci/mediatek-pcie-gen3.yaml       | 8
> > ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-
> > gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-
> > gen3.yaml
> > index e7b1f9892da4..3e26c032cea9 100644
> > --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
> > @@ -96,6 +96,12 @@ properties:
> >    phys:
> >      maxItems: 1
> >  
> > +  disable-dvfsrc-vlt-req:
> > +    description: Disable dvfsrc voltage request, if this property
> > is presented,
> > +      we assume that the requested voltage is always higher enough
> > to keep
> > +      the PCIe controller active.
> > +    type: boolean
> What determines setting this property? Can it be implied by the 
> compatible (which should be SoC specific).
> 
> Is this property specific to PCIe controller? 
> 
> Wouldn't the request be harmless to make the voltage request even if
> not 
> needed?
> 
> I think this probably should be addressed in a common way as part of 
> other QoS, devfreq, etc. requirements for devices.
> 
> Rob

Hi Rob,

Thanks for your review and sorry for the late response.

We have internal discussion and we agree with that this feature should
not be specific to the PCIe controller, we need to find a common way to
do this. 

But as the driver of dvfsrc is not finished the upstream, we don't have
a better solution for now, so we would like to pull back this patch and
will send another patch to disable dvfsrc by default until we find a
common solution to enable it.

Thanks.

[PATCH v3 2/2] PCI: mediatek-gen3: Add support for disable dvfsrc voltage request

[Jianjun Wang]

PCIe Gen3 PHY layer cannot work properly when the requested voltage
is lower than a specific level(e.g. 0.55V, it's depends on
the chip manufacturing process).

When the dvfsrc feature is implemented, the requested voltage
may be reduced to a lower level in suspend mode, hence that
the MAC layer will assert a HW signal to request the dvfsrc
to raise voltage to normal mode, and it will wait the voltage
ready signal from dvfsrc to decide if the LTSSM can start normally.

When the dvfsrc feature is not implemented, the MAC layer still
assert the voltage request to dvfsrc when exit suspend mode,
but will not receive the voltage ready signal, in this case,
the LTSSM cannot start normally, and the PCIe link will be failed.

Add support for disable dvfsrc voltage request, if the property of
"disable-dvfsrc-vlt-req" is presented in device node, we assume that
the requested voltage is always higher enough to keep the PCIe Gen3
PHY active, and the voltage request to dvfsrc should be disabled.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 31 +++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 3c5b97716d40..028014707588 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -79,6 +79,9 @@
 #define PCIE_ICMD_PM_REG		0x198
 #define PCIE_TURN_OFF_LINK		BIT(4)
 
+#define PCIE_MISC_CTRL_REG		0x348
+#define PCIE_DISABLE_DVFSRC_VLT_REQ	BIT(1)
+
 #define PCIE_TRANS_TABLE_BASE_REG	0x800
 #define PCIE_ATR_SRC_ADDR_MSB_OFFSET	0x4
 #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET	0x8
@@ -297,6 +300,34 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
 	val &= ~PCIE_INTX_ENABLE;
 	writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
 
+	/*
+	 * PCIe Gen3 PHY layer can not work properly when the requested voltage
+	 * is lower than a specific level(e.g. 0.55V, it's depends on
+	 * the chip manufacturing process).
+	 *
+	 * When the dvfsrc feature is implemented, the requested voltage
+	 * might be reduced to a lower level in suspend mode, hence that
+	 * the MAC layer will assert a HW signal to request the dvfsrc
+	 * to raise voltage to normal mode, and it will wait the voltage
+	 * ready signal from dvfsrc to start the LTSSM normally.
+	 *
+	 * When the dvfsrc feature is not implemented, the MAC layer still
+	 * assert the voltage request to dvfsrc when exit suspend mode,
+	 * but will not get the voltage ready signal, in this case, the LTSSM
+	 * cannot start normally, and the PCIe link will be failed.
+	 *
+	 * If the property of "disable-dvfsrc-vlt-req" is presented
+	 * in device node, we assume that the requested voltage is always
+	 * higher enough to keep the PCIe Gen3 PHY active, and the voltage
+	 * request to dvfsrc should be disabled.
+	 */
+	val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG);
+	val &= ~PCIE_DISABLE_DVFSRC_VLT_REQ;
+	if (of_property_read_bool(port->dev->of_node, "disable-dvfsrc-vlt-req"))
+		val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
+
+	writel_relaxed(val, port->base + PCIE_MISC_CTRL_REG);
+
 	/* Assert all reset signals */
 	val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
 	val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;
-- 
2.18.0

Re: [PATCH v3 2/2] PCI: mediatek-gen3: Add support for disable dvfsrc voltage request

[Qizhong Cheng]

Reviewed-by: Qizhong Cheng <qizhong.cheng@mediatek.com>
Tested-by: Qizhong Cheng <qizhong.cheng@mediatek.com>

On Wed, 2021-06-30 at 10:49 +0800, Jianjun Wang wrote:
> PCIe Gen3 PHY layer cannot work properly when the requested voltage
> is lower than a specific level(e.g. 0.55V, it's depends on
> the chip manufacturing process).
> 
> When the dvfsrc feature is implemented, the requested voltage
> may be reduced to a lower level in suspend mode, hence that
> the MAC layer will assert a HW signal to request the dvfsrc
> to raise voltage to normal mode, and it will wait the voltage
> ready signal from dvfsrc to decide if the LTSSM can start normally.
> 
> When the dvfsrc feature is not implemented, the MAC layer still
> assert the voltage request to dvfsrc when exit suspend mode,
> but will not receive the voltage ready signal, in this case,
> the LTSSM cannot start normally, and the PCIe link will be failed.
> 
> Add support for disable dvfsrc voltage request, if the property of
> "disable-dvfsrc-vlt-req" is presented in device node, we assume that
> the requested voltage is always higher enough to keep the PCIe Gen3
> PHY active, and the voltage request to dvfsrc should be disabled.
> 
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> ---
>  drivers/pci/controller/pcie-mediatek-gen3.c | 31 +++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 3c5b97716d40..028014707588 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -79,6 +79,9 @@
>  #define PCIE_ICMD_PM_REG		0x198
>  #define PCIE_TURN_OFF_LINK		BIT(4)
>  
> +#define PCIE_MISC_CTRL_REG		0x348
> +#define PCIE_DISABLE_DVFSRC_VLT_REQ	BIT(1)
> +
>  #define PCIE_TRANS_TABLE_BASE_REG	0x800
>  #define PCIE_ATR_SRC_ADDR_MSB_OFFSET	0x4
>  #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET	0x8
> @@ -297,6 +300,34 @@ static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
>  	val &= ~PCIE_INTX_ENABLE;
>  	writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG);
>  
> +	/*
> +	 * PCIe Gen3 PHY layer can not work properly when the requested voltage
> +	 * is lower than a specific level(e.g. 0.55V, it's depends on
> +	 * the chip manufacturing process).
> +	 *
> +	 * When the dvfsrc feature is implemented, the requested voltage
> +	 * might be reduced to a lower level in suspend mode, hence that
> +	 * the MAC layer will assert a HW signal to request the dvfsrc
> +	 * to raise voltage to normal mode, and it will wait the voltage
> +	 * ready signal from dvfsrc to start the LTSSM normally.
> +	 *
> +	 * When the dvfsrc feature is not implemented, the MAC layer still
> +	 * assert the voltage request to dvfsrc when exit suspend mode,
> +	 * but will not get the voltage ready signal, in this case, the LTSSM
> +	 * cannot start normally, and the PCIe link will be failed.
> +	 *
> +	 * If the property of "disable-dvfsrc-vlt-req" is presented
> +	 * in device node, we assume that the requested voltage is always
> +	 * higher enough to keep the PCIe Gen3 PHY active, and the voltage
> +	 * request to dvfsrc should be disabled.
> +	 */
> +	val = readl_relaxed(port->base + PCIE_MISC_CTRL_REG);
> +	val &= ~PCIE_DISABLE_DVFSRC_VLT_REQ;
> +	if (of_property_read_bool(port->dev->of_node, "disable-dvfsrc-vlt-req"))
> +		val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
> +
> +	writel_relaxed(val, port->base + PCIE_MISC_CTRL_REG);
> +
>  	/* Assert all reset signals */
>  	val = readl_relaxed(port->base + PCIE_RST_CTRL_REG);
>  	val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB;