* [PATCH v2 1/4] PCI: brcmstb: Break register definitions into separate header
2021-08-19 21:56 [PATCH v2 0/4] CM4 ACPI PCIe quirk Jeremy Linton
@ 2021-08-19 21:56 ` Jeremy Linton
2021-08-22 8:49 ` Florian Fainelli
2021-08-19 21:56 ` [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk Jeremy Linton
` (3 subsequent siblings)
4 siblings, 1 reply; 18+ messages in thread
From: Jeremy Linton @ 2021-08-19 21:56 UTC (permalink / raw)
To: linux-pci
Cc: lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh, kw,
f.fainelli, sdonthineni, stefan.wahren, bcm-kernel-feedback-list,
linux-acpi, linux-arm-kernel, linux-rpi-kernel, linux-kernel,
Jeremy Linton
We are about to create a standalone ACPI quirk module for the
bcmstb controller. Lets move the register definitions into a separate
file so they can be shared between the APCI quirk and the normal
host bridge driver.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
drivers/pci/controller/pcie-brcmstb.c | 150 +------------------------
drivers/pci/controller/pcie-brcmstb.h | 155 ++++++++++++++++++++++++++
2 files changed, 157 insertions(+), 148 deletions(-)
create mode 100644 drivers/pci/controller/pcie-brcmstb.h
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 08bc788d9422..59a19ae59c8f 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -31,159 +31,12 @@
#include <linux/types.h>
#include "../pci.h"
-
-/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
-#define BRCM_PCIE_CAP_REGS 0x00ac
-
-/* Broadcom STB PCIe Register Offsets */
-#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
-#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
-#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
-
-#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
-#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
-
-#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
-#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
-
-#define PCIE_RC_DL_MDIO_ADDR 0x1100
-#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
-#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
-
-#define PCIE_MISC_MISC_CTRL 0x4008
-#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
-#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
-#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
-
-#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
-#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
-#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
-#define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
-#define PCIE_MEM_WIN0_LO(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
-#define PCIE_MEM_WIN0_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
-
-#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
-#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
-
-#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
-#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
-#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
-
-#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
-#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
-
-#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
-#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
-
-#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
-#define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
-#define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
-
-#define PCIE_MISC_PCIE_CTRL 0x4064
-#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
-#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
-
-#define PCIE_MISC_PCIE_STATUS 0x4068
-#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
-#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
-#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
-#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
-
-#define PCIE_MISC_REVISION 0x406c
-#define BRCM_PCIE_HW_REV_33 0x0303
-#define BRCM_PCIE_HW_REV_3_20 0x0320
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
-#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
-#define PCIE_MEM_WIN0_BASE_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
-
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
-#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
-#define PCIE_MEM_WIN0_LIMIT_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
-
-#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
-#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
-#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
-
-
-#define PCIE_INTR2_CPU_BASE 0x4300
-#define PCIE_MSI_INTR2_BASE 0x4500
-/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
-#define MSI_INT_STATUS 0x0
-#define MSI_INT_CLR 0x8
-#define MSI_INT_MASK_SET 0x10
-#define MSI_INT_MASK_CLR 0x14
-
-#define PCIE_EXT_CFG_DATA 0x8000
-#define PCIE_EXT_CFG_INDEX 0x9000
-
-#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
-#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
-
-#define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
-#define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
-#define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
-#define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
-
-/* PCIe parameters */
-#define BRCM_NUM_PCIE_OUT_WINS 0x4
-#define BRCM_INT_PCI_MSI_NR 32
-#define BRCM_INT_PCI_MSI_LEGACY_NR 8
-#define BRCM_INT_PCI_MSI_SHIFT 0
-
-/* MSI target adresses */
-#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
-#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
-
-/* MDIO registers */
-#define MDIO_PORT0 0x0
-#define MDIO_DATA_MASK 0x7fffffff
-#define MDIO_PORT_MASK 0xf0000
-#define MDIO_REGAD_MASK 0xffff
-#define MDIO_CMD_MASK 0xfff00000
-#define MDIO_CMD_READ 0x1
-#define MDIO_CMD_WRITE 0x0
-#define MDIO_DATA_DONE_MASK 0x80000000
-#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
-#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
-#define SSC_REGS_ADDR 0x1100
-#define SET_ADDR_OFFSET 0x1f
-#define SSC_CNTL_OFFSET 0x2
-#define SSC_CNTL_OVRD_EN_MASK 0x8000
-#define SSC_CNTL_OVRD_VAL_MASK 0x4000
-#define SSC_STATUS_OFFSET 0x1
-#define SSC_STATUS_SSC_MASK 0x400
-#define SSC_STATUS_PLL_LOCK_MASK 0x800
-#define PCIE_BRCM_MAX_MEMC 3
+#include "pcie-brcmstb.h"
#define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
#define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
#define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
-/* Rescal registers */
-#define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
-#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
-#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
-#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
-#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
-#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
-#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
-#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
-
/* Forward declarations */
struct brcm_pcie;
static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
@@ -192,6 +45,7 @@ static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
+
enum {
RGR1_SW_INIT_1,
EXT_CFG_INDEX,
diff --git a/drivers/pci/controller/pcie-brcmstb.h b/drivers/pci/controller/pcie-brcmstb.h
new file mode 100644
index 000000000000..fc20cc7ae02f
--- /dev/null
+++ b/drivers/pci/controller/pcie-brcmstb.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright (C) 2009 - 2021 Broadcom */
+
+#ifndef _PCIE_BRCMSTB_H
+#define _PCIE_BRCMSTB_H
+
+/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
+#define BRCM_PCIE_CAP_REGS 0x00ac
+
+/* Broadcom STB PCIe Register Offsets */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
+#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
+
+#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
+
+#define PCIE_RC_DL_MDIO_ADDR 0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
+
+#define PCIE_MISC_MISC_CTRL 0x4008
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
+
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
+#define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
+#define PCIE_MEM_WIN0_LO(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
+#define PCIE_MEM_WIN0_HI(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
+
+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
+
+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
+#define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
+
+#define PCIE_MISC_MSI_DATA_CONFIG 0x404c
+#define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
+#define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
+
+#define PCIE_MISC_PCIE_CTRL 0x4064
+#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
+
+#define PCIE_MISC_PCIE_STATUS 0x4068
+#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
+#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
+#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
+#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
+
+#define PCIE_MISC_REVISION 0x406c
+#define BRCM_PCIE_HW_REV_33 0x0303
+#define BRCM_PCIE_HW_REV_3_20 0x0320
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
+#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
+#define PCIE_MEM_WIN0_BASE_HI(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
+#define PCIE_MEM_WIN0_LIMIT_HI(win) \
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
+
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+
+
+#define PCIE_INTR2_CPU_BASE 0x4300
+#define PCIE_MSI_INTR2_BASE 0x4500
+/* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
+#define MSI_INT_STATUS 0x0
+#define MSI_INT_CLR 0x8
+#define MSI_INT_MASK_SET 0x10
+#define MSI_INT_MASK_CLR 0x14
+
+#define PCIE_EXT_CFG_DATA 0x8000
+#define PCIE_EXT_CFG_INDEX 0x9000
+
+#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
+#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
+
+#define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
+#define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
+#define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
+#define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
+
+/* PCIe parameters */
+#define BRCM_NUM_PCIE_OUT_WINS 0x4
+#define BRCM_INT_PCI_MSI_NR 32
+#define BRCM_INT_PCI_MSI_LEGACY_NR 8
+#define BRCM_INT_PCI_MSI_SHIFT 0
+
+/* MSI target addresses */
+#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
+#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
+
+/* MDIO registers */
+#define MDIO_PORT0 0x0
+#define MDIO_DATA_MASK 0x7fffffff
+#define MDIO_PORT_MASK 0xf0000
+#define MDIO_REGAD_MASK 0xffff
+#define MDIO_CMD_MASK 0xfff00000
+#define MDIO_CMD_READ 0x1
+#define MDIO_CMD_WRITE 0x0
+#define MDIO_DATA_DONE_MASK 0x80000000
+#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
+#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
+#define SSC_REGS_ADDR 0x1100
+#define SET_ADDR_OFFSET 0x1f
+#define SSC_CNTL_OFFSET 0x2
+#define SSC_CNTL_OVRD_EN_MASK 0x8000
+#define SSC_CNTL_OVRD_VAL_MASK 0x4000
+#define SSC_STATUS_OFFSET 0x1
+#define SSC_STATUS_SSC_MASK 0x400
+#define SSC_STATUS_PLL_LOCK_MASK 0x800
+#define PCIE_BRCM_MAX_MEMC 3
+
+/* Rescal registers */
+#define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
+#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
+#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
+#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
+#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
+#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
+#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
+#define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
+
+#endif /* _PCIE_BRCMSTB_H */
--
2.31.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 1/4] PCI: brcmstb: Break register definitions into separate header
2021-08-19 21:56 ` [PATCH v2 1/4] PCI: brcmstb: Break register definitions into separate header Jeremy Linton
@ 2021-08-22 8:49 ` Florian Fainelli
0 siblings, 0 replies; 18+ messages in thread
From: Florian Fainelli @ 2021-08-22 8:49 UTC (permalink / raw)
To: Jeremy Linton, linux-pci
Cc: lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh, kw,
sdonthineni, stefan.wahren, bcm-kernel-feedback-list, linux-acpi,
linux-arm-kernel, linux-rpi-kernel, linux-kernel, Jim Quinlan
On 8/19/2021 11:56 PM, Jeremy Linton wrote:
> We are about to create a standalone ACPI quirk module for the
> bcmstb controller. Lets move the register definitions into a separate
> file so they can be shared between the APCI quirk and the normal
> host bridge driver.
>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk
2021-08-19 21:56 [PATCH v2 0/4] CM4 ACPI PCIe quirk Jeremy Linton
2021-08-19 21:56 ` [PATCH v2 1/4] PCI: brcmstb: Break register definitions into separate header Jeremy Linton
@ 2021-08-19 21:56 ` Jeremy Linton
2021-08-20 19:06 ` Bjorn Helgaas
` (2 more replies)
2021-08-19 21:56 ` [PATCH v2 3/4] PCI/ACPI: Add Broadcom bcm2711 MCFG quirk Jeremy Linton
` (2 subsequent siblings)
4 siblings, 3 replies; 18+ messages in thread
From: Jeremy Linton @ 2021-08-19 21:56 UTC (permalink / raw)
To: linux-pci
Cc: lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh, kw,
f.fainelli, sdonthineni, stefan.wahren, bcm-kernel-feedback-list,
linux-acpi, linux-arm-kernel, linux-rpi-kernel, linux-kernel,
Jeremy Linton
The PFTF CM4 is an ACPI platform that isn't ECAM compliant. Its config
space is in two parts. One part is for the root port registers and a
second moveable window pointing at a device's 4K config space. Thus it
doesn't have an MCFG, and any MCFG provided would be nonsense
anyway. Instead, a Linux specific host bridge _DSD selects a custom
ECAM ops and cfgres. The cfg op picks between those two regions while
disallowing problematic accesses.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pcie-brcmstb-acpi.c | 74 ++++++++++++++++++++++
include/linux/pci-ecam.h | 1 +
3 files changed, 76 insertions(+)
create mode 100644 drivers/pci/controller/pcie-brcmstb-acpi.c
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index aaf30b3dcc14..65aa6fd3ed89 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -57,5 +57,6 @@ ifdef CONFIG_PCI_QUIRKS
obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
obj-$(CONFIG_ARM64) += pci-thunder-pem.o
obj-$(CONFIG_ARM64) += pci-xgene.o
+obj-$(CONFIG_ARM64) += pcie-brcmstb-acpi.o
endif
endif
diff --git a/drivers/pci/controller/pcie-brcmstb-acpi.c b/drivers/pci/controller/pcie-brcmstb-acpi.c
new file mode 100644
index 000000000000..71f6def3074c
--- /dev/null
+++ b/drivers/pci/controller/pcie-brcmstb-acpi.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ACPI quirks for Brcm2711 PCIe host controller
+ * As used on the Raspberry Pi Compute Module 4
+ *
+ * Copyright (C) 2021 Arm Ltd.
+ */
+
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/pci-ecam.h>
+#include "../pci.h"
+#include "pcie-brcmstb.h"
+
+static int brcm_acpi_init(struct pci_config_window *cfg)
+{
+ /*
+ * This platform doesn't technically have anything that could be called
+ * ECAM. Its config region has root port specific registers between
+ * standard PCIe defined config registers. Thus the region setup by the
+ * generic ECAM code needs to be adjusted. The HW can access bus 0-ff
+ * but the footprint isn't a nice power of 2 (40k). For purposes of
+ * mapping the config region we are just going to squash the standard
+ * and nonstandard registers together rather than mapping them separately.
+ */
+ iounmap(cfg->win);
+ cfg->win = pci_remap_cfgspace(cfg->res.start, resource_size(&cfg->res));
+ if (!cfg->win)
+ goto err_exit;
+
+ /* MSI is nonstandard as well */
+ pci_no_msi();
+
+ return 0;
+err_exit:
+ dev_err(cfg->parent, "PCI: Failed to remap config\n");
+ return -ENOMEM;
+}
+
+static void __iomem *brcm_pcie_map_conf2(struct pci_bus *bus,
+ unsigned int devfn, int where)
+{
+ struct pci_config_window *cfg = bus->sysdata;
+ void __iomem *base = cfg->win;
+ int idx;
+ u32 up;
+
+ /* Accesses to the RC go right to the RC registers if slot==0 */
+ if (pci_is_root_bus(bus))
+ return PCI_SLOT(devfn) ? NULL : base + where;
+
+ /* Assure link up before sending request */
+ up = readl(base + PCIE_MISC_PCIE_STATUS);
+ if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK))
+ return NULL;
+
+ if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK))
+ return NULL;
+
+ /* For devices, write to the config space index register */
+ idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
+ writel(idx, base + PCIE_EXT_CFG_INDEX);
+ return base + PCIE_EXT_CFG_DATA + where;
+}
+
+const struct pci_ecam_ops bcm2711_pcie_ops = {
+ .init = brcm_acpi_init,
+ .bus_shift = 1,
+ .pci_ops = {
+ .map_bus = brcm_pcie_map_conf2,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
+ }
+};
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index adea5a4771cf..a5de0285bb7f 100644
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -87,6 +87,7 @@ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 *
extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
+extern const struct pci_ecam_ops bcm2711_pcie_ops; /* Bcm2711 PCIe */
#endif
#if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
--
2.31.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk
2021-08-19 21:56 ` [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk Jeremy Linton
@ 2021-08-20 19:06 ` Bjorn Helgaas
2021-08-20 20:31 ` Jeremy Linton
2021-08-22 8:52 ` Florian Fainelli
2021-08-29 11:13 ` Pali Rohár
2 siblings, 1 reply; 18+ messages in thread
From: Bjorn Helgaas @ 2021-08-20 19:06 UTC (permalink / raw)
To: Jeremy Linton
Cc: linux-pci, lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh,
kw, f.fainelli, sdonthineni, stefan.wahren,
bcm-kernel-feedback-list, linux-acpi, linux-arm-kernel,
linux-rpi-kernel, linux-kernel
On Thu, Aug 19, 2021 at 04:56:53PM -0500, Jeremy Linton wrote:
> The PFTF CM4 is an ACPI platform that isn't ECAM compliant. Its config
> space is in two parts. One part is for the root port registers and a
> second moveable window pointing at a device's 4K config space. Thus it
> doesn't have an MCFG, and any MCFG provided would be nonsense
> anyway. Instead, a Linux specific host bridge _DSD selects a custom
> ECAM ops and cfgres. The cfg op picks between those two regions while
> disallowing problematic accesses.
This doesn't actually say what this patch *does*.
Can you expand "PFTF CM4" somehow? Google (and the comment below, I
guess) suggests it's something to do with Raspberry Pi 4, but it would
be nice if the commit log made sense without Googling or reading the
patch.
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pcie-brcmstb-acpi.c | 74 ++++++++++++++++++++++
> include/linux/pci-ecam.h | 1 +
> 3 files changed, 76 insertions(+)
> create mode 100644 drivers/pci/controller/pcie-brcmstb-acpi.c
>
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index aaf30b3dcc14..65aa6fd3ed89 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -57,5 +57,6 @@ ifdef CONFIG_PCI_QUIRKS
> obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
> obj-$(CONFIG_ARM64) += pci-thunder-pem.o
> obj-$(CONFIG_ARM64) += pci-xgene.o
> +obj-$(CONFIG_ARM64) += pcie-brcmstb-acpi.o
> endif
> endif
> diff --git a/drivers/pci/controller/pcie-brcmstb-acpi.c b/drivers/pci/controller/pcie-brcmstb-acpi.c
> new file mode 100644
> index 000000000000..71f6def3074c
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-brcmstb-acpi.c
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * ACPI quirks for Brcm2711 PCIe host controller
> + * As used on the Raspberry Pi Compute Module 4
> + *
> + * Copyright (C) 2021 Arm Ltd.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/pci.h>
> +#include <linux/pci-ecam.h>
> +#include "../pci.h"
> +#include "pcie-brcmstb.h"
> +
> +static int brcm_acpi_init(struct pci_config_window *cfg)
> +{
> + /*
> + * This platform doesn't technically have anything that could be called
> + * ECAM. Its config region has root port specific registers between
> + * standard PCIe defined config registers. Thus the region setup by the
> + * generic ECAM code needs to be adjusted. The HW can access bus 0-ff
> + * but the footprint isn't a nice power of 2 (40k). For purposes of
> + * mapping the config region we are just going to squash the standard
> + * and nonstandard registers together rather than mapping them separately.
> + */
> + iounmap(cfg->win);
> + cfg->win = pci_remap_cfgspace(cfg->res.start, resource_size(&cfg->res));
> + if (!cfg->win)
> + goto err_exit;
> +
> + /* MSI is nonstandard as well */
> + pci_no_msi();
> +
> + return 0;
> +err_exit:
> + dev_err(cfg->parent, "PCI: Failed to remap config\n");
> + return -ENOMEM;
> +}
> +
> +static void __iomem *brcm_pcie_map_conf2(struct pci_bus *bus,
> + unsigned int devfn, int where)
> +{
> + struct pci_config_window *cfg = bus->sysdata;
> + void __iomem *base = cfg->win;
> + int idx;
> + u32 up;
> +
> + /* Accesses to the RC go right to the RC registers if slot==0 */
> + if (pci_is_root_bus(bus))
> + return PCI_SLOT(devfn) ? NULL : base + where;
> +
> + /* Assure link up before sending request */
Obviously this is horribly racy, since the link may go down after you
check but before you send the request. Maybe the hardware leaves you
no choice. I'd feel a little better about it if the comment
acknowledged that (if it's so) and outlined the consequence of losing
the race (panic, recoverable error, etc).
> + up = readl(base + PCIE_MISC_PCIE_STATUS);
> + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK))
> + return NULL;
> +
> + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK))
> + return NULL;
> +
> + /* For devices, write to the config space index register */
> + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
> + writel(idx, base + PCIE_EXT_CFG_INDEX);
> + return base + PCIE_EXT_CFG_DATA + where;
> +}
> +
> +const struct pci_ecam_ops bcm2711_pcie_ops = {
> + .init = brcm_acpi_init,
> + .bus_shift = 1,
> + .pci_ops = {
> + .map_bus = brcm_pcie_map_conf2,
> + .read = pci_generic_config_read,
> + .write = pci_generic_config_write,
> + }
> +};
> diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
> index adea5a4771cf..a5de0285bb7f 100644
> --- a/include/linux/pci-ecam.h
> +++ b/include/linux/pci-ecam.h
> @@ -87,6 +87,7 @@ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 *
> extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
> extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
> extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
> +extern const struct pci_ecam_ops bcm2711_pcie_ops; /* Bcm2711 PCIe */
> #endif
>
> #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk
2021-08-20 19:06 ` Bjorn Helgaas
@ 2021-08-20 20:31 ` Jeremy Linton
0 siblings, 0 replies; 18+ messages in thread
From: Jeremy Linton @ 2021-08-20 20:31 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh,
kw, f.fainelli, sdonthineni, stefan.wahren,
bcm-kernel-feedback-list, linux-acpi, linux-arm-kernel,
linux-rpi-kernel, linux-kernel
Hi,
Thanks for looking at this.
On 8/20/21 2:06 PM, Bjorn Helgaas wrote:
> On Thu, Aug 19, 2021 at 04:56:53PM -0500, Jeremy Linton wrote:
>> The PFTF CM4 is an ACPI platform that isn't ECAM compliant. Its config
>> space is in two parts. One part is for the root port registers and a
>> second moveable window pointing at a device's 4K config space. Thus it
>> doesn't have an MCFG, and any MCFG provided would be nonsense
>> anyway. Instead, a Linux specific host bridge _DSD selects a custom
>> ECAM ops and cfgres. The cfg op picks between those two regions while
>> disallowing problematic accesses.
>
> This doesn't actually say what this patch *does*.
Ok.
>
> Can you expand "PFTF CM4" somehow? Google (and the comment below, I
> guess) suggests it's something to do with Raspberry Pi 4, but it would
> be nice if the commit log made sense without Googling or reading the
> patch.
Yes, sure, as you deduced PFTF is a community project which aims to
create a systemready UEFI/ACPI platform out of rpi4/rpi400/cm4 systems.
Its actually fairly far along in that goal, and is capable of booting a
wide range of arm64 based OS's & Hypervisors. Its acting like a proof of
concept that putting effort into some basic platform abstractions
reduces the effort to boot off the shelf OSs. It does this by moving
much of the platform specific code into firmware.
>
>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>> ---
>> drivers/pci/controller/Makefile | 1 +
>> drivers/pci/controller/pcie-brcmstb-acpi.c | 74 ++++++++++++++++++++++
>> include/linux/pci-ecam.h | 1 +
>> 3 files changed, 76 insertions(+)
>> create mode 100644 drivers/pci/controller/pcie-brcmstb-acpi.c
>>
>> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
>> index aaf30b3dcc14..65aa6fd3ed89 100644
>> --- a/drivers/pci/controller/Makefile
>> +++ b/drivers/pci/controller/Makefile
>> @@ -57,5 +57,6 @@ ifdef CONFIG_PCI_QUIRKS
>> obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
>> obj-$(CONFIG_ARM64) += pci-thunder-pem.o
>> obj-$(CONFIG_ARM64) += pci-xgene.o
>> +obj-$(CONFIG_ARM64) += pcie-brcmstb-acpi.o
>> endif
>> endif
>> diff --git a/drivers/pci/controller/pcie-brcmstb-acpi.c b/drivers/pci/controller/pcie-brcmstb-acpi.c
>> new file mode 100644
>> index 000000000000..71f6def3074c
>> --- /dev/null
>> +++ b/drivers/pci/controller/pcie-brcmstb-acpi.c
>> @@ -0,0 +1,74 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * ACPI quirks for Brcm2711 PCIe host controller
>> + * As used on the Raspberry Pi Compute Module 4
>> + *
>> + * Copyright (C) 2021 Arm Ltd.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/pci.h>
>> +#include <linux/pci-ecam.h>
>> +#include "../pci.h"
>> +#include "pcie-brcmstb.h"
>> +
>> +static int brcm_acpi_init(struct pci_config_window *cfg)
>> +{
>> + /*
>> + * This platform doesn't technically have anything that could be called
>> + * ECAM. Its config region has root port specific registers between
>> + * standard PCIe defined config registers. Thus the region setup by the
>> + * generic ECAM code needs to be adjusted. The HW can access bus 0-ff
>> + * but the footprint isn't a nice power of 2 (40k). For purposes of
>> + * mapping the config region we are just going to squash the standard
>> + * and nonstandard registers together rather than mapping them separately.
>> + */
>> + iounmap(cfg->win);
>> + cfg->win = pci_remap_cfgspace(cfg->res.start, resource_size(&cfg->res));
>> + if (!cfg->win)
>> + goto err_exit;
>> +
>> + /* MSI is nonstandard as well */
>> + pci_no_msi();
>> +
>> + return 0;
>> +err_exit:
>> + dev_err(cfg->parent, "PCI: Failed to remap config\n");
>> + return -ENOMEM;
>> +}
>> +
>> +static void __iomem *brcm_pcie_map_conf2(struct pci_bus *bus,
>> + unsigned int devfn, int where)
>> +{
>> + struct pci_config_window *cfg = bus->sysdata;
>> + void __iomem *base = cfg->win;
>> + int idx;
>> + u32 up;
>> +
>> + /* Accesses to the RC go right to the RC registers if slot==0 */
>> + if (pci_is_root_bus(bus))
>> + return PCI_SLOT(devfn) ? NULL : base + where;
>> +
>> + /* Assure link up before sending request */
>
> Obviously this is horribly racy, since the link may go down after you
> check but before you send the request. Maybe the hardware leaves you
> no choice. I'd feel a little better about it if the comment
> acknowledged that (if it's so) and outlined the consequence of losing
> the race (panic, recoverable error, etc).
Sure, that gets at what appears to be the fundamental problem with this
bridge, mainly that the HW doesn't appear to be able to handle missing
config TLP completions in a way that can be recovered.
So, if one loses the race here (and the window is much larger in the DT
config accessor) the machine takes what is basically an unrecoverable
exception. I will update the comment to that effect.
>
>> + up = readl(base + PCIE_MISC_PCIE_STATUS);
>> + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK))
>> + return NULL;
>> +
>> + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK))
>> + return NULL;
>> +
>> + /* For devices, write to the config space index register */
>> + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
>> + writel(idx, base + PCIE_EXT_CFG_INDEX);
>> + return base + PCIE_EXT_CFG_DATA + where;
>> +}
>> +
>> +const struct pci_ecam_ops bcm2711_pcie_ops = {
>> + .init = brcm_acpi_init,
>> + .bus_shift = 1,
>> + .pci_ops = {
>> + .map_bus = brcm_pcie_map_conf2,
>> + .read = pci_generic_config_read,
>> + .write = pci_generic_config_write,
>> + }
>> +};
>> diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
>> index adea5a4771cf..a5de0285bb7f 100644
>> --- a/include/linux/pci-ecam.h
>> +++ b/include/linux/pci-ecam.h
>> @@ -87,6 +87,7 @@ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 *
>> extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
>> extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
>> extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
>> +extern const struct pci_ecam_ops bcm2711_pcie_ops; /* Bcm2711 PCIe */
>> #endif
>>
>> #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
>> --
>> 2.31.1
>>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk
2021-08-19 21:56 ` [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk Jeremy Linton
2021-08-20 19:06 ` Bjorn Helgaas
@ 2021-08-22 8:52 ` Florian Fainelli
2021-08-29 11:13 ` Pali Rohár
2 siblings, 0 replies; 18+ messages in thread
From: Florian Fainelli @ 2021-08-22 8:52 UTC (permalink / raw)
To: Jeremy Linton, linux-pci
Cc: lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh, kw,
sdonthineni, stefan.wahren, bcm-kernel-feedback-list, linux-acpi,
linux-arm-kernel, linux-rpi-kernel, linux-kernel
On 8/19/2021 11:56 PM, Jeremy Linton wrote:
> The PFTF CM4 is an ACPI platform that isn't ECAM compliant. Its config
> space is in two parts. One part is for the root port registers and a
> second moveable window pointing at a device's 4K config space. Thus it
> doesn't have an MCFG, and any MCFG provided would be nonsense
> anyway. Instead, a Linux specific host bridge _DSD selects a custom
> ECAM ops and cfgres. The cfg op picks between those two regions while
> disallowing problematic accesses.
>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Once you address Bjorn's feedback, feel free to add:
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
I do wonder if squashing patches 2 and 3 would make more sense,
otherwise we have a bcm2711_pcie_ops that is unused in patch 2.
--
Florian
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk
2021-08-19 21:56 ` [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk Jeremy Linton
2021-08-20 19:06 ` Bjorn Helgaas
2021-08-22 8:52 ` Florian Fainelli
@ 2021-08-29 11:13 ` Pali Rohár
2021-08-30 16:10 ` Jeremy Linton
2 siblings, 1 reply; 18+ messages in thread
From: Pali Rohár @ 2021-08-29 11:13 UTC (permalink / raw)
To: lorenzo.pieralisi
Cc: Jeremy Linton, linux-pci, nsaenz, bhelgaas, rjw, lenb, robh, kw,
f.fainelli, sdonthineni, stefan.wahren, bcm-kernel-feedback-list,
linux-acpi, linux-arm-kernel, linux-rpi-kernel, linux-kernel
On Thursday 19 August 2021 16:56:53 Jeremy Linton wrote:
> The PFTF CM4 is an ACPI platform that isn't ECAM compliant. Its config
> space is in two parts. One part is for the root port registers and a
> second moveable window pointing at a device's 4K config space. Thus it
> doesn't have an MCFG, and any MCFG provided would be nonsense
> anyway. Instead, a Linux specific host bridge _DSD selects a custom
> ECAM ops and cfgres. The cfg op picks between those two regions while
> disallowing problematic accesses.
I'm not sure if Lorenzo would like this patch series...
In past there was a long discussion about ECAM compliance, MCFG quirks
and usage of ACPI (on other platform), see long thread:
https://lore.kernel.org/linux-pci/20200207183427.GA40158@google.com/
And I think it is not a good idea to extend MCFG quirks table as
according to discussion it was just temporary plaster and if platform is
not ACPI / ECAM compliant then it should use DT booting...
Lorenzo, could you put any comment on this?
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pcie-brcmstb-acpi.c | 74 ++++++++++++++++++++++
> include/linux/pci-ecam.h | 1 +
> 3 files changed, 76 insertions(+)
> create mode 100644 drivers/pci/controller/pcie-brcmstb-acpi.c
>
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index aaf30b3dcc14..65aa6fd3ed89 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -57,5 +57,6 @@ ifdef CONFIG_PCI_QUIRKS
> obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
> obj-$(CONFIG_ARM64) += pci-thunder-pem.o
> obj-$(CONFIG_ARM64) += pci-xgene.o
> +obj-$(CONFIG_ARM64) += pcie-brcmstb-acpi.o
> endif
> endif
> diff --git a/drivers/pci/controller/pcie-brcmstb-acpi.c b/drivers/pci/controller/pcie-brcmstb-acpi.c
> new file mode 100644
> index 000000000000..71f6def3074c
> --- /dev/null
> +++ b/drivers/pci/controller/pcie-brcmstb-acpi.c
> @@ -0,0 +1,74 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * ACPI quirks for Brcm2711 PCIe host controller
> + * As used on the Raspberry Pi Compute Module 4
> + *
> + * Copyright (C) 2021 Arm Ltd.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/pci.h>
> +#include <linux/pci-ecam.h>
> +#include "../pci.h"
> +#include "pcie-brcmstb.h"
> +
> +static int brcm_acpi_init(struct pci_config_window *cfg)
> +{
> + /*
> + * This platform doesn't technically have anything that could be called
> + * ECAM. Its config region has root port specific registers between
> + * standard PCIe defined config registers. Thus the region setup by the
> + * generic ECAM code needs to be adjusted. The HW can access bus 0-ff
> + * but the footprint isn't a nice power of 2 (40k). For purposes of
> + * mapping the config region we are just going to squash the standard
> + * and nonstandard registers together rather than mapping them separately.
> + */
> + iounmap(cfg->win);
> + cfg->win = pci_remap_cfgspace(cfg->res.start, resource_size(&cfg->res));
> + if (!cfg->win)
> + goto err_exit;
> +
> + /* MSI is nonstandard as well */
> + pci_no_msi();
> +
> + return 0;
> +err_exit:
> + dev_err(cfg->parent, "PCI: Failed to remap config\n");
> + return -ENOMEM;
> +}
> +
> +static void __iomem *brcm_pcie_map_conf2(struct pci_bus *bus,
> + unsigned int devfn, int where)
> +{
> + struct pci_config_window *cfg = bus->sysdata;
> + void __iomem *base = cfg->win;
> + int idx;
> + u32 up;
> +
> + /* Accesses to the RC go right to the RC registers if slot==0 */
> + if (pci_is_root_bus(bus))
> + return PCI_SLOT(devfn) ? NULL : base + where;
> +
> + /* Assure link up before sending request */
> + up = readl(base + PCIE_MISC_PCIE_STATUS);
> + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK))
> + return NULL;
> +
> + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK))
> + return NULL;
> +
> + /* For devices, write to the config space index register */
> + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
> + writel(idx, base + PCIE_EXT_CFG_INDEX);
> + return base + PCIE_EXT_CFG_DATA + where;
> +}
> +
> +const struct pci_ecam_ops bcm2711_pcie_ops = {
> + .init = brcm_acpi_init,
> + .bus_shift = 1,
> + .pci_ops = {
> + .map_bus = brcm_pcie_map_conf2,
> + .read = pci_generic_config_read,
> + .write = pci_generic_config_write,
> + }
> +};
> diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
> index adea5a4771cf..a5de0285bb7f 100644
> --- a/include/linux/pci-ecam.h
> +++ b/include/linux/pci-ecam.h
> @@ -87,6 +87,7 @@ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 *
> extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
> extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
> extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
> +extern const struct pci_ecam_ops bcm2711_pcie_ops; /* Bcm2711 PCIe */
> #endif
>
> #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk
2021-08-29 11:13 ` Pali Rohár
@ 2021-08-30 16:10 ` Jeremy Linton
2021-08-30 16:54 ` Pali Rohár
0 siblings, 1 reply; 18+ messages in thread
From: Jeremy Linton @ 2021-08-30 16:10 UTC (permalink / raw)
To: Pali Rohár, lorenzo.pieralisi
Cc: linux-pci, nsaenz, bhelgaas, rjw, lenb, robh, kw, f.fainelli,
sdonthineni, stefan.wahren, bcm-kernel-feedback-list, linux-acpi,
linux-arm-kernel, linux-rpi-kernel, linux-kernel
Hi,
On 8/29/21 6:13 AM, Pali Rohár wrote:
> On Thursday 19 August 2021 16:56:53 Jeremy Linton wrote:
>> The PFTF CM4 is an ACPI platform that isn't ECAM compliant. Its config
>> space is in two parts. One part is for the root port registers and a
>> second moveable window pointing at a device's 4K config space. Thus it
>> doesn't have an MCFG, and any MCFG provided would be nonsense
>> anyway. Instead, a Linux specific host bridge _DSD selects a custom
>> ECAM ops and cfgres. The cfg op picks between those two regions while
>> disallowing problematic accesses.
>
> I'm not sure if Lorenzo would like this patch series...
That was sorta true since the arm64/ACPI/PCI patches landed. The
underlying reason is the desire for arm platforms to require less
one-off kernel patching in order to "just work". But, its become
apparent that there continue to be problems with PCIe IP and Arm
interconnect integration. So, a firmware interface was standardized
which solves most of the nonstandard ECAM issues. At that point it was
decided though that the kernel maintainers would prefer to have the
quirks visible to the kernel rather than hidden in the firmware, and
that they would be more open to merging these quirks. The Tegra patch
you listed above has been merged.
More info about this: https://lkml.org/lkml/2021/3/25/777
Thanks,
>
> In past there was a long discussion about ECAM compliance, MCFG quirks
> and usage of ACPI (on other platform), see long thread:
> https://lore.kernel.org/linux-pci/20200207183427.GA40158@google.com/
>
> And I think it is not a good idea to extend MCFG quirks table as
> according to discussion it was just temporary plaster and if platform is
> not ACPI / ECAM compliant then it should use DT booting...
>
> Lorenzo, could you put any comment on this?
>
>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>> ---
>> drivers/pci/controller/Makefile | 1 +
>> drivers/pci/controller/pcie-brcmstb-acpi.c | 74 ++++++++++++++++++++++
>> include/linux/pci-ecam.h | 1 +
>> 3 files changed, 76 insertions(+)
>> create mode 100644 drivers/pci/controller/pcie-brcmstb-acpi.c
>>
>> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
>> index aaf30b3dcc14..65aa6fd3ed89 100644
>> --- a/drivers/pci/controller/Makefile
>> +++ b/drivers/pci/controller/Makefile
>> @@ -57,5 +57,6 @@ ifdef CONFIG_PCI_QUIRKS
>> obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
>> obj-$(CONFIG_ARM64) += pci-thunder-pem.o
>> obj-$(CONFIG_ARM64) += pci-xgene.o
>> +obj-$(CONFIG_ARM64) += pcie-brcmstb-acpi.o
>> endif
>> endif
>> diff --git a/drivers/pci/controller/pcie-brcmstb-acpi.c b/drivers/pci/controller/pcie-brcmstb-acpi.c
>> new file mode 100644
>> index 000000000000..71f6def3074c
>> --- /dev/null
>> +++ b/drivers/pci/controller/pcie-brcmstb-acpi.c
>> @@ -0,0 +1,74 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * ACPI quirks for Brcm2711 PCIe host controller
>> + * As used on the Raspberry Pi Compute Module 4
>> + *
>> + * Copyright (C) 2021 Arm Ltd.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/pci.h>
>> +#include <linux/pci-ecam.h>
>> +#include "../pci.h"
>> +#include "pcie-brcmstb.h"
>> +
>> +static int brcm_acpi_init(struct pci_config_window *cfg)
>> +{
>> + /*
>> + * This platform doesn't technically have anything that could be called
>> + * ECAM. Its config region has root port specific registers between
>> + * standard PCIe defined config registers. Thus the region setup by the
>> + * generic ECAM code needs to be adjusted. The HW can access bus 0-ff
>> + * but the footprint isn't a nice power of 2 (40k). For purposes of
>> + * mapping the config region we are just going to squash the standard
>> + * and nonstandard registers together rather than mapping them separately.
>> + */
>> + iounmap(cfg->win);
>> + cfg->win = pci_remap_cfgspace(cfg->res.start, resource_size(&cfg->res));
>> + if (!cfg->win)
>> + goto err_exit;
>> +
>> + /* MSI is nonstandard as well */
>> + pci_no_msi();
>> +
>> + return 0;
>> +err_exit:
>> + dev_err(cfg->parent, "PCI: Failed to remap config\n");
>> + return -ENOMEM;
>> +}
>> +
>> +static void __iomem *brcm_pcie_map_conf2(struct pci_bus *bus,
>> + unsigned int devfn, int where)
>> +{
>> + struct pci_config_window *cfg = bus->sysdata;
>> + void __iomem *base = cfg->win;
>> + int idx;
>> + u32 up;
>> +
>> + /* Accesses to the RC go right to the RC registers if slot==0 */
>> + if (pci_is_root_bus(bus))
>> + return PCI_SLOT(devfn) ? NULL : base + where;
>> +
>> + /* Assure link up before sending request */
>> + up = readl(base + PCIE_MISC_PCIE_STATUS);
>> + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK))
>> + return NULL;
>> +
>> + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK))
>> + return NULL;
>> +
>> + /* For devices, write to the config space index register */
>> + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
>> + writel(idx, base + PCIE_EXT_CFG_INDEX);
>> + return base + PCIE_EXT_CFG_DATA + where;
>> +}
>> +
>> +const struct pci_ecam_ops bcm2711_pcie_ops = {
>> + .init = brcm_acpi_init,
>> + .bus_shift = 1,
>> + .pci_ops = {
>> + .map_bus = brcm_pcie_map_conf2,
>> + .read = pci_generic_config_read,
>> + .write = pci_generic_config_write,
>> + }
>> +};
>> diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
>> index adea5a4771cf..a5de0285bb7f 100644
>> --- a/include/linux/pci-ecam.h
>> +++ b/include/linux/pci-ecam.h
>> @@ -87,6 +87,7 @@ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 *
>> extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
>> extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
>> extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
>> +extern const struct pci_ecam_ops bcm2711_pcie_ops; /* Bcm2711 PCIe */
>> #endif
>>
>> #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
>> --
>> 2.31.1
>>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk
2021-08-30 16:10 ` Jeremy Linton
@ 2021-08-30 16:54 ` Pali Rohár
0 siblings, 0 replies; 18+ messages in thread
From: Pali Rohár @ 2021-08-30 16:54 UTC (permalink / raw)
To: Jeremy Linton
Cc: lorenzo.pieralisi, linux-pci, nsaenz, bhelgaas, rjw, lenb, robh,
kw, f.fainelli, sdonthineni, stefan.wahren,
bcm-kernel-feedback-list, linux-acpi, linux-arm-kernel,
linux-rpi-kernel, linux-kernel
On Monday 30 August 2021 11:10:55 Jeremy Linton wrote:
> Hi,
>
> On 8/29/21 6:13 AM, Pali Rohár wrote:
> > On Thursday 19 August 2021 16:56:53 Jeremy Linton wrote:
> > > The PFTF CM4 is an ACPI platform that isn't ECAM compliant. Its config
> > > space is in two parts. One part is for the root port registers and a
> > > second moveable window pointing at a device's 4K config space. Thus it
> > > doesn't have an MCFG, and any MCFG provided would be nonsense
> > > anyway. Instead, a Linux specific host bridge _DSD selects a custom
> > > ECAM ops and cfgres. The cfg op picks between those two regions while
> > > disallowing problematic accesses.
> >
> > I'm not sure if Lorenzo would like this patch series...
>
> That was sorta true since the arm64/ACPI/PCI patches landed. The underlying
> reason is the desire for arm platforms to require less one-off kernel
> patching in order to "just work". But, its become apparent that there
> continue to be problems with PCIe IP and Arm interconnect integration. So, a
> firmware interface was standardized which solves most of the nonstandard
> ECAM issues. At that point it was decided though that the kernel maintainers
> would prefer to have the quirks visible to the kernel rather than hidden in
> the firmware, and that they would be more open to merging these quirks. The
> Tegra patch you listed above has been merged.
>
> More info about this: https://lkml.org/lkml/2021/3/25/777
Hi and thanks for pointer!
I did not know about that new discussion and a new solution.
Anyway, according to that discussion, adding a new MCFG quirk into
kernel requires adding some errata entry for documenting buggy HW. And
seems that this documentation update is not included in this patch
series...
>
> Thanks,
>
> >
> > In past there was a long discussion about ECAM compliance, MCFG quirks
> > and usage of ACPI (on other platform), see long thread:
> > https://lore.kernel.org/linux-pci/20200207183427.GA40158@google.com/
> >
> > And I think it is not a good idea to extend MCFG quirks table as
> > according to discussion it was just temporary plaster and if platform is
> > not ACPI / ECAM compliant then it should use DT booting...
> >
> > Lorenzo, could you put any comment on this?
> >
> > > Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> > > ---
> > > drivers/pci/controller/Makefile | 1 +
> > > drivers/pci/controller/pcie-brcmstb-acpi.c | 74 ++++++++++++++++++++++
> > > include/linux/pci-ecam.h | 1 +
> > > 3 files changed, 76 insertions(+)
> > > create mode 100644 drivers/pci/controller/pcie-brcmstb-acpi.c
> > >
> > > diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> > > index aaf30b3dcc14..65aa6fd3ed89 100644
> > > --- a/drivers/pci/controller/Makefile
> > > +++ b/drivers/pci/controller/Makefile
> > > @@ -57,5 +57,6 @@ ifdef CONFIG_PCI_QUIRKS
> > > obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
> > > obj-$(CONFIG_ARM64) += pci-thunder-pem.o
> > > obj-$(CONFIG_ARM64) += pci-xgene.o
> > > +obj-$(CONFIG_ARM64) += pcie-brcmstb-acpi.o
> > > endif
> > > endif
> > > diff --git a/drivers/pci/controller/pcie-brcmstb-acpi.c b/drivers/pci/controller/pcie-brcmstb-acpi.c
> > > new file mode 100644
> > > index 000000000000..71f6def3074c
> > > --- /dev/null
> > > +++ b/drivers/pci/controller/pcie-brcmstb-acpi.c
> > > @@ -0,0 +1,74 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * ACPI quirks for Brcm2711 PCIe host controller
> > > + * As used on the Raspberry Pi Compute Module 4
> > > + *
> > > + * Copyright (C) 2021 Arm Ltd.
> > > + */
> > > +
> > > +#include <linux/io.h>
> > > +#include <linux/pci.h>
> > > +#include <linux/pci-ecam.h>
> > > +#include "../pci.h"
> > > +#include "pcie-brcmstb.h"
> > > +
> > > +static int brcm_acpi_init(struct pci_config_window *cfg)
> > > +{
> > > + /*
> > > + * This platform doesn't technically have anything that could be called
> > > + * ECAM. Its config region has root port specific registers between
> > > + * standard PCIe defined config registers. Thus the region setup by the
> > > + * generic ECAM code needs to be adjusted. The HW can access bus 0-ff
> > > + * but the footprint isn't a nice power of 2 (40k). For purposes of
> > > + * mapping the config region we are just going to squash the standard
> > > + * and nonstandard registers together rather than mapping them separately.
> > > + */
> > > + iounmap(cfg->win);
> > > + cfg->win = pci_remap_cfgspace(cfg->res.start, resource_size(&cfg->res));
> > > + if (!cfg->win)
> > > + goto err_exit;
> > > +
> > > + /* MSI is nonstandard as well */
> > > + pci_no_msi();
> > > +
> > > + return 0;
> > > +err_exit:
> > > + dev_err(cfg->parent, "PCI: Failed to remap config\n");
> > > + return -ENOMEM;
> > > +}
> > > +
> > > +static void __iomem *brcm_pcie_map_conf2(struct pci_bus *bus,
> > > + unsigned int devfn, int where)
> > > +{
> > > + struct pci_config_window *cfg = bus->sysdata;
> > > + void __iomem *base = cfg->win;
> > > + int idx;
> > > + u32 up;
> > > +
> > > + /* Accesses to the RC go right to the RC registers if slot==0 */
> > > + if (pci_is_root_bus(bus))
> > > + return PCI_SLOT(devfn) ? NULL : base + where;
> > > +
> > > + /* Assure link up before sending request */
> > > + up = readl(base + PCIE_MISC_PCIE_STATUS);
> > > + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK))
> > > + return NULL;
> > > +
> > > + if (!(up & PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK))
> > > + return NULL;
> > > +
> > > + /* For devices, write to the config space index register */
> > > + idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
> > > + writel(idx, base + PCIE_EXT_CFG_INDEX);
> > > + return base + PCIE_EXT_CFG_DATA + where;
> > > +}
> > > +
> > > +const struct pci_ecam_ops bcm2711_pcie_ops = {
> > > + .init = brcm_acpi_init,
> > > + .bus_shift = 1,
> > > + .pci_ops = {
> > > + .map_bus = brcm_pcie_map_conf2,
> > > + .read = pci_generic_config_read,
> > > + .write = pci_generic_config_write,
> > > + }
> > > +};
> > > diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
> > > index adea5a4771cf..a5de0285bb7f 100644
> > > --- a/include/linux/pci-ecam.h
> > > +++ b/include/linux/pci-ecam.h
> > > @@ -87,6 +87,7 @@ extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 *
> > > extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
> > > extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
> > > extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
> > > +extern const struct pci_ecam_ops bcm2711_pcie_ops; /* Bcm2711 PCIe */
> > > #endif
> > > #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
> > > --
> > > 2.31.1
> > >
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 3/4] PCI/ACPI: Add Broadcom bcm2711 MCFG quirk
2021-08-19 21:56 [PATCH v2 0/4] CM4 ACPI PCIe quirk Jeremy Linton
2021-08-19 21:56 ` [PATCH v2 1/4] PCI: brcmstb: Break register definitions into separate header Jeremy Linton
2021-08-19 21:56 ` [PATCH v2 2/4] PCI: brcmstb: Add ACPI config space quirk Jeremy Linton
@ 2021-08-19 21:56 ` Jeremy Linton
2021-08-22 8:53 ` Florian Fainelli
2021-08-19 21:56 ` [PATCH v2 4/4] MAINTAINERS: Widen brcmstb PCIe file scope Jeremy Linton
2021-08-20 19:11 ` [PATCH v2 0/4] CM4 ACPI PCIe quirk Bjorn Helgaas
4 siblings, 1 reply; 18+ messages in thread
From: Jeremy Linton @ 2021-08-19 21:56 UTC (permalink / raw)
To: linux-pci
Cc: lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh, kw,
f.fainelli, sdonthineni, stefan.wahren, bcm-kernel-feedback-list,
linux-acpi, linux-arm-kernel, linux-rpi-kernel, linux-kernel,
Jeremy Linton
Now that there is a bcm2711 quirk, it needs to be enabled when the
MCFG is missing. Use an ACPI namespace _DSD property
"linux-ecam-quirk-id" as an alternative to the MCFG OEM.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
drivers/acpi/pci_mcfg.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index 53cab975f612..4b991ee5c66c 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -169,6 +169,9 @@ static struct mcfg_fixup mcfg_quirks[] = {
ALTRA_ECAM_QUIRK(1, 13),
ALTRA_ECAM_QUIRK(1, 14),
ALTRA_ECAM_QUIRK(1, 15),
+
+ { "bcm2711", "", 0, 0, MCFG_BUS_ANY, &bcm2711_pcie_ops,
+ DEFINE_RES_MEM(0xFD500000, 0xA000) },
};
static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
@@ -198,8 +201,18 @@ static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
u16 segment = root->segment;
struct resource *bus_range = &root->secondary;
struct mcfg_fixup *f;
+ const char *soc;
int i;
+ /*
+ * This may be a machine with a PCI/SMC conduit, which means it doesn't
+ * have an MCFG. Use an ACPI namespace definition instead.
+ */
+ if (!fwnode_property_read_string(acpi_fwnode_handle(root->device),
+ "linux-ecam-quirk-id", &soc)) {
+ memcpy(mcfg_oem_id, soc, ACPI_OEM_ID_SIZE);
+ }
+
for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
if (f->cfgres.start)
--
2.31.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 3/4] PCI/ACPI: Add Broadcom bcm2711 MCFG quirk
2021-08-19 21:56 ` [PATCH v2 3/4] PCI/ACPI: Add Broadcom bcm2711 MCFG quirk Jeremy Linton
@ 2021-08-22 8:53 ` Florian Fainelli
2021-08-24 21:39 ` Jeremy Linton
0 siblings, 1 reply; 18+ messages in thread
From: Florian Fainelli @ 2021-08-22 8:53 UTC (permalink / raw)
To: Jeremy Linton, linux-pci
Cc: lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh, kw,
sdonthineni, stefan.wahren, bcm-kernel-feedback-list, linux-acpi,
linux-arm-kernel, linux-rpi-kernel, linux-kernel
On 8/19/2021 11:56 PM, Jeremy Linton wrote:
> Now that there is a bcm2711 quirk, it needs to be enabled when the
> MCFG is missing. Use an ACPI namespace _DSD property
> "linux-ecam-quirk-id" as an alternative to the MCFG OEM.
>
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> drivers/acpi/pci_mcfg.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
> index 53cab975f612..4b991ee5c66c 100644
> --- a/drivers/acpi/pci_mcfg.c
> +++ b/drivers/acpi/pci_mcfg.c
> @@ -169,6 +169,9 @@ static struct mcfg_fixup mcfg_quirks[] = {
> ALTRA_ECAM_QUIRK(1, 13),
> ALTRA_ECAM_QUIRK(1, 14),
> ALTRA_ECAM_QUIRK(1, 15),
> +
> + { "bcm2711", "", 0, 0, MCFG_BUS_ANY, &bcm2711_pcie_ops,
> + DEFINE_RES_MEM(0xFD500000, 0xA000) },
> };
>
> static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
> @@ -198,8 +201,18 @@ static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
> u16 segment = root->segment;
> struct resource *bus_range = &root->secondary;
> struct mcfg_fixup *f;
> + const char *soc;
> int i;
>
> + /*
> + * This may be a machine with a PCI/SMC conduit, which means it doesn't
> + * have an MCFG. Use an ACPI namespace definition instead.
> + */
> + if (!fwnode_property_read_string(acpi_fwnode_handle(root->device),
> + "linux-ecam-quirk-id", &soc)) {
> + memcpy(mcfg_oem_id, soc, ACPI_OEM_ID_SIZE);
Being super paranoid here, can we use one of the "safe" string copy
routines here just in case?
> + }
> +
> for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
> if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
> if (f->cfgres.start)
>
--
Florian
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 3/4] PCI/ACPI: Add Broadcom bcm2711 MCFG quirk
2021-08-22 8:53 ` Florian Fainelli
@ 2021-08-24 21:39 ` Jeremy Linton
2021-08-25 16:23 ` Florian Fainelli
0 siblings, 1 reply; 18+ messages in thread
From: Jeremy Linton @ 2021-08-24 21:39 UTC (permalink / raw)
To: Florian Fainelli, linux-pci
Cc: lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh, kw,
sdonthineni, stefan.wahren, bcm-kernel-feedback-list, linux-acpi,
linux-arm-kernel, linux-rpi-kernel, linux-kernel
Hi,
On 8/22/21 3:53 AM, Florian Fainelli wrote:
>
>
> On 8/19/2021 11:56 PM, Jeremy Linton wrote:
>> Now that there is a bcm2711 quirk, it needs to be enabled when the
>> MCFG is missing. Use an ACPI namespace _DSD property
>> "linux-ecam-quirk-id" as an alternative to the MCFG OEM.
>>
>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>> ---
>> drivers/acpi/pci_mcfg.c | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>>
>> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
>> index 53cab975f612..4b991ee5c66c 100644
>> --- a/drivers/acpi/pci_mcfg.c
>> +++ b/drivers/acpi/pci_mcfg.c
>> @@ -169,6 +169,9 @@ static struct mcfg_fixup mcfg_quirks[] = {
>> ALTRA_ECAM_QUIRK(1, 13),
>> ALTRA_ECAM_QUIRK(1, 14),
>> ALTRA_ECAM_QUIRK(1, 15),
>> +
>> + { "bcm2711", "", 0, 0, MCFG_BUS_ANY, &bcm2711_pcie_ops,
>> + DEFINE_RES_MEM(0xFD500000, 0xA000) },
>> };
>> static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
>> @@ -198,8 +201,18 @@ static void pci_mcfg_apply_quirks(struct
>> acpi_pci_root *root,
>> u16 segment = root->segment;
>> struct resource *bus_range = &root->secondary;
>> struct mcfg_fixup *f;
>> + const char *soc;
>> int i;
>> + /*
>> + * This may be a machine with a PCI/SMC conduit, which means it
>> doesn't
>> + * have an MCFG. Use an ACPI namespace definition instead.
>> + */
>> + if (!fwnode_property_read_string(acpi_fwnode_handle(root->device),
>> + "linux-ecam-quirk-id", &soc)) {
>> + memcpy(mcfg_oem_id, soc, ACPI_OEM_ID_SIZE);
>
> Being super paranoid here, can we use one of the "safe" string copy
> routines here just in case?
Hmm, I went around with this a bit when I first wrote it, because the
OEM fields in the ACPI tables are fixed len and don't have null
termination. Maybe the right thing to do here is verify the string size
is at least as long as the OEM_ID_SIZE and then continue to use the memcpy.
>
>> + }
>> +
>> for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++,
>> f++) {
>> if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
>> if (f->cfgres.start)
>>
>
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [PATCH v2 3/4] PCI/ACPI: Add Broadcom bcm2711 MCFG quirk
2021-08-24 21:39 ` Jeremy Linton
@ 2021-08-25 16:23 ` Florian Fainelli
0 siblings, 0 replies; 18+ messages in thread
From: Florian Fainelli @ 2021-08-25 16:23 UTC (permalink / raw)
To: Jeremy Linton, linux-pci
Cc: lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh, kw,
sdonthineni, stefan.wahren, bcm-kernel-feedback-list, linux-acpi,
linux-arm-kernel, linux-rpi-kernel, linux-kernel
On 8/24/2021 11:39 PM, Jeremy Linton wrote:
> Hi,
>
> On 8/22/21 3:53 AM, Florian Fainelli wrote:
>>
>>
>> On 8/19/2021 11:56 PM, Jeremy Linton wrote:
>>> Now that there is a bcm2711 quirk, it needs to be enabled when the
>>> MCFG is missing. Use an ACPI namespace _DSD property
>>> "linux-ecam-quirk-id" as an alternative to the MCFG OEM.
>>>
>>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>>> ---
>>> drivers/acpi/pci_mcfg.c | 13 +++++++++++++
>>> 1 file changed, 13 insertions(+)
>>>
>>> diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
>>> index 53cab975f612..4b991ee5c66c 100644
>>> --- a/drivers/acpi/pci_mcfg.c
>>> +++ b/drivers/acpi/pci_mcfg.c
>>> @@ -169,6 +169,9 @@ static struct mcfg_fixup mcfg_quirks[] = {
>>> ALTRA_ECAM_QUIRK(1, 13),
>>> ALTRA_ECAM_QUIRK(1, 14),
>>> ALTRA_ECAM_QUIRK(1, 15),
>>> +
>>> + { "bcm2711", "", 0, 0, MCFG_BUS_ANY, &bcm2711_pcie_ops,
>>> + DEFINE_RES_MEM(0xFD500000, 0xA000) },
>>> };
>>> static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
>>> @@ -198,8 +201,18 @@ static void pci_mcfg_apply_quirks(struct
>>> acpi_pci_root *root,
>>> u16 segment = root->segment;
>>> struct resource *bus_range = &root->secondary;
>>> struct mcfg_fixup *f;
>>> + const char *soc;
>>> int i;
>>> + /*
>>> + * This may be a machine with a PCI/SMC conduit, which means it
>>> doesn't
>>> + * have an MCFG. Use an ACPI namespace definition instead.
>>> + */
>>> + if (!fwnode_property_read_string(acpi_fwnode_handle(root->device),
>>> + "linux-ecam-quirk-id", &soc)) {
>>> + memcpy(mcfg_oem_id, soc, ACPI_OEM_ID_SIZE);
>>
>> Being super paranoid here, can we use one of the "safe" string copy
>> routines here just in case?
>
> Hmm, I went around with this a bit when I first wrote it, because the
> OEM fields in the ACPI tables are fixed len and don't have null
> termination. Maybe the right thing to do here is verify the string size
> is at least as long as the OEM_ID_SIZE and then continue to use the memcpy.
Sure, sounds entirely reasonable to me.
--
Florian
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2 4/4] MAINTAINERS: Widen brcmstb PCIe file scope
2021-08-19 21:56 [PATCH v2 0/4] CM4 ACPI PCIe quirk Jeremy Linton
` (2 preceding siblings ...)
2021-08-19 21:56 ` [PATCH v2 3/4] PCI/ACPI: Add Broadcom bcm2711 MCFG quirk Jeremy Linton
@ 2021-08-19 21:56 ` Jeremy Linton
2021-08-20 19:09 ` Bjorn Helgaas
2021-08-20 19:11 ` [PATCH v2 0/4] CM4 ACPI PCIe quirk Bjorn Helgaas
4 siblings, 1 reply; 18+ messages in thread
From: Jeremy Linton @ 2021-08-19 21:56 UTC (permalink / raw)
To: linux-pci
Cc: lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh, kw,
f.fainelli, sdonthineni, stefan.wahren, bcm-kernel-feedback-list,
linux-acpi, linux-arm-kernel, linux-rpi-kernel, linux-kernel,
Jeremy Linton
The brcmstb PCI hardware is now split across
multiple files. Include them in the maintainers
block.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index fd25e4ecf0b9..605a385cea36 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3500,7 +3500,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/nsaenz/linux-rpi.git
F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
-F: drivers/pci/controller/pcie-brcmstb.c
+F: drivers/pci/controller/pcie-brcmstb*
F: drivers/staging/vc04_services
N: bcm2711
N: bcm283*
--
2.31.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [PATCH v2 4/4] MAINTAINERS: Widen brcmstb PCIe file scope
2021-08-19 21:56 ` [PATCH v2 4/4] MAINTAINERS: Widen brcmstb PCIe file scope Jeremy Linton
@ 2021-08-20 19:09 ` Bjorn Helgaas
2021-08-22 8:55 ` Florian Fainelli
0 siblings, 1 reply; 18+ messages in thread
From: Bjorn Helgaas @ 2021-08-20 19:09 UTC (permalink / raw)
To: Jeremy Linton
Cc: linux-pci, lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh,
kw, f.fainelli, sdonthineni, stefan.wahren,
bcm-kernel-feedback-list, linux-acpi, linux-arm-kernel,
linux-rpi-kernel, linux-kernel
On Thu, Aug 19, 2021 at 04:56:55PM -0500, Jeremy Linton wrote:
> The brcmstb PCI hardware is now split across
> multiple files. Include them in the maintainers
> block.
Rewrap to fill 75 columns or so.
> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fd25e4ecf0b9..605a385cea36 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -3500,7 +3500,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> S: Maintained
> T: git git://git.kernel.org/pub/scm/linux/kernel/git/nsaenz/linux-rpi.git
> F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> -F: drivers/pci/controller/pcie-brcmstb.c
> +F: drivers/pci/controller/pcie-brcmstb*
There are already two entries that mention
drivers/pci/controller/pcie-brcmstb.c, and a patch headed for v5.14
adds a third. Do you want to update them all?
> F: drivers/staging/vc04_services
> N: bcm2711
> N: bcm283*
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 4/4] MAINTAINERS: Widen brcmstb PCIe file scope
2021-08-20 19:09 ` Bjorn Helgaas
@ 2021-08-22 8:55 ` Florian Fainelli
0 siblings, 0 replies; 18+ messages in thread
From: Florian Fainelli @ 2021-08-22 8:55 UTC (permalink / raw)
To: Bjorn Helgaas, Jeremy Linton
Cc: linux-pci, lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh,
kw, sdonthineni, stefan.wahren, bcm-kernel-feedback-list,
linux-acpi, linux-arm-kernel, linux-rpi-kernel, linux-kernel
On 8/20/2021 9:09 PM, Bjorn Helgaas wrote:
> On Thu, Aug 19, 2021 at 04:56:55PM -0500, Jeremy Linton wrote:
>> The brcmstb PCI hardware is now split across
>> multiple files. Include them in the maintainers
>> block.
>
> Rewrap to fill 75 columns or so.
>
>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>> ---
>> MAINTAINERS | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index fd25e4ecf0b9..605a385cea36 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -3500,7 +3500,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>> S: Maintained
>> T: git git://git.kernel.org/pub/scm/linux/kernel/git/nsaenz/linux-rpi.git
>> F: Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
>> -F: drivers/pci/controller/pcie-brcmstb.c
>> +F: drivers/pci/controller/pcie-brcmstb*
>
> There are already two entries that mention
> drivers/pci/controller/pcie-brcmstb.c, and a patch headed for v5.14
> adds a third. Do you want to update them all?
That would be a good idea, the patch that Bjorn is referring to is:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=e647eff57466c8cf7547532d6b26166b9b17f341
With that fixed:
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v2 0/4] CM4 ACPI PCIe quirk
2021-08-19 21:56 [PATCH v2 0/4] CM4 ACPI PCIe quirk Jeremy Linton
` (3 preceding siblings ...)
2021-08-19 21:56 ` [PATCH v2 4/4] MAINTAINERS: Widen brcmstb PCIe file scope Jeremy Linton
@ 2021-08-20 19:11 ` Bjorn Helgaas
4 siblings, 0 replies; 18+ messages in thread
From: Bjorn Helgaas @ 2021-08-20 19:11 UTC (permalink / raw)
To: Jeremy Linton
Cc: linux-pci, lorenzo.pieralisi, nsaenz, bhelgaas, rjw, lenb, robh,
kw, f.fainelli, sdonthineni, stefan.wahren,
bcm-kernel-feedback-list, linux-acpi, linux-arm-kernel,
linux-rpi-kernel, linux-kernel
On Thu, Aug 19, 2021 at 04:56:51PM -0500, Jeremy Linton wrote:
> The PFTF CM4 is an ACPI platform that is following the Arm PCIe SMC
> (DEN0115) standard because its PCIe config space isn't ECAM compliant
> since it is split into two parts. One part describes the root port
> registers, and another contains a moveable window pointing at a given
> device's 4K config space. Thus it doesn't have an MCFG table. As
> Linux doesn't support the PCI/SMC, a host bridge specific _DSD is
> added and associated with custom ECAM ops and cfgres. The custom cfg
> op selects between those two regions, as well as disallowing
> problematic accesses.
>
> V1->V2:
> Only move register definitions to new .h file, add
> include guards.
> Change quirk namespace identifier.
> Update Maintainers file.
> A number of whitespace, grammar, etc fixes.
>
>
> Jeremy Linton (4):
> PCI: brcmstb: Break register definitions into separate header
> PCI: brcmstb: Add ACPI config space quirk
> PCI/ACPI: Add Broadcom bcm2711 MCFG quirk
> MAINTAINERS: Widen brcmstb PCIe file scope
>
> MAINTAINERS | 2 +-
> drivers/acpi/pci_mcfg.c | 13 ++
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pcie-brcmstb-acpi.c | 74 ++++++++++
> drivers/pci/controller/pcie-brcmstb.c | 150 +-------------------
> drivers/pci/controller/pcie-brcmstb.h | 155 +++++++++++++++++++++
> include/linux/pci-ecam.h | 1 +
> 7 files changed, 247 insertions(+), 149 deletions(-)
> create mode 100644 drivers/pci/controller/pcie-brcmstb-acpi.c
> create mode 100644 drivers/pci/controller/pcie-brcmstb.h
I'm fine with all of these, given the minor comments I made.
Lorenzo, if you want to pick this up after Jeremy updates it:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
^ permalink raw reply [flat|nested] 18+ messages in thread