* [PATCH v4 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge @ 2022-11-07 9:54 Thippeswamy Havalige 2022-11-07 9:54 ` [PATCH v4 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL " Thippeswamy Havalige 2022-11-07 10:06 ` [PATCH v4 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI " Krzysztof Kozlowski 0 siblings, 2 replies; 4+ messages in thread From: Thippeswamy Havalige @ 2022-11-07 9:54 UTC (permalink / raw) To: linux-pci, linux-kernel, devicetree, krzysztof.kozlowski Cc: bhelgaas, michals, robh+dt, nagaradhesh.yeleswarapu, bharat.kumar.gogada, Thippeswamy Havalige Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge dt binding. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> --- Changes in v4: Modified to same style of quotes as in other places. Removed spaces between <> of reg, ranges, interrupts properties. --- .../devicetree/bindings/pci/xilinx-pcie.txt | 88 ------------------- .../bindings/pci/xlnx,axi-pcie-host.yaml | 88 +++++++++++++++++++ 2 files changed, 88 insertions(+), 88 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt deleted file mode 100644 index fd57a81180a4..000000000000 --- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt +++ /dev/null @@ -1,88 +0,0 @@ -* Xilinx AXI PCIe Root Port Bridge DT description - -Required properties: -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- compatible: Should contain "xlnx,axi-pcie-host-1.00.a" -- reg: Should contain AXI PCIe registers location and length -- device_type: must be "pci" -- interrupts: Should contain AXI PCIe interrupt -- interrupt-map-mask, - interrupt-map: standard PCI properties to define the mapping of the - PCI interface to interrupt numbers. -- ranges: ranges for the PCI memory regions (I/O space region is not - supported by hardware) - Please refer to the standard PCI bus binding document for a more - detailed explanation - -Optional properties for Zynq/Microblaze: -- bus-range: PCI bus numbers covered - -Interrupt controller child node -+++++++++++++++++++++++++++++++ -Required properties: -- interrupt-controller: identifies the node as an interrupt controller -- #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. - -NOTE: -The core provides a single interrupt for both INTx/MSI messages. So, -created a interrupt controller node to support 'interrupt-map' DT -functionality. The driver will create an IRQ domain for this map, decode -the four INTx interrupts in ISR and route them to this domain. - - -Example: -++++++++ -Zynq: - pci_express: axi-pcie@50000000 { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = < 0x50000000 0x1000000 >; - device_type = "pci"; - interrupts = < 0 52 4 >; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 1>, - <0 0 0 2 &pcie_intc 2>, - <0 0 0 3 &pcie_intc 3>, - <0 0 0 4 &pcie_intc 4>; - ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >; - - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - -Microblaze: - pci_express: axi-pcie@10000000 { - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - reg = <0x10000000 0x4000000>; - device_type = "pci"; - interrupt-parent = <µblaze_0_intc>; - interrupts = <1 2>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 1>, - <0 0 0 2 &pcie_intc 2>, - <0 0 0 3 &pcie_intc 3>, - <0 0 0 4 &pcie_intc 4>; - ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>; - - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - - }; diff --git a/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml new file mode 100644 index 000000000000..69b7decabd45 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xlnx,axi-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI PCIe Root Port Bridge + +maintainers: + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + +properties: + compatible: + const: xlnx,axi-pcie-host-1.00.a + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ranges: + items: + - description: | + ranges for the PCI memory regions (I/O space region is not + supported by hardware) + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + + additionalProperties: false + +required: + - compatible + - reg + - ranges + - interrupts + - interrupt-map + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + pcie@50000000 { + compatible = "xlnx,axi-pcie-host-1.00.a"; + reg = <0x50000000 0x1000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 1>, + <0 0 0 2 &pcie_intc 2>, + <0 0 0 3 &pcie_intc 3>, + <0 0 0 4 &pcie_intc 4>; + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>; + pcie_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v4 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge 2022-11-07 9:54 [PATCH v4 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge Thippeswamy Havalige @ 2022-11-07 9:54 ` Thippeswamy Havalige 2022-11-07 10:07 ` Krzysztof Kozlowski 2022-11-07 10:06 ` [PATCH v4 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI " Krzysztof Kozlowski 1 sibling, 1 reply; 4+ messages in thread From: Thippeswamy Havalige @ 2022-11-07 9:54 UTC (permalink / raw) To: linux-pci, linux-kernel, devicetree, krzysztof.kozlowski Cc: bhelgaas, michals, robh+dt, nagaradhesh.yeleswarapu, bharat.kumar.gogada, Thippeswamy Havalige Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge dt binding. Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> --- Changes in v4: Dropped, msi-controller property as it comes from msi schema. Rearranged interrupts description as per example. Used same style of quotes. --- .../bindings/pci/xilinx-nwl-pcie.txt | 73 --------- .../bindings/pci/xlnx,nwl-pcie.yaml | 149 ++++++++++++++++++ 2 files changed, 149 insertions(+), 73 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt deleted file mode 100644 index f56f8c58c5d9..000000000000 --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Xilinx NWL PCIe Root Port Bridge DT description - -Required properties: -- compatible: Should contain "xlnx,nwl-pcie-2.11" -- #address-cells: Address representation for root ports, set to <3> -- #size-cells: Size representation for root ports, set to <2> -- #interrupt-cells: specifies the number of cells needed to encode an - interrupt source. The value must be 1. -- reg: Should contain Bridge, PCIe Controller registers location, - configuration space, and length -- reg-names: Must include the following entries: - "breg": bridge registers - "pcireg": PCIe controller registers - "cfg": configuration space region -- device_type: must be "pci" -- interrupts: Should contain NWL PCIe interrupt -- interrupt-names: Must include the following entries: - "msi1, msi0": interrupt asserted when an MSI is received - "intx": interrupt asserted when a legacy interrupt is received - "misc": interrupt asserted when miscellaneous interrupt is received -- interrupt-map-mask and interrupt-map: standard PCI properties to define the - mapping of the PCI interface to interrupt numbers. -- ranges: ranges for the PCI memory regions (I/O space region is not - supported by hardware) - Please refer to the standard PCI bus binding document for a more - detailed explanation -- msi-controller: indicates that this is MSI controller node -- msi-parent: MSI parent of the root complex itself -- legacy-interrupt-controller: Interrupt controller device node for Legacy - interrupts - - interrupt-controller: identifies the node as an interrupt controller - - #interrupt-cells: should be set to 1 - - #address-cells: specifies the number of cells needed to encode an - address. The value must be 0. - -Optional properties: -- dma-coherent: present if DMA operations are coherent -- clocks: Input clock specifier. Refer to common clock bindings - -Example: -++++++++ - -nwl_pcie: pcie@fd0e0000 { - #address-cells = <3>; - #size-cells = <2>; - compatible = "xlnx,nwl-pcie-2.11"; - #interrupt-cells = <1>; - msi-controller; - device_type = "pci"; - interrupt-parent = <&gic>; - interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>; - interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - - msi-parent = <&nwl_pcie>; - reg = <0x0 0xfd0e0000 0x0 0x1000>, - <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; - reg-names = "breg", "pcireg", "cfg"; - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ - - pcie_intc: legacy-interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - -}; diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml new file mode 100644 index 000000000000..35c2d9fb3b9b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx NWL PCIe Root Port Bridge + +maintainers: + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: xlnx,nwl-pcie-2.11 + + reg: + items: + - description: PCIe bridge registers location. + - description: PCIe Controller registers location. + - description: PCIe Configuration space region. + + reg-names: + items: + - const: breg + - const: pcireg + - const: cfg + + interrupts: + items: + - description: interrupt asserted when miscellaneous interrupt is received + - description: unused interrupt(dummy) + - description: interrupt asserted when a legacy interrupt is received + - description: msi1 interrupt asserted when an MSI is received + - description: msi0 interrupt asserted when an MSI is received + + interrupt-names: + minItems: 4 + items: + - const: misc + - const: dummy + - const: intx + - const: msi1 + - const: msi0 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + "#interrupt-cells": + const: 1 + + msi-parent: + description: MSI controller the device is capable of using. + + interrupt-map: + maxItems: 4 + + power-domains: + maxItems: 1 + + iommus: + maxItems: 1 + + dma-coherent: + description: Optional, present if DMA operations are coherent + + clocks: + description: Optional, input clock specifier. + + legacy-interrupt-controller: + description: Interrupt controller node for handling legacy PCI interrupts. + type: object + properties: + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + "interrupt-controller": true + + required: + - "#address-cells" + - "#interrupt-cells" + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - "#interrupt-cells" + - interrupt-map + - interrupt-map-mask + - msi-controller + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/xlnx-zynqmp-power.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + nwl_pcie: pcie@fd0e0000 { + compatible = "xlnx,nwl-pcie-2.11"; + reg = <0x0 0xfd0e0000 0x0 0x1000>, + <0x0 0xfd480000 0x0 0x1000>, + <0x80 0x00000000 0x0 0x1000000>; + reg-names = "breg", "pcireg", "cfg"; + ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, + <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + msi-controller; + device_type = "pci"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; + msi-parent = <&nwl_pcie>; + power-domains = <&zynqmp_firmware PD_PCIE>; + iommus = <&smmu 0x4d0>; + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v4 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL PCIe Root Port Bridge 2022-11-07 9:54 ` [PATCH v4 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL " Thippeswamy Havalige @ 2022-11-07 10:07 ` Krzysztof Kozlowski 0 siblings, 0 replies; 4+ messages in thread From: Krzysztof Kozlowski @ 2022-11-07 10:07 UTC (permalink / raw) To: Thippeswamy Havalige, linux-pci, linux-kernel, devicetree Cc: bhelgaas, michals, robh+dt, nagaradhesh.yeleswarapu, bharat.kumar.gogada On 07/11/2022 10:54, Thippeswamy Havalige wrote: > Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge > dt binding. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > --- > Changes in v4: > Dropped, msi-controller property as it comes from msi schema. > Rearranged interrupts description as per example. > Used same style of quotes. > --- > .../bindings/pci/xilinx-nwl-pcie.txt | 73 --------- > .../bindings/pci/xlnx,nwl-pcie.yaml | 149 ++++++++++++++++++ > 2 files changed, 149 insertions(+), 73 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > create mode 100644 Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > deleted file mode 100644 > index f56f8c58c5d9..000000000000 > --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > +++ /dev/null > @@ -1,73 +0,0 @@ > -* Xilinx NWL PCIe Root Port Bridge DT description > - > -Required properties: > -- compatible: Should contain "xlnx,nwl-pcie-2.11" > -- #address-cells: Address representation for root ports, set to <3> > -- #size-cells: Size representation for root ports, set to <2> > -- #interrupt-cells: specifies the number of cells needed to encode an > - interrupt source. The value must be 1. > -- reg: Should contain Bridge, PCIe Controller registers location, > - configuration space, and length > -- reg-names: Must include the following entries: > - "breg": bridge registers > - "pcireg": PCIe controller registers > - "cfg": configuration space region > -- device_type: must be "pci" > -- interrupts: Should contain NWL PCIe interrupt > -- interrupt-names: Must include the following entries: > - "msi1, msi0": interrupt asserted when an MSI is received > - "intx": interrupt asserted when a legacy interrupt is received > - "misc": interrupt asserted when miscellaneous interrupt is received > -- interrupt-map-mask and interrupt-map: standard PCI properties to define the > - mapping of the PCI interface to interrupt numbers. > -- ranges: ranges for the PCI memory regions (I/O space region is not > - supported by hardware) > - Please refer to the standard PCI bus binding document for a more > - detailed explanation > -- msi-controller: indicates that this is MSI controller node > -- msi-parent: MSI parent of the root complex itself > -- legacy-interrupt-controller: Interrupt controller device node for Legacy > - interrupts > - - interrupt-controller: identifies the node as an interrupt controller > - - #interrupt-cells: should be set to 1 > - - #address-cells: specifies the number of cells needed to encode an > - address. The value must be 0. > - > -Optional properties: > -- dma-coherent: present if DMA operations are coherent > -- clocks: Input clock specifier. Refer to common clock bindings > - > -Example: > -++++++++ > - > -nwl_pcie: pcie@fd0e0000 { > - #address-cells = <3>; > - #size-cells = <2>; > - compatible = "xlnx,nwl-pcie-2.11"; > - #interrupt-cells = <1>; > - msi-controller; > - device_type = "pci"; > - interrupt-parent = <&gic>; > - interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>; > - interrupt-names = "msi0", "msi1", "intx", "dummy", "misc"; > - interrupt-map-mask = <0x0 0x0 0x0 0x7>; > - interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, > - <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, > - <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, > - <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; > - > - msi-parent = <&nwl_pcie>; > - reg = <0x0 0xfd0e0000 0x0 0x1000>, > - <0x0 0xfd480000 0x0 0x1000>, > - <0x80 0x00000000 0x0 0x1000000>; > - reg-names = "breg", "pcireg", "cfg"; > - ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ > - 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ > - > - pcie_intc: legacy-interrupt-controller { > - interrupt-controller; > - #address-cells = <0>; > - #interrupt-cells = <1>; > - }; > - > -}; > diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > new file mode 100644 > index 000000000000..35c2d9fb3b9b > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml > @@ -0,0 +1,149 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx NWL PCIe Root Port Bridge > + > +maintainers: > + - Thippeswamy Havalige <thippeswamy.havalige@amd.com> > + > +allOf: > + - $ref: /schemas/pci/pci-bus.yaml# > + - $ref: /schemas/interrupt-controller/msi-controller.yaml# > + > +properties: > + compatible: > + const: xlnx,nwl-pcie-2.11 > + > + reg: > + items: > + - description: PCIe bridge registers location. > + - description: PCIe Controller registers location. > + - description: PCIe Configuration space region. > + > + reg-names: > + items: > + - const: breg > + - const: pcireg > + - const: cfg > + > + interrupts: > + items: > + - description: interrupt asserted when miscellaneous interrupt is received > + - description: unused interrupt(dummy) > + - description: interrupt asserted when a legacy interrupt is received > + - description: msi1 interrupt asserted when an MSI is received > + - description: msi0 interrupt asserted when an MSI is received > + > + interrupt-names: > + minItems: 4 This still does not match your interrupts. It should not be different. Either you require 4 or 5 interrupts. Not 4 and 5... > + items: > + - const: misc > + - const: dummy > + - const: intx > + - const: msi1 > + - const: msi0 > + > + interrupt-map-mask: > + items: > + - const: 0 > + - const: 0 > + - const: 0 > + - const: 7 > + Best regards, Krzysztof ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v4 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge 2022-11-07 9:54 [PATCH v4 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge Thippeswamy Havalige 2022-11-07 9:54 ` [PATCH v4 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL " Thippeswamy Havalige @ 2022-11-07 10:06 ` Krzysztof Kozlowski 1 sibling, 0 replies; 4+ messages in thread From: Krzysztof Kozlowski @ 2022-11-07 10:06 UTC (permalink / raw) To: Thippeswamy Havalige, linux-pci, linux-kernel, devicetree Cc: bhelgaas, michals, robh+dt, nagaradhesh.yeleswarapu, bharat.kumar.gogada On 07/11/2022 10:54, Thippeswamy Havalige wrote: > Convert to YAML dtschemas of Xilinx AXI PCIe Root Port Bridge > dt binding. > > Just one blank line before SoB. With commit fixes: Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com> > --- Best regards, Krzysztof ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-11-07 10:08 UTC | newest] Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-11-07 9:54 [PATCH v4 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI PCIe Root Port Bridge Thippeswamy Havalige 2022-11-07 9:54 ` [PATCH v4 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML schemas of Xilinx NWL " Thippeswamy Havalige 2022-11-07 10:07 ` Krzysztof Kozlowski 2022-11-07 10:06 ` [PATCH v4 1/2] dt-bindings: PCI: xilinx-pcie: Convert to YAML schemas of Xilinx AXI " Krzysztof Kozlowski
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