* [PATCH] perf vendor events arm64: Add to core JSON events for eMAG
@ 2018-08-23 20:22 Sean V Kelley
2018-08-28 17:35 ` John Garry
[not found] ` <CAAbOPF1h1S1U2R-xxeYAH=CimZdYjOYUxaL9GDQ7yS5T6W7dpA@mail.gmail.com>
0 siblings, 2 replies; 4+ messages in thread
From: Sean V Kelley @ 2018-08-23 20:22 UTC (permalink / raw)
To: linux-arm-kernel, linux-perf-users, acme
Cc: Alexander Shishkin, Will Deacon, Peter Zijlstra,
Ganapatrao Kulkarni, Namhyung Kim, Sean V Kelley, Jiri Olsa,
William Cohen
Adds the remainder of the supported ARMv8 recommended IMPLEMENTATION
DEFINED events for the Ampere Computing eMAG file.
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: William Cohen <wcohen@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Sean V Kelley <seanvk.dev@oregontracks.org>
---
.../arch/arm64/ampere/emag/core-imp-def.json | 150 +++++++++++++++++-
1 file changed, 144 insertions(+), 6 deletions(-)
diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
index bc03c06c3918..d95202dbe2b2 100644
--- a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
@@ -9,7 +9,7 @@
"ArchStdEvent": "L1D_CACHE_REFILL_RD",
},
{
- "ArchStdEvent": "L1D_CACHE_REFILL_WR",
+ "ArchStdEvent": "L1D_CACHE_INVAL",
},
{
"ArchStdEvent": "L1D_TLB_REFILL_RD",
@@ -18,15 +18,153 @@
"ArchStdEvent": "L1D_TLB_REFILL_WR",
},
{
- "ArchStdEvent": "L1D_TLB_RD",
+ "ArchStdEvent": "L2D_CACHE_RD",
},
{
- "ArchStdEvent": "L1D_TLB_WR",
+ "ArchStdEvent": "L2D_CACHE_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_RD",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_REFILL_WR",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
+ },
+ {
+ "ArchStdEvent": "L2D_CACHE_INVAL",
},
{
"ArchStdEvent": "BUS_ACCESS_RD",
- },
- {
+ },
+ {
"ArchStdEvent": "BUS_ACCESS_WR",
- }
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_NORMAL",
+ },
+ {
+ "ArchStdEvent": "BUS_ACCESS_PERIPH",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_RD",
+ },
+ {
+ "ArchStdEvent": "MEM_ACCESS_WR",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "UNALIGNED_LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDREX_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_PASS_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_FAIL_SPEC",
+ },
+ {
+ "ArchStdEvent": "STREX_SPEC",
+ },
+ {
+ "ArchStdEvent": "LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "ST_SPEC",
+ },
+ {
+ "ArchStdEvent": "LDST_SPEC",
+ },
+ {
+ "ArchStdEvent": "DP_SPEC",
+ },
+ {
+ "ArchStdEvent": "ASE_SPEC",
+ },
+ {
+ "ArchStdEvent": "VFP_SPEC",
+ },
+ {
+ "ArchStdEvent": "PC_WRITE_SPEC",
+ },
+ {
+ "ArchStdEvent": "CRYPTO_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_IMMED_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_RETURN_SPEC",
+ },
+ {
+ "ArchStdEvent": "BR_INDIRECT_SPEC",
+ },
+ {
+ "ArchStdEvent": "ISB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DSB_SPEC",
+ },
+ {
+ "ArchStdEvent": "DMB_SPEC",
+ },
+ {
+ "ArchStdEvent": "EXC_UNDEF",
+ },
+ {
+ "ArchStdEvent": "EXC_SVC",
+ },
+ {
+ "ArchStdEvent": "EXC_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_FIQ",
+ },
+ {
+ "ArchStdEvent": "EXC_HVC",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_PABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_DABORT",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_OTHER",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_IRQ",
+ },
+ {
+ "ArchStdEvent": "EXC_TRAP_FIQ",
+ },
+ {
+ "ArchStdEvent": "RC_LD_SPEC",
+ },
+ {
+ "ArchStdEvent": "RC_ST_SPEC",
+ },
]
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add to core JSON events for eMAG
2018-08-23 20:22 [PATCH] perf vendor events arm64: Add to core JSON events for eMAG Sean V Kelley
@ 2018-08-28 17:35 ` John Garry
[not found] ` <CAAbOPF1h1S1U2R-xxeYAH=CimZdYjOYUxaL9GDQ7yS5T6W7dpA@mail.gmail.com>
1 sibling, 0 replies; 4+ messages in thread
From: John Garry @ 2018-08-28 17:35 UTC (permalink / raw)
To: Sean V Kelley, linux-arm-kernel, linux-perf-users, acme
Cc: Alexander Shishkin, Will Deacon, Peter Zijlstra,
Ganapatrao Kulkarni, Namhyung Kim, William Cohen, Jiri Olsa
On 23/08/2018 21:22, Sean V Kelley wrote:
> Adds the remainder of the supported ARMv8 recommended IMPLEMENTATION
> DEFINED events for the Ampere Computing eMAG file.
>
> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> Cc: Jiri Olsa <jolsa@redhat.com>
> Cc: Namhyung Kim <namhyung@kernel.org>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: William Cohen <wcohen@redhat.com>
> Cc: linux-arm-kernel@lists.infradead.org
>
> Signed-off-by: Sean V Kelley <seanvk.dev@oregontracks.org>
> ---
> .../arch/arm64/ampere/emag/core-imp-def.json | 150 +++++++++++++++++-
> 1 file changed, 144 insertions(+), 6 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
> index bc03c06c3918..d95202dbe2b2 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
> @@ -9,7 +9,7 @@
> "ArchStdEvent": "L1D_CACHE_REFILL_RD",
> },
> {
> - "ArchStdEvent": "L1D_CACHE_REFILL_WR",
You seem to be removing event support here, which is not consistent with
the commit log. Please explain.
> + "ArchStdEvent": "L1D_CACHE_INVAL",
> },
> {
> "ArchStdEvent": "L1D_TLB_REFILL_RD",
> @@ -18,15 +18,153 @@
> "ArchStdEvent": "L1D_TLB_REFILL_WR",
> },
> {
> - "ArchStdEvent": "L1D_TLB_RD",
> + "ArchStdEvent": "L2D_CACHE_RD",
> },
> {
> - "ArchStdEvent": "L1D_TLB_WR",
> + "ArchStdEvent": "L2D_CACHE_WR",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_REFILL_RD",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_REFILL_WR",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_INVAL",
> },
> {
> "ArchStdEvent": "BUS_ACCESS_RD",
> - },
> - {
> + },
> + {
> "ArchStdEvent": "BUS_ACCESS_WR",
> - }
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_SHARED",
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_NORMAL",
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_PERIPH",
> + },
> + {
> + "ArchStdEvent": "MEM_ACCESS_RD",
> + },
> + {
> + "ArchStdEvent": "MEM_ACCESS_WR",
> + },
> + {
> + "ArchStdEvent": "UNALIGNED_LD_SPEC",
> + },
> + {
> + "ArchStdEvent": "UNALIGNED_ST_SPEC",
> + },
> + {
> + "ArchStdEvent": "UNALIGNED_LDST_SPEC",
> + },
> + {
> + "ArchStdEvent": "LDREX_SPEC",
> + },
> + {
> + "ArchStdEvent": "STREX_PASS_SPEC",
> + },
> + {
> + "ArchStdEvent": "STREX_FAIL_SPEC",
> + },
> + {
> + "ArchStdEvent": "STREX_SPEC",
> + },
> + {
> + "ArchStdEvent": "LD_SPEC",
> + },
> + {
> + "ArchStdEvent": "ST_SPEC",
> + },
> + {
> + "ArchStdEvent": "LDST_SPEC",
> + },
> + {
> + "ArchStdEvent": "DP_SPEC",
> + },
> + {
> + "ArchStdEvent": "ASE_SPEC",
> + },
> + {
> + "ArchStdEvent": "VFP_SPEC",
> + },
> + {
> + "ArchStdEvent": "PC_WRITE_SPEC",
> + },
> + {
> + "ArchStdEvent": "CRYPTO_SPEC",
> + },
> + {
> + "ArchStdEvent": "BR_IMMED_SPEC",
> + },
> + {
> + "ArchStdEvent": "BR_RETURN_SPEC",
> + },
> + {
> + "ArchStdEvent": "BR_INDIRECT_SPEC",
> + },
> + {
> + "ArchStdEvent": "ISB_SPEC",
> + },
> + {
> + "ArchStdEvent": "DSB_SPEC",
> + },
> + {
> + "ArchStdEvent": "DMB_SPEC",
> + },
> + {
> + "ArchStdEvent": "EXC_UNDEF",
> + },
> + {
> + "ArchStdEvent": "EXC_SVC",
> + },
> + {
> + "ArchStdEvent": "EXC_PABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_DABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_IRQ",
> + },
> + {
> + "ArchStdEvent": "EXC_FIQ",
> + },
> + {
> + "ArchStdEvent": "EXC_HVC",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_PABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_DABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_OTHER",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_IRQ",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_FIQ",
> + },
> + {
> + "ArchStdEvent": "RC_LD_SPEC",
> + },
> + {
> + "ArchStdEvent": "RC_ST_SPEC",
> + },
> ]
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add to core JSON events for eMAG
[not found] ` <CAAbOPF1h1S1U2R-xxeYAH=CimZdYjOYUxaL9GDQ7yS5T6W7dpA@mail.gmail.com>
@ 2018-08-28 18:54 ` William Cohen
2018-08-30 4:14 ` Sean V Kelley
0 siblings, 1 reply; 4+ messages in thread
From: William Cohen @ 2018-08-28 18:54 UTC (permalink / raw)
To: Sean V Kelley, linux-arm-kernel, linux-perf-users, acme,
will.deacon, john.garry
On 08/28/2018 01:21 PM, Sean V Kelley wrote:
>
>
> On Thu, Aug 23, 2018 at 1:23 PM Sean V Kelley <seanvk.dev@oregontracks.org <mailto:seanvk.dev@oregontracks.org>> wrote:
>
> Adds the remainder of the supported ARMv8 recommended IMPLEMENTATION
> DEFINED events for the Ampere Computing eMAG file.
>
>
> Just checking in? Perhaps John, William or Will could take a look if you have time?
>
> Thanks,
>
> Sean
Hi,
Is there some public manual that lists the performance events for the Ampere eMAG? As mentioned that some unavailable events were incorrectly added to the lists for the processor. Having a reference for this would allow checking for those types of problems.
One suggestions would be to split the events into multiple JSON files like the x86 and arm cortex 53 processors, so related events grouped into meaningful functional groups rather than just one long alphabetical list.
Otherwise the patch looks reasonable.
-William Cohen
>
>
>
>
> Cc: Arnaldo Carvalho de Melo <acme@kernel.org <mailto:acme@kernel.org>>
> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com <mailto:alexander.shishkin@linux.intel.com>>
> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com <mailto:ganapatrao.kulkarni@cavium.com>>
> Cc: Jiri Olsa <jolsa@redhat.com <mailto:jolsa@redhat.com>>
> Cc: Namhyung Kim <namhyung@kernel.org <mailto:namhyung@kernel.org>>
> Cc: Peter Zijlstra <peterz@infradead.org <mailto:peterz@infradead.org>>
> Cc: Will Deacon <will.deacon@arm.com <mailto:will.deacon@arm.com>>
> Cc: William Cohen <wcohen@redhat.com <mailto:wcohen@redhat.com>>
> Cc: linux-arm-kernel@lists.infradead.org <mailto:linux-arm-kernel@lists.infradead.org>
>
> Signed-off-by: Sean V Kelley <seanvk.dev@oregontracks.org <mailto:seanvk.dev@oregontracks.org>>
> ---
> .../arch/arm64/ampere/emag/core-imp-def.json | 150 +++++++++++++++++-
> 1 file changed, 144 insertions(+), 6 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
> index bc03c06c3918..d95202dbe2b2 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
> @@ -9,7 +9,7 @@
> "ArchStdEvent": "L1D_CACHE_REFILL_RD",
> },
> {
> - "ArchStdEvent": "L1D_CACHE_REFILL_WR",
> + "ArchStdEvent": "L1D_CACHE_INVAL",
> },
> {
> "ArchStdEvent": "L1D_TLB_REFILL_RD",
> @@ -18,15 +18,153 @@
> "ArchStdEvent": "L1D_TLB_REFILL_WR",
> },
> {
> - "ArchStdEvent": "L1D_TLB_RD",
> + "ArchStdEvent": "L2D_CACHE_RD",
> },
> {
> - "ArchStdEvent": "L1D_TLB_WR",
> + "ArchStdEvent": "L2D_CACHE_WR",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_REFILL_RD",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_REFILL_WR",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_INVAL",
> },
> {
> "ArchStdEvent": "BUS_ACCESS_RD",
> - },
> - {
> + },
> + {
> "ArchStdEvent": "BUS_ACCESS_WR",
> - }
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_SHARED",
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_NORMAL",
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_PERIPH",
> + },
> + {
> + "ArchStdEvent": "MEM_ACCESS_RD",
> + },
> + {
> + "ArchStdEvent": "MEM_ACCESS_WR",
> + },
> + {
> + "ArchStdEvent": "UNALIGNED_LD_SPEC",
> + },
> + {
> + "ArchStdEvent": "UNALIGNED_ST_SPEC",
> + },
> + {
> + "ArchStdEvent": "UNALIGNED_LDST_SPEC",
> + },
> + {
> + "ArchStdEvent": "LDREX_SPEC",
> + },
> + {
> + "ArchStdEvent": "STREX_PASS_SPEC",
> + },
> + {
> + "ArchStdEvent": "STREX_FAIL_SPEC",
> + },
> + {
> + "ArchStdEvent": "STREX_SPEC",
> + },
> + {
> + "ArchStdEvent": "LD_SPEC",
> + },
> + {
> + "ArchStdEvent": "ST_SPEC",
> + },
> + {
> + "ArchStdEvent": "LDST_SPEC",
> + },
> + {
> + "ArchStdEvent": "DP_SPEC",
> + },
> + {
> + "ArchStdEvent": "ASE_SPEC",
> + },
> + {
> + "ArchStdEvent": "VFP_SPEC",
> + },
> + {
> + "ArchStdEvent": "PC_WRITE_SPEC",
> + },
> + {
> + "ArchStdEvent": "CRYPTO_SPEC",
> + },
> + {
> + "ArchStdEvent": "BR_IMMED_SPEC",
> + },
> + {
> + "ArchStdEvent": "BR_RETURN_SPEC",
> + },
> + {
> + "ArchStdEvent": "BR_INDIRECT_SPEC",
> + },
> + {
> + "ArchStdEvent": "ISB_SPEC",
> + },
> + {
> + "ArchStdEvent": "DSB_SPEC",
> + },
> + {
> + "ArchStdEvent": "DMB_SPEC",
> + },
> + {
> + "ArchStdEvent": "EXC_UNDEF",
> + },
> + {
> + "ArchStdEvent": "EXC_SVC",
> + },
> + {
> + "ArchStdEvent": "EXC_PABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_DABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_IRQ",
> + },
> + {
> + "ArchStdEvent": "EXC_FIQ",
> + },
> + {
> + "ArchStdEvent": "EXC_HVC",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_PABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_DABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_OTHER",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_IRQ",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_FIQ",
> + },
> + {
> + "ArchStdEvent": "RC_LD_SPEC",
> + },
> + {
> + "ArchStdEvent": "RC_ST_SPEC",
> + },
> ]
> --
> 2.17.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] perf vendor events arm64: Add to core JSON events for eMAG
2018-08-28 18:54 ` William Cohen
@ 2018-08-30 4:14 ` Sean V Kelley
0 siblings, 0 replies; 4+ messages in thread
From: Sean V Kelley @ 2018-08-30 4:14 UTC (permalink / raw)
To: wcohen; +Cc: linux-perf-users, john.garry, will.deacon, acme, linux-arm-kernel
On Tue, Aug 28, 2018 at 11:55 AM William Cohen <wcohen@redhat.com> wrote:
> On 08/28/2018 01:21 PM, Sean V Kelley wrote:
> >
> >
> > On Thu, Aug 23, 2018 at 1:23 PM Sean V Kelley <seanvk.dev@oregontracks.org <mailto:seanvk.dev@oregontracks.org>> wrote:
> >
> > Adds the remainder of the supported ARMv8 recommended IMPLEMENTATION
> > DEFINED events for the Ampere Computing eMAG file.
> >
> >
> > Just checking in? Perhaps John, William or Will could take a look if you have time?
> >
> > Thanks,
> >
> > Sean
>
> Hi,
>
> Is there some public manual that lists the performance events for the Ampere eMAG? As mentioned that some unavailable events were incorrectly added to the lists for the processor. Having a reference for this would allow checking for those types of problems.
>
Hi,
Yes, the intent is to get the public manual published and easily accessible from a link. And I agree it's an essential reference for patches now and when the hardware is fully available.
>
> One suggestions would be to split the events into multiple JSON files like the x86 and arm cortex 53 processors, so related events grouped into meaningful functional groups rather than just one long alphabetical list.
Thanks I will take a look.
Sean
Otherwise the patch looks reasonable.
-William Cohen
>
>
>
>
> Cc: Arnaldo Carvalho de Melo <acme@kernel.org <mailto:acme@kernel.org>>
> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com <mailto:alexander.shishkin@linux.intel.com>>
> Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com <mailto:ganapatrao.kulkarni@cavium.com>>
> Cc: Jiri Olsa <jolsa@redhat.com <mailto:jolsa@redhat.com>>
> Cc: Namhyung Kim <namhyung@kernel.org <mailto:namhyung@kernel.org>>
> Cc: Peter Zijlstra <peterz@infradead.org <mailto:peterz@infradead.org>>
> Cc: Will Deacon <will.deacon@arm.com <mailto:will.deacon@arm.com>>
> Cc: William Cohen <wcohen@redhat.com <mailto:wcohen@redhat.com>>
> Cc: linux-arm-kernel@lists.infradead.org <mailto:linux-arm-kernel@lists.infradead.org>
>
> Signed-off-by: Sean V Kelley <seanvk.dev@oregontracks.org <mailto:seanvk.dev@oregontracks.org>>
> ---
> .../arch/arm64/ampere/emag/core-imp-def.json | 150 +++++++++++++++++-
> 1 file changed, 144 insertions(+), 6 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
> index bc03c06c3918..d95202dbe2b2 100644
> --- a/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
> +++ b/tools/perf/pmu-events/arch/arm64/ampere/emag/core-imp-def.json
> @@ -9,7 +9,7 @@
> "ArchStdEvent": "L1D_CACHE_REFILL_RD",
> },
> {
> - "ArchStdEvent": "L1D_CACHE_REFILL_WR",
> + "ArchStdEvent": "L1D_CACHE_INVAL",
> },
> {
> "ArchStdEvent": "L1D_TLB_REFILL_RD",
> @@ -18,15 +18,153 @@
> "ArchStdEvent": "L1D_TLB_REFILL_WR",
> },
> {
> - "ArchStdEvent": "L1D_TLB_RD",
> + "ArchStdEvent": "L2D_CACHE_RD",
> },
> {
> - "ArchStdEvent": "L1D_TLB_WR",
> + "ArchStdEvent": "L2D_CACHE_WR",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_REFILL_RD",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_REFILL_WR",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_WB_VICTIM",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_WB_CLEAN",
> + },
> + {
> + "ArchStdEvent": "L2D_CACHE_INVAL",
> },
> {
> "ArchStdEvent": "BUS_ACCESS_RD",
> - },
> - {
> + },
> + {
> "ArchStdEvent": "BUS_ACCESS_WR",
> - }
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_SHARED",
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_NOT_SHARED",
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_NORMAL",
> + },
> + {
> + "ArchStdEvent": "BUS_ACCESS_PERIPH",
> + },
> + {
> + "ArchStdEvent": "MEM_ACCESS_RD",
> + },
> + {
> + "ArchStdEvent": "MEM_ACCESS_WR",
> + },
> + {
> + "ArchStdEvent": "UNALIGNED_LD_SPEC",
> + },
> + {
> + "ArchStdEvent": "UNALIGNED_ST_SPEC",
> + },
> + {
> + "ArchStdEvent": "UNALIGNED_LDST_SPEC",
> + },
> + {
> + "ArchStdEvent": "LDREX_SPEC",
> + },
> + {
> + "ArchStdEvent": "STREX_PASS_SPEC",
> + },
> + {
> + "ArchStdEvent": "STREX_FAIL_SPEC",
> + },
> + {
> + "ArchStdEvent": "STREX_SPEC",
> + },
> + {
> + "ArchStdEvent": "LD_SPEC",
> + },
> + {
> + "ArchStdEvent": "ST_SPEC",
> + },
> + {
> + "ArchStdEvent": "LDST_SPEC",
> + },
> + {
> + "ArchStdEvent": "DP_SPEC",
> + },
> + {
> + "ArchStdEvent": "ASE_SPEC",
> + },
> + {
> + "ArchStdEvent": "VFP_SPEC",
> + },
> + {
> + "ArchStdEvent": "PC_WRITE_SPEC",
> + },
> + {
> + "ArchStdEvent": "CRYPTO_SPEC",
> + },
> + {
> + "ArchStdEvent": "BR_IMMED_SPEC",
> + },
> + {
> + "ArchStdEvent": "BR_RETURN_SPEC",
> + },
> + {
> + "ArchStdEvent": "BR_INDIRECT_SPEC",
> + },
> + {
> + "ArchStdEvent": "ISB_SPEC",
> + },
> + {
> + "ArchStdEvent": "DSB_SPEC",
> + },
> + {
> + "ArchStdEvent": "DMB_SPEC",
> + },
> + {
> + "ArchStdEvent": "EXC_UNDEF",
> + },
> + {
> + "ArchStdEvent": "EXC_SVC",
> + },
> + {
> + "ArchStdEvent": "EXC_PABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_DABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_IRQ",
> + },
> + {
> + "ArchStdEvent": "EXC_FIQ",
> + },
> + {
> + "ArchStdEvent": "EXC_HVC",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_PABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_DABORT",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_OTHER",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_IRQ",
> + },
> + {
> + "ArchStdEvent": "EXC_TRAP_FIQ",
> + },
> + {
> + "ArchStdEvent": "RC_LD_SPEC",
> + },
> + {
> + "ArchStdEvent": "RC_ST_SPEC",
> + },
> ]
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-08-30 4:14 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-23 20:22 [PATCH] perf vendor events arm64: Add to core JSON events for eMAG Sean V Kelley
2018-08-28 17:35 ` John Garry
[not found] ` <CAAbOPF1h1S1U2R-xxeYAH=CimZdYjOYUxaL9GDQ7yS5T6W7dpA@mail.gmail.com>
2018-08-28 18:54 ` William Cohen
2018-08-30 4:14 ` Sean V Kelley
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