[PATCH v2 1/2] perf/x86/intel: Expose EPT-friendly PEBS for SPR and future models

[PATCH v2 1/2] perf/x86/intel: Expose EPT-friendly PEBS for SPR and future models

[Like Xu]

From: Like Xu <likexu@tencent.com>

According to Intel SDM, the EPT-friendly PEBS is supported by all the
platforms after ICX, ADL and the future platforms with PEBS format 5.

Currently the only in-kernel user of this capability is KVM, which has
very limited support for hybrid core pmu, so ADL and its successors do
not currently expose this capability. When both hybrid core and PEBS
format 5 are present, KVM will decide on its own merits.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-perf-users@vger.kernel.org
Suggested-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Like Xu <likexu@tencent.com>
---
V1 -> V2 Changelog:
- the perf part should be a separate patch; (Kan)
- apply PEBS format 5 to avoid patching every future model; (Kan)

 arch/x86/events/intel/core.c | 1 +
 arch/x86/events/intel/ds.c   | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2db93498ff71..804540ba4599 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6288,6 +6288,7 @@ __init int intel_pmu_init(void)
 		x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
 		x86_pmu.extra_regs = intel_spr_extra_regs;
 		x86_pmu.limit_period = spr_limit_period;
+		x86_pmu.pebs_ept = 1;
 		x86_pmu.pebs_aliases = NULL;
 		x86_pmu.pebs_prec_dist = true;
 		x86_pmu.pebs_block = true;
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index ba60427caa6d..4e937f685cdc 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2253,8 +2253,10 @@ void __init intel_ds_init(void)
 			x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
 			break;
 
-		case 4:
 		case 5:
+			x86_pmu.pebs_ept = 1;
+			fallthrough;
+		case 4:
 			x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
 			x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
 			if (x86_pmu.intel_cap.pebs_baseline) {
-- 
2.37.3

Re: [PATCH v2 1/2] perf/x86/intel: Expose EPT-friendly PEBS for SPR and future models

[Liang, Kan]

On 2022-09-22 1:19 a.m., Like Xu wrote:
> From: Like Xu <likexu@tencent.com>
> 
> According to Intel SDM, the EPT-friendly PEBS is supported by all the
> platforms after ICX, ADL and the future platforms with PEBS format 5.
> 
> Currently the only in-kernel user of this capability is KVM, which has
> very limited support for hybrid core pmu, so ADL and its successors do
> not currently expose this capability. When both hybrid core and PEBS
> format 5 are present, KVM will decide on its own merits.
> 
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: linux-perf-users@vger.kernel.org
> Suggested-by: Kan Liang <kan.liang@linux.intel.com>
> Signed-off-by: Like Xu <likexu@tencent.com>


Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

Thanks,
Kan

> ---
> V1 -> V2 Changelog:
> - the perf part should be a separate patch; (Kan)
> - apply PEBS format 5 to avoid patching every future model; (Kan)
> 
>  arch/x86/events/intel/core.c | 1 +
>  arch/x86/events/intel/ds.c   | 4 +++-
>  2 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 2db93498ff71..804540ba4599 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -6288,6 +6288,7 @@ __init int intel_pmu_init(void)
>  		x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
>  		x86_pmu.extra_regs = intel_spr_extra_regs;
>  		x86_pmu.limit_period = spr_limit_period;
> +		x86_pmu.pebs_ept = 1;
>  		x86_pmu.pebs_aliases = NULL;
>  		x86_pmu.pebs_prec_dist = true;
>  		x86_pmu.pebs_block = true;
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index ba60427caa6d..4e937f685cdc 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -2253,8 +2253,10 @@ void __init intel_ds_init(void)
>  			x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
>  			break;
>  
> -		case 4:
>  		case 5:
> +			x86_pmu.pebs_ept = 1;
> +			fallthrough;
> +		case 4:
>  			x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
>  			x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
>  			if (x86_pmu.intel_cap.pebs_baseline) {