* [PATCH v5 1/8] dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible
2023-03-30 8:40 [PATCH v5 0/8] Enable IPQ9754 USB Varadarajan Narayanan
@ 2023-03-30 8:40 ` Varadarajan Narayanan
2023-03-30 8:40 ` [PATCH v5 2/8] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY Varadarajan Narayanan
` (6 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-30 8:40 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
Cc: Varadarajan Narayanan
Document the compatible string used for the qusb2 phy in IPQ9574.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Changes in v5:
- Undo v4 changes
Changes in v4:
- Remove constraints not applicable to IPQ9574
Changes in v3:
- Maintain the proper sorted order
Changes in v2:
- Moved ipq6018 to the proper place and placed ipq9574
next to it as suggested by Dmitry
---
Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
index 7f403e7..20e18d5 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
@@ -18,13 +18,14 @@ properties:
oneOf:
- items:
- enum:
+ - qcom,ipq6018-qusb2-phy
- qcom,ipq8074-qusb2-phy
+ - qcom,ipq9574-qusb2-phy
- qcom,msm8953-qusb2-phy
- qcom,msm8996-qusb2-phy
- qcom,msm8998-qusb2-phy
- qcom,qcm2290-qusb2-phy
- qcom,sdm660-qusb2-phy
- - qcom,ipq6018-qusb2-phy
- qcom,sm4250-qusb2-phy
- qcom,sm6115-qusb2-phy
- items:
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 2/8] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY
2023-03-30 8:40 [PATCH v5 0/8] Enable IPQ9754 USB Varadarajan Narayanan
2023-03-30 8:40 ` [PATCH v5 1/8] dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible Varadarajan Narayanan
@ 2023-03-30 8:40 ` Varadarajan Narayanan
2023-03-30 8:40 ` [PATCH v5 3/8] dt-bindings: usb: dwc3: Add IPQ9574 compatible Varadarajan Narayanan
` (5 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-30 8:40 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
Cc: Varadarajan Narayanan
Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Note: In the earlier patch sets, had used the (legacy)
specification available in qcom,msm8996-qmp-usb3-phy.yaml. Moved
to newer specification in qcom,sc8280xp-qmp-usb3-uni-phy.yaml
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
index 16fce10..9a18410 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- qcom,sc8280xp-qmp-usb3-uni-phy
+ - qcom,ipq9574-qmp-usb3-phy
reg:
maxItems: 1
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 3/8] dt-bindings: usb: dwc3: Add IPQ9574 compatible
2023-03-30 8:40 [PATCH v5 0/8] Enable IPQ9754 USB Varadarajan Narayanan
2023-03-30 8:40 ` [PATCH v5 1/8] dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible Varadarajan Narayanan
2023-03-30 8:40 ` [PATCH v5 2/8] dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY Varadarajan Narayanan
@ 2023-03-30 8:40 ` Varadarajan Narayanan
2023-03-30 9:39 ` Dmitry Baryshkov
2023-03-30 12:47 ` Rob Herring
2023-03-30 8:40 ` [PATCH v5 4/8] clk: qcom: gcc-ipq9574: Add USB related clocks Varadarajan Narayanan
` (4 subsequent siblings)
7 siblings, 2 replies; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-30 8:40 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
Cc: Varadarajan Narayanan
Document the IPQ9574 dwc3 compatible.
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Changes in v5:
- Restore removed constraints
Changes in v4:
- Update other relevant sections
- Remove constraints not applicable to IPQ9574
---
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index a2aabda..8def6a3 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -17,6 +17,7 @@ properties:
- qcom,ipq6018-dwc3
- qcom,ipq8064-dwc3
- qcom,ipq8074-dwc3
+ - qcom,ipq9574-dwc3
- qcom,msm8953-dwc3
- qcom,msm8994-dwc3
- qcom,msm8996-dwc3
@@ -242,6 +243,24 @@ allOf:
compatible:
contains:
enum:
+ - qcom,ipq9574-dwc3
+ then:
+ properties:
+ clocks:
+ maxItems: 5
+ clock-names:
+ items:
+ - const: sys_noc_axi
+ - const: anoc_axi
+ - const: master
+ - const: sleep
+ - const: mock_utmi
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,msm8994-dwc3
- qcom,qcs404-dwc3
then:
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v5 3/8] dt-bindings: usb: dwc3: Add IPQ9574 compatible
2023-03-30 8:40 ` [PATCH v5 3/8] dt-bindings: usb: dwc3: Add IPQ9574 compatible Varadarajan Narayanan
@ 2023-03-30 9:39 ` Dmitry Baryshkov
2023-03-30 12:47 ` Rob Herring
1 sibling, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-03-30 9:39 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
<quic_varada@quicinc.com> wrote:
>
> Document the IPQ9574 dwc3 compatible.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> Changes in v5:
> - Restore removed constraints
>
> Changes in v4:
> - Update other relevant sections
> - Remove constraints not applicable to IPQ9574
> ---
> Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> index a2aabda..8def6a3 100644
> --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> @@ -17,6 +17,7 @@ properties:
> - qcom,ipq6018-dwc3
> - qcom,ipq8064-dwc3
> - qcom,ipq8074-dwc3
> + - qcom,ipq9574-dwc3
> - qcom,msm8953-dwc3
> - qcom,msm8994-dwc3
> - qcom,msm8996-dwc3
> @@ -242,6 +243,24 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,ipq9574-dwc3
> + then:
> + properties:
> + clocks:
> + maxItems: 5
> + clock-names:
> + items:
> + - const: sys_noc_axi
> + - const: anoc_axi
> + - const: master
> + - const: sleep
> + - const: mock_utmi
Is there any chance of using clock names that are close to the names
used by existing platforms?
I think this fits into the third 'if' bucket:
cfg_noc = sys_noc_axi
core = master
iface = anoc_axi
sleep = sleep
mock_utmi = mock_utmi
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> - qcom,msm8994-dwc3
> - qcom,qcs404-dwc3
> then:
> --
> 2.7.4
>
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v5 3/8] dt-bindings: usb: dwc3: Add IPQ9574 compatible
2023-03-30 8:40 ` [PATCH v5 3/8] dt-bindings: usb: dwc3: Add IPQ9574 compatible Varadarajan Narayanan
2023-03-30 9:39 ` Dmitry Baryshkov
@ 2023-03-30 12:47 ` Rob Herring
1 sibling, 0 replies; 20+ messages in thread
From: Rob Herring @ 2023-03-30 12:47 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: konrad.dybcio, linux-phy, andersson, gregkh, agross, robh+dt,
linux-arm-msm, linux-clk, sboyd, vkoul, linux-kernel, mturquette,
linux-usb, kishon, krzysztof.kozlowski+dt, quic_wcheng,
devicetree
On Thu, 30 Mar 2023 14:10:45 +0530, Varadarajan Narayanan wrote:
> Document the IPQ9574 dwc3 compatible.
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> Changes in v5:
> - Restore removed constraints
>
> Changes in v4:
> - Update other relevant sections
> - Remove constraints not applicable to IPQ9574
> ---
> Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/cb8f2ba0ff39951aeada479ed3895d19c9f72617.1680162377.git.quic_varada@quicinc.com
usb2@60f8800: clock-names:0: 'core' was expected
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dtb
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtb
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dtb
usb2@60f8800: 'dwc3@6000000' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dtb
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtb
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dtb
usb2@60f8800: 'interrupt-names' is a required property
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dtb
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtb
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtb
usb2@60f8800: 'oneOf' conditional failed, one must be fixed:
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dtb
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtb
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtb
usb2@60f8800: 'power-domains' is a required property
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dtb
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtb
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtb
usb3@100f8800: 'dwc3@10000000', 'reset-names' do not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm/boot/dts/qcom-ipq8064-ap148.dtb
arch/arm/boot/dts/qcom-ipq8064-rb3011.dtb
usb3@110f8800: 'dwc3@11000000', 'reset-names' do not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm/boot/dts/qcom-ipq8064-ap148.dtb
arch/arm/boot/dts/qcom-ipq8064-rb3011.dtb
usb3@110f8800: 'interrupt-names' is a required property
arch/arm/boot/dts/qcom-ipq8064-rb3011.dtb
usb3@110f8800: 'oneOf' conditional failed, one must be fixed:
arch/arm/boot/dts/qcom-ipq8064-rb3011.dtb
usb3@110f8800: 'power-domains' is a required property
arch/arm/boot/dts/qcom-ipq8064-rb3011.dtb
usb3@8af8800: 'dwc3@8a00000' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dtb
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtb
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dtb
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dtb
usb3@8af8800: 'interrupt-names' is a required property
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dtb
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtb
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtb
usb3@8af8800: 'oneOf' conditional failed, one must be fixed:
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dtb
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtb
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtb
usb3@8af8800: 'power-domains' is a required property
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dtb
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtb
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dtb
usb@4ef8800: 'interrupt-names' is a required property
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb
usb@4ef8800: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb
usb@4ef8800: usb@4e00000: Unevaluated properties are not allowed ('extcon' was unexpected)
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb
usb@6af8800: 'extcon' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb
arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dtb
arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dtb
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dtb
usb@6af8800: usb@6a00000: Unevaluated properties are not allowed ('extcon' was unexpected)
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb
arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dtb
arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-scorpio.dtb
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dtb
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-kagura.dtb
arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-keyaki.dtb
arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dtb
usb@70f8800: 'interrupt-names' is a required property
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb
usb@70f8800: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb
usb@70f8800: 'power-domains' is a required property
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb
usb@70f8800: usb@7000000: Unevaluated properties are not allowed ('phy_mode' was unexpected)
arch/arm64/boot/dts/qcom/msm8953-motorola-potter.dtb
arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dtb
arch/arm64/boot/dts/qcom/msm8953-xiaomi-mido.dtb
arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dtb
arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dtb
arch/arm64/boot/dts/qcom/sdm450-motorola-ali.dtb
arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dtb
arch/arm64/boot/dts/qcom/sdm632-motorola-ocean.dtb
usb@7678800: 'interrupt-names' is a required property
arch/arm64/boot/dts/qcom/qcs404-evb-1000.dtb
arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
usb@7678800: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/qcs404-evb-1000.dtb
arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
usb@7678800: 'power-domains' is a required property
arch/arm64/boot/dts/qcom/qcs404-evb-1000.dtb
arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
usb@76f8800: 'extcon' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb
usb@76f8800: 'interrupt-names' is a required property
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb
usb@76f8800: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb
usb@76f8800: usb@7600000: Unevaluated properties are not allowed ('extcon' was unexpected)
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb
usb@79b8800: 'interrupt-names' is a required property
arch/arm64/boot/dts/qcom/qcs404-evb-1000.dtb
arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
usb@79b8800: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/qcs404-evb-1000.dtb
arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
usb@79b8800: 'power-domains' is a required property
arch/arm64/boot/dts/qcom/qcs404-evb-1000.dtb
arch/arm64/boot/dts/qcom/qcs404-evb-4000.dtb
usb@8af8800: assigned-clock-rates: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dtb
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb
usb@8af8800: assigned-clocks: [[4, 124], [4, 125], [4, 126]] is too long
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dtb
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb
usb@8af8800: assigned-clocks: [[9, 186], [9, 158], [9, 159]] is too long
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb
usb@8af8800: 'interrupt-names' is a required property
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
usb@8af8800: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
usb@8cf8800: assigned-clock-rates: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dtb
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb
usb@8cf8800: assigned-clocks: [[4, 131], [4, 132], [4, 133]] is too long
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
arch/arm64/boot/dts/qcom/ipq8074-hk10-c1.dtb
arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb
usb@8cf8800: 'interrupt-names' is a required property
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
usb@8cf8800: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/ipq8074-hk01.dtb
usb@a6f8800: 'dr_mode' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dtb
usb@a6f8800: 'dwc3@a600000' does not match any of the regexes: '^usb@[0-9a-f]+$', 'pinctrl-[0-9]+'
arch/arm/boot/dts/qcom-sdx55-mtp.dtb
arch/arm/boot/dts/qcom-sdx55-t55.dtb
arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dtb
usb@a6f8800: usb@a600000: Unevaluated properties are not allowed ('maximum-spped' was unexpected)
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish.dtb
usb@a8f8800: assigned-clock-rates: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dtb
arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dtb
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dtb
usb@a8f8800: assigned-clocks: [[34, 92], [34, 91], [35, 64]] is too long
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dtb
arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dtb
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dtb
usb@a8f8800: usb@a800000: Unevaluated properties are not allowed ('extcon' was unexpected)
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dtb
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dtb
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dtb
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dtb
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dtb
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dtb
usb@c2f8800: clock-names:2: 'iface' was expected
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dtb
arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dtb
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dtb
usb@c2f8800: clock-names: ['cfg_noc', 'core', 'mock_utmi', 'sleep'] is too short
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dtb
arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dtb
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dtb
usb@c2f8800: clocks: [[34, 48], [34, 88], [34, 89], [34, 90]] is too short
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dtb
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dtb
arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dtb
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dtb
usb@c2f8800: 'power-domains' is a required property
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dtb
usb@f92f8800: 'interrupt-names' is a required property
arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dtb
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dtb
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dtb
arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dtb
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dtb
arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dtb
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dtb
usb@f92f8800: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dtb
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dtb
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dtb
arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dtb
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dtb
arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dtb
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dtb
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dtb
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 4/8] clk: qcom: gcc-ipq9574: Add USB related clocks
2023-03-30 8:40 [PATCH v5 0/8] Enable IPQ9754 USB Varadarajan Narayanan
` (2 preceding siblings ...)
2023-03-30 8:40 ` [PATCH v5 3/8] dt-bindings: usb: dwc3: Add IPQ9574 compatible Varadarajan Narayanan
@ 2023-03-30 8:40 ` Varadarajan Narayanan
2023-03-30 8:40 ` [PATCH v5 5/8] phy: qcom-qusb2: add QUSB2 support for IPQ9574 Varadarajan Narayanan
` (3 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-30 8:40 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
Cc: Varadarajan Narayanan
Add the clocks needed for enabling USB in IPQ9574
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Changes in v2:
- Fixed coding style issues
---
drivers/clk/qcom/gcc-ipq9574.c | 37 ++++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,ipq9574-gcc.h | 2 ++
2 files changed, 39 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 1bf33d5..06b724a 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -2041,6 +2041,41 @@ static struct clk_regmap_mux usb0_pipe_clk_src = {
},
};
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x2c054,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x2c054,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &usb0_pipe_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x2c058,
+ .clkr = {
+ .enable_reg = 0x2c058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+ .parent_hws = (const struct clk_hw *[]) {
+ &gcc_sleep_clk_src.clkr.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
F(144000, P_XO, 16, 12, 125),
F(400000, P_XO, 12, 1, 5),
@@ -4008,6 +4043,8 @@ static struct clk_regmap *gcc_ipq9574_clks[] = {
[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
index 14543a4..97a7b19 100644
--- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h
@@ -214,4 +214,6 @@
#define GCC_SNOC_PCIE1_1LANE_S_CLK 205
#define GCC_SNOC_PCIE2_2LANE_S_CLK 206
#define GCC_SNOC_PCIE3_2LANE_S_CLK 207
+#define GCC_USB0_PIPE_CLK 208
+#define GCC_USB0_SLEEP_CLK 209
#endif
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 5/8] phy: qcom-qusb2: add QUSB2 support for IPQ9574
2023-03-30 8:40 [PATCH v5 0/8] Enable IPQ9754 USB Varadarajan Narayanan
` (3 preceding siblings ...)
2023-03-30 8:40 ` [PATCH v5 4/8] clk: qcom: gcc-ipq9574: Add USB related clocks Varadarajan Narayanan
@ 2023-03-30 8:40 ` Varadarajan Narayanan
2023-03-30 8:40 ` [PATCH v5 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence Varadarajan Narayanan
` (2 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-30 8:40 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
Cc: Varadarajan Narayanan
Add the phy init sequence for the Super Speed ports found
on IPQ9574.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Changes in v2:
- Place the entry such that the list continues to be sorted
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 2ef638b..bec6e40 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -912,6 +912,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
.compatible = "qcom,ipq8074-qusb2-phy",
.data = &msm8996_phy_cfg,
}, {
+ .compatible = "qcom,ipq9574-qusb2-phy",
+ .data = &ipq6018_phy_cfg,
+ }, {
.compatible = "qcom,msm8953-qusb2-phy",
.data = &msm8996_phy_cfg,
}, {
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v5 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
2023-03-30 8:40 [PATCH v5 0/8] Enable IPQ9754 USB Varadarajan Narayanan
` (4 preceding siblings ...)
2023-03-30 8:40 ` [PATCH v5 5/8] phy: qcom-qusb2: add QUSB2 support for IPQ9574 Varadarajan Narayanan
@ 2023-03-30 8:40 ` Varadarajan Narayanan
2023-03-30 9:41 ` Dmitry Baryshkov
2023-03-30 8:40 ` [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes Varadarajan Narayanan
2023-03-30 8:40 ` [PATCH v5 8/8] arm64: dts: qcom: ipq9574: Enable USB Varadarajan Narayanan
7 siblings, 1 reply; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-30 8:40 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
Cc: Varadarajan Narayanan, Praveenkumar I
Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
Reused clock and reset list from existing targets.
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Changes in v5:
- Fix additional review comments
- Use V3 register offsets
Changes in v4:
- Use qmp_usb_offsets for register space access
Changes in v3:
- Fix hex captitalization
Changes in v2:
- Removed unused phy register offsets
- Moved the clock entries to the correct place
- Maintain sorted order
---
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index a49711c..77041dd 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
};
+static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+ /* PLL and Loop filter settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+ /* SSC settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
+ QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
+};
+
+static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
@@ -1558,6 +1640,14 @@ static const char * const qmp_phy_vreg_l[] = {
"vdda-phy", "vdda-pll",
};
+static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
+ .serdes = 0,
+ .pcs = 0x800,
+ .pcs_usb = 0,
+ .tx = 0x200,
+ .rx = 0x400,
+};
+
static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
.serdes = 0,
.pcs = 0x0200,
@@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
.regs = qmp_v3_usb3phy_regs_layout,
};
+static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
+ .lanes = 1,
+
+ .offsets = &qmp_usb_offsets_ipq9574,
+
+ .serdes_tbl = ipq9574_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
+ .tx_tbl = ipq9574_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
+ .rx_tbl = ipq9574_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
+ .pcs_tbl = ipq9574_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
+ .clk_list = qmp_v4_phy_clk_l,
+ .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
+ .reset_list = qcm2290_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = qmp_v3_usb3phy_regs_layout,
+};
+
static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
.lanes = 1,
@@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
.compatible = "qcom,ipq8074-qmp-usb3-phy",
.data = &ipq8074_usb3phy_cfg,
}, {
+ .compatible = "qcom,ipq9574-qmp-usb3-phy",
+ .data = &ipq9574_usb3phy_cfg,
+ }, {
.compatible = "qcom,msm8996-qmp-usb3-phy",
.data = &msm8996_usb3phy_cfg,
}, {
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v5 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
2023-03-30 8:40 ` [PATCH v5 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence Varadarajan Narayanan
@ 2023-03-30 9:41 ` Dmitry Baryshkov
2023-03-30 12:57 ` Varadarajan Narayanan
0 siblings, 1 reply; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-03-30 9:41 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk, Praveenkumar I
On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
<quic_varada@quicinc.com> wrote:
>
> Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> Reused clock and reset list from existing targets.
>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> Changes in v5:
> - Fix additional review comments
> - Use V3 register offsets
> Changes in v4:
> - Use qmp_usb_offsets for register space access
> Changes in v3:
> - Fix hex captitalization
> Changes in v2:
> - Removed unused phy register offsets
> - Moved the clock entries to the correct place
> - Maintain sorted order
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> index a49711c..77041dd 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> @@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> };
>
> +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> + /* PLL and Loop filter settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
> + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> +};
> +
> +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> +};
> +
> static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> @@ -1558,6 +1640,14 @@ static const char * const qmp_phy_vreg_l[] = {
> "vdda-phy", "vdda-pll",
> };
>
> +static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
> + .serdes = 0,
> + .pcs = 0x800,
> + .pcs_usb = 0,
No, pcs_usb is not 0.
> + .tx = 0x200,
> + .rx = 0x400,
> +};
> +
> static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
> .serdes = 0,
> .pcs = 0x0200,
> @@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> .regs = qmp_v3_usb3phy_regs_layout,
> };
>
> +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> + .lanes = 1,
> +
> + .offsets = &qmp_usb_offsets_ipq9574,
> +
> + .serdes_tbl = ipq9574_usb3_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> + .tx_tbl = ipq9574_usb3_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> + .rx_tbl = ipq9574_usb3_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> + .pcs_tbl = ipq9574_usb3_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> + .clk_list = qmp_v4_phy_clk_l,
> + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> + .reset_list = qcm2290_usb3phy_reset_l,
> + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = qmp_v3_usb3phy_regs_layout,
> +};
> +
> static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> .lanes = 1,
>
> @@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> .compatible = "qcom,ipq8074-qmp-usb3-phy",
> .data = &ipq8074_usb3phy_cfg,
> }, {
> + .compatible = "qcom,ipq9574-qmp-usb3-phy",
> + .data = &ipq9574_usb3phy_cfg,
> + }, {
> .compatible = "qcom,msm8996-qmp-usb3-phy",
> .data = &msm8996_usb3phy_cfg,
> }, {
> --
> 2.7.4
>
--
With best wishes
Dmitry
--
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v5 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
2023-03-30 9:41 ` Dmitry Baryshkov
@ 2023-03-30 12:57 ` Varadarajan Narayanan
2023-03-30 13:09 ` Dmitry Baryshkov
0 siblings, 1 reply; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-30 12:57 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk, Praveenkumar I
On Thu, Mar 30, 2023 at 12:41:08PM +0300, Dmitry Baryshkov wrote:
> On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
> <quic_varada@quicinc.com> wrote:
> >
> > Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> > Reused clock and reset list from existing targets.
> >
> > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > Changes in v5:
> > - Fix additional review comments
> > - Use V3 register offsets
> > Changes in v4:
> > - Use qmp_usb_offsets for register space access
> > Changes in v3:
> > - Fix hex captitalization
> > Changes in v2:
> > - Removed unused phy register offsets
> > - Moved the clock entries to the correct place
> > - Maintain sorted order
> > ---
> > drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
> > 1 file changed, 115 insertions(+)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > index a49711c..77041dd 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > @@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> > [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> > };
> >
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> > + /* PLL and Loop filter settings */
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> > + /* SSC settings */
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
> > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> > + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> > + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> > +};
> > +
> > +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> > +};
> > +
> > static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > @@ -1558,6 +1640,14 @@ static const char * const qmp_phy_vreg_l[] = {
> > "vdda-phy", "vdda-pll",
> > };
> >
> > +static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
> > + .serdes = 0,
> > + .pcs = 0x800,
> > + .pcs_usb = 0,
>
> No, pcs_usb is not 0.
Not sure I understand this comment.
Since IPQ9574 uses new style DT entries, pcs_usb_offset = 0 and
that will not be used.
qmp->pcs_usb is used in qmp_usb_enable_autonomous_mode and
qmp_usb_disable_autonomous_mode. If "qmp->pcs_usb == 0", those
functions use the value of qmp->pcs (0x7d800) for pcs_usb.
The registers used in these functions are
QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR & QPHY_PCS_AUTONOMOUS_MODE_CTRL
The offsets for the above registers as specified in
qmp_v3_usb3phy_regs_layout is
#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL 0x0d8
#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0dc
qphy_{set|clr}bits called from qmp_usb_enable_autonomous_mode and
qmp_usb_disable_autonomous_mode will use the offset 0x7d8d8 and
0x78d8c. This offset matches with the register offset document of
the IPQ9574. So, felt setting pcs_usb to zero should be ok. Can
you please clarify.
Thanks
Varada
>
> > + .tx = 0x200,
> > + .rx = 0x400,
> > +};
> > +
> > static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
> > .serdes = 0,
> > .pcs = 0x0200,
> > @@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> > .regs = qmp_v3_usb3phy_regs_layout,
> > };
> >
> > +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> > + .lanes = 1,
> > +
> > + .offsets = &qmp_usb_offsets_ipq9574,
> > +
> > + .serdes_tbl = ipq9574_usb3_serdes_tbl,
> > + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> > + .tx_tbl = ipq9574_usb3_tx_tbl,
> > + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> > + .rx_tbl = ipq9574_usb3_rx_tbl,
> > + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> > + .pcs_tbl = ipq9574_usb3_pcs_tbl,
> > + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> > + .clk_list = qmp_v4_phy_clk_l,
> > + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> > + .reset_list = qcm2290_usb3phy_reset_l,
> > + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
> > + .vreg_list = qmp_phy_vreg_l,
> > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> > + .regs = qmp_v3_usb3phy_regs_layout,
> > +};
> > +
> > static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> > .lanes = 1,
> >
> > @@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> > .compatible = "qcom,ipq8074-qmp-usb3-phy",
> > .data = &ipq8074_usb3phy_cfg,
> > }, {
> > + .compatible = "qcom,ipq9574-qmp-usb3-phy",
> > + .data = &ipq9574_usb3phy_cfg,
> > + }, {
> > .compatible = "qcom,msm8996-qmp-usb3-phy",
> > .data = &msm8996_usb3phy_cfg,
> > }, {
> > --
> > 2.7.4
> >
>
>
> --
> With best wishes
> Dmitry
--
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v5 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
2023-03-30 12:57 ` Varadarajan Narayanan
@ 2023-03-30 13:09 ` Dmitry Baryshkov
2023-03-31 6:47 ` Varadarajan Narayanan
0 siblings, 1 reply; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-03-30 13:09 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk, Praveenkumar I
On Thu, 30 Mar 2023 at 15:58, Varadarajan Narayanan
<quic_varada@quicinc.com> wrote:
>
> On Thu, Mar 30, 2023 at 12:41:08PM +0300, Dmitry Baryshkov wrote:
> > On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
> > <quic_varada@quicinc.com> wrote:
> > >
> > > Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> > > Reused clock and reset list from existing targets.
> > >
> > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > ---
> > > Changes in v5:
> > > - Fix additional review comments
> > > - Use V3 register offsets
> > > Changes in v4:
> > > - Use qmp_usb_offsets for register space access
> > > Changes in v3:
> > > - Fix hex captitalization
> > > Changes in v2:
> > > - Removed unused phy register offsets
> > > - Moved the clock entries to the correct place
> > > - Maintain sorted order
> > > ---
> > > drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
> > > 1 file changed, 115 insertions(+)
> > >
> > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > > index a49711c..77041dd 100644
> > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > > @@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> > > [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> > > };
> > >
> > > +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> > > + /* PLL and Loop filter settings */
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> > > + /* SSC settings */
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
> > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> > > + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> > > + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> > > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> > > +};
> > > +
> > > +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> > > +};
> > > +
> > > static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> > > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > > QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > > @@ -1558,6 +1640,14 @@ static const char * const qmp_phy_vreg_l[] = {
> > > "vdda-phy", "vdda-pll",
> > > };
> > >
> > > +static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
> > > + .serdes = 0,
> > > + .pcs = 0x800,
> > > + .pcs_usb = 0,
> >
> > No, pcs_usb is not 0.
>
> Not sure I understand this comment.
>
> Since IPQ9574 uses new style DT entries, pcs_usb_offset = 0 and
> that will not be used.
>
> qmp->pcs_usb is used in qmp_usb_enable_autonomous_mode and
> qmp_usb_disable_autonomous_mode. If "qmp->pcs_usb == 0", those
> functions use the value of qmp->pcs (0x7d800) for pcs_usb.
So, you mixed qmp->pcs_usb and offsets->pcs_usb here. They are not equal.
>
> The registers used in these functions are
> QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR & QPHY_PCS_AUTONOMOUS_MODE_CTRL
>
> The offsets for the above registers as specified in
> qmp_v3_usb3phy_regs_layout is
>
> #define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL 0x0d8
> #define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0dc
>
> qphy_{set|clr}bits called from qmp_usb_enable_autonomous_mode and
> qmp_usb_disable_autonomous_mode will use the offset 0x7d8d8 and
> 0x78d8c. This offset matches with the register offset document of
> the IPQ9574. So, felt setting pcs_usb to zero should be ok. Can
> you please clarify.
And this tells you what pcs_usb offset is.
>
> Thanks
> Varada
>
>
> >
> > > + .tx = 0x200,
> > > + .rx = 0x400,
> > > +};
> > > +
> > > static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
> > > .serdes = 0,
> > > .pcs = 0x0200,
> > > @@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> > > .regs = qmp_v3_usb3phy_regs_layout,
> > > };
> > >
> > > +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> > > + .lanes = 1,
> > > +
> > > + .offsets = &qmp_usb_offsets_ipq9574,
> > > +
> > > + .serdes_tbl = ipq9574_usb3_serdes_tbl,
> > > + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> > > + .tx_tbl = ipq9574_usb3_tx_tbl,
> > > + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> > > + .rx_tbl = ipq9574_usb3_rx_tbl,
> > > + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> > > + .pcs_tbl = ipq9574_usb3_pcs_tbl,
> > > + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> > > + .clk_list = qmp_v4_phy_clk_l,
> > > + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> > > + .reset_list = qcm2290_usb3phy_reset_l,
> > > + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
> > > + .vreg_list = qmp_phy_vreg_l,
> > > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> > > + .regs = qmp_v3_usb3phy_regs_layout,
> > > +};
> > > +
> > > static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> > > .lanes = 1,
> > >
> > > @@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> > > .compatible = "qcom,ipq8074-qmp-usb3-phy",
> > > .data = &ipq8074_usb3phy_cfg,
> > > }, {
> > > + .compatible = "qcom,ipq9574-qmp-usb3-phy",
> > > + .data = &ipq9574_usb3phy_cfg,
> > > + }, {
> > > .compatible = "qcom,msm8996-qmp-usb3-phy",
> > > .data = &msm8996_usb3phy_cfg,
> > > }, {
> > > --
> > > 2.7.4
> > >
> >
> >
> > --
> > With best wishes
> > Dmitry
--
With best wishes
Dmitry
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v5 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence
2023-03-30 13:09 ` Dmitry Baryshkov
@ 2023-03-31 6:47 ` Varadarajan Narayanan
0 siblings, 0 replies; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-31 6:47 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk, Praveenkumar I
On Thu, Mar 30, 2023 at 04:09:41PM +0300, Dmitry Baryshkov wrote:
> On Thu, 30 Mar 2023 at 15:58, Varadarajan Narayanan
> <quic_varada@quicinc.com> wrote:
> >
> > On Thu, Mar 30, 2023 at 12:41:08PM +0300, Dmitry Baryshkov wrote:
> > > On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
> > > <quic_varada@quicinc.com> wrote:
> > > >
> > > > Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
> > > > Reused clock and reset list from existing targets.
> > > >
> > > > Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > > ---
> > > > Changes in v5:
> > > > - Fix additional review comments
> > > > - Use V3 register offsets
> > > > Changes in v4:
> > > > - Use qmp_usb_offsets for register space access
> > > > Changes in v3:
> > > > - Fix hex captitalization
> > > > Changes in v2:
> > > > - Removed unused phy register offsets
> > > > - Moved the clock entries to the correct place
> > > > - Maintain sorted order
> > > > ---
> > > > drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 115 ++++++++++++++++++++++++++++++++
> > > > 1 file changed, 115 insertions(+)
> > > >
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > > > index a49711c..77041dd 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
> > > > @@ -139,6 +139,88 @@ static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
> > > > [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
> > > > };
> > > >
> > > > +static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
> > > > + /* PLL and Loop filter settings */
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> > > > + /* SSC settings */
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
> > > > + QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> > > > + QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> > > > + QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> > > > + QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
> > > > +};
> > > > +
> > > > +static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
> > > > + QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
> > > > +};
> > > > +
> > > > static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
> > > > QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
> > > > QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> > > > @@ -1558,6 +1640,14 @@ static const char * const qmp_phy_vreg_l[] = {
> > > > "vdda-phy", "vdda-pll",
> > > > };
> > > >
> > > > +static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
> > > > + .serdes = 0,
> > > > + .pcs = 0x800,
> > > > + .pcs_usb = 0,
> > >
> > > No, pcs_usb is not 0.
> >
> > Not sure I understand this comment.
> >
> > Since IPQ9574 uses new style DT entries, pcs_usb_offset = 0 and
> > that will not be used.
> >
> > qmp->pcs_usb is used in qmp_usb_enable_autonomous_mode and
> > qmp_usb_disable_autonomous_mode. If "qmp->pcs_usb == 0", those
> > functions use the value of qmp->pcs (0x7d800) for pcs_usb.
>
> So, you mixed qmp->pcs_usb and offsets->pcs_usb here. They are not equal.
Got it. Thanks.
Will set pcs_usb to 0x800, that way the register offsets will get
calculated properly.
Thanks
Varada
> > The registers used in these functions are
> > QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR & QPHY_PCS_AUTONOMOUS_MODE_CTRL
> >
> > The offsets for the above registers as specified in
> > qmp_v3_usb3phy_regs_layout is
> >
> > #define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL 0x0d8
> > #define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0dc
> >
> > qphy_{set|clr}bits called from qmp_usb_enable_autonomous_mode and
> > qmp_usb_disable_autonomous_mode will use the offset 0x7d8d8 and
> > 0x78d8c. This offset matches with the register offset document of
> > the IPQ9574. So, felt setting pcs_usb to zero should be ok. Can
> > you please clarify.
>
> And this tells you what pcs_usb offset is.
>
> >
> > Thanks
> > Varada
> >
> >
> > >
> > > > + .tx = 0x200,
> > > > + .rx = 0x400,
> > > > +};
> > > > +
> > > > static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
> > > > .serdes = 0,
> > > > .pcs = 0x0200,
> > > > @@ -1586,6 +1676,28 @@ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
> > > > .regs = qmp_v3_usb3phy_regs_layout,
> > > > };
> > > >
> > > > +static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
> > > > + .lanes = 1,
> > > > +
> > > > + .offsets = &qmp_usb_offsets_ipq9574,
> > > > +
> > > > + .serdes_tbl = ipq9574_usb3_serdes_tbl,
> > > > + .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
> > > > + .tx_tbl = ipq9574_usb3_tx_tbl,
> > > > + .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
> > > > + .rx_tbl = ipq9574_usb3_rx_tbl,
> > > > + .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
> > > > + .pcs_tbl = ipq9574_usb3_pcs_tbl,
> > > > + .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
> > > > + .clk_list = qmp_v4_phy_clk_l,
> > > > + .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l),
> > > > + .reset_list = qcm2290_usb3phy_reset_l,
> > > > + .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
> > > > + .vreg_list = qmp_phy_vreg_l,
> > > > + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> > > > + .regs = qmp_v3_usb3phy_regs_layout,
> > > > +};
> > > > +
> > > > static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
> > > > .lanes = 1,
> > > >
> > > > @@ -2589,6 +2701,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
> > > > .compatible = "qcom,ipq8074-qmp-usb3-phy",
> > > > .data = &ipq8074_usb3phy_cfg,
> > > > }, {
> > > > + .compatible = "qcom,ipq9574-qmp-usb3-phy",
> > > > + .data = &ipq9574_usb3phy_cfg,
> > > > + }, {
> > > > .compatible = "qcom,msm8996-qmp-usb3-phy",
> > > > .data = &msm8996_usb3phy_cfg,
> > > > }, {
> > > > --
> > > > 2.7.4
> > > >
> > >
> > >
> > > --
> > > With best wishes
> > > Dmitry
>
>
>
> --
> With best wishes
> Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes
2023-03-30 8:40 [PATCH v5 0/8] Enable IPQ9754 USB Varadarajan Narayanan
` (5 preceding siblings ...)
2023-03-30 8:40 ` [PATCH v5 6/8] phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence Varadarajan Narayanan
@ 2023-03-30 8:40 ` Varadarajan Narayanan
2023-03-30 9:44 ` Dmitry Baryshkov
2023-03-30 8:40 ` [PATCH v5 8/8] arm64: dts: qcom: ipq9574: Enable USB Varadarajan Narayanan
7 siblings, 1 reply; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-30 8:40 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
Cc: Varadarajan Narayanan
Add USB phy and controller related nodes
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Changes in v5:
- Fix additional comments
- Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
- 'make dtbs_check' giving the following messages since
ipq9574 doesn't have power domains. Hope this is ok
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
/local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
Changes in v4:
- Use newer bindings without subnodes
- Fix coding style issues
Changes in v3:
- Insert the nodes at proper location
Changes in v2:
- Fixed issues flagged by Krzysztof
- Fix issues reported by make dtbs_check
- Remove NOC related clocks (to be added with proper
interconnect support)
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
arch/arm64/boot/dts/qcom/ipq9574.dtsi | 120 ++++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 2bb4053..8fa9e1a 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -186,6 +186,33 @@
method = "smc";
};
+ reg_usb_3p3: s3300 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "usb-phy-vdd-dummy";
+ };
+
+ reg_usb_1p8: s1800 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "usb-phy-pll-dummy";
+ };
+
+ reg_usb_0p925: s0925 {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <925000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-name = "usb-phy-dummy";
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -215,6 +242,52 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ qusb_phy_0: phy@7b000 {
+ compatible = "qcom,ipq9574-qusb2-phy";
+ reg = <0x0007b000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&xo_board_clk>;
+ clock-names = "cfg_ahb",
+ "ref";
+
+ vdd-supply = <®_usb_0p925>;
+ vdda-pll-supply = <®_usb_1p8>;
+ vdda-phy-dpdm-supply = <®_usb_3p3>;
+
+ resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: phy@7d000 {
+ compatible = "qcom,ipq9574-qmp-usb3-phy";
+ reg = <0x0007d000 0xa00>;
+ #phy-cells = <0>;
+
+ clocks = <&gcc GCC_USB0_AUX_CLK>,
+ <&xo_board_clk>,
+ <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB0_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "pipe";
+
+ resets = <&gcc GCC_USB0_PHY_BCR>,
+ <&gcc GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy",
+ "phy_phy";
+
+ vdda-pll-supply = <®_usb_1p8>;
+ vdda-phy-supply = <®_usb_0p925>;
+
+ status = "disabled";
+
+ #clock-cells = <0>;
+ clock-output-names = "usb0_pipe_clk";
+ };
+
pcie0_phy: phy@84000 {
compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
reg = <0x00084000 0x1bc>; /* Serdes PLL */
@@ -436,6 +509,53 @@
status = "disabled";
};
+ usb3: usb@8a00000 {
+ compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
+ reg = <0x08af8800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = <&gcc GCC_SNOC_USB_CLK>,
+ <&gcc GCC_ANOC_USB_AXI_CLK>,
+ <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_SLEEP_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+
+ clock-names = "sys_noc_axi",
+ "anoc_axi",
+ "master",
+ "sleep",
+ "mock_utmi";
+
+ assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
+ <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ assigned-clock-rates = <200000000>,
+ <24000000>;
+
+ interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event";
+
+ resets = <&gcc GCC_USB_BCR>;
+ status = "disabled";
+
+ dwc_0: usb@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xcd00>;
+ clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
+ clock-names = "ref";
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&qusb_phy_0>, <&ssphy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ tx-fifo-resize;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ dr_mode = "host";
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
--
2.7.4
--
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^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes
2023-03-30 8:40 ` [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes Varadarajan Narayanan
@ 2023-03-30 9:44 ` Dmitry Baryshkov
2023-03-31 9:27 ` Varadarajan Narayanan
0 siblings, 1 reply; 20+ messages in thread
From: Dmitry Baryshkov @ 2023-03-30 9:44 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
<quic_varada@quicinc.com> wrote:
>
> Add USB phy and controller related nodes
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> Changes in v5:
> - Fix additional comments
> - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> - 'make dtbs_check' giving the following messages since
> ipq9574 doesn't have power domains. Hope this is ok
>
> /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
> From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
> From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
No, I think it is not.
>
>
> Changes in v4:
> - Use newer bindings without subnodes
> - Fix coding style issues
>
> Changes in v3:
> - Insert the nodes at proper location
>
> Changes in v2:
> - Fixed issues flagged by Krzysztof
> - Fix issues reported by make dtbs_check
> - Remove NOC related clocks (to be added with proper
> interconnect support)
>
> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 120 ++++++++++++++++++++++++++++++++++
> 1 file changed, 120 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> index 2bb4053..8fa9e1a 100644
> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -186,6 +186,33 @@
> method = "smc";
> };
>
> + reg_usb_3p3: s3300 {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-name = "usb-phy-vdd-dummy";
> + };
> +
> + reg_usb_1p8: s1800 {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-name = "usb-phy-pll-dummy";
> + };
> +
> + reg_usb_0p925: s0925 {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <925000>;
> + regulator-max-microvolt = <925000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-name = "usb-phy-dummy";
> + };
> +
> reserved-memory {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -215,6 +242,52 @@
> #size-cells = <1>;
> ranges = <0 0 0 0xffffffff>;
>
> + qusb_phy_0: phy@7b000 {
> + compatible = "qcom,ipq9574-qusb2-phy";
> + reg = <0x0007b000 0x180>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&xo_board_clk>;
> + clock-names = "cfg_ahb",
> + "ref";
> +
> + vdd-supply = <®_usb_0p925>;
> + vdda-pll-supply = <®_usb_1p8>;
> + vdda-phy-dpdm-supply = <®_usb_3p3>;
> +
> + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> + status = "disabled";
> + };
> +
> + ssphy_0: phy@7d000 {
Nit: usually the label usb_0_qmpphy
> + compatible = "qcom,ipq9574-qmp-usb3-phy";
> + reg = <0x0007d000 0xa00>;
> + #phy-cells = <0>;
> +
> + clocks = <&gcc GCC_USB0_AUX_CLK>,
> + <&xo_board_clk>,
> + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> + <&gcc GCC_USB0_PIPE_CLK>;
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "pipe";
> +
> + resets = <&gcc GCC_USB0_PHY_BCR>,
> + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> + reset-names = "phy",
> + "phy_phy";
> +
> + vdda-pll-supply = <®_usb_1p8>;
> + vdda-phy-supply = <®_usb_0p925>;
> +
> + status = "disabled";
> +
> + #clock-cells = <0>;
> + clock-output-names = "usb0_pipe_clk";
> + };
> +
> pcie0_phy: phy@84000 {
> compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> reg = <0x00084000 0x1bc>; /* Serdes PLL */
> @@ -436,6 +509,53 @@
> status = "disabled";
> };
>
> + usb3: usb@8a00000 {
> + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> + reg = <0x08af8800 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + clocks = <&gcc GCC_SNOC_USB_CLK>,
> + <&gcc GCC_ANOC_USB_AXI_CLK>,
> + <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_SLEEP_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> +
> + clock-names = "sys_noc_axi",
> + "anoc_axi",
> + "master",
> + "sleep",
> + "mock_utmi";
> +
> + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + assigned-clock-rates = <200000000>,
> + <24000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pwr_event";
> +
> + resets = <&gcc GCC_USB_BCR>;
> + status = "disabled";
> +
> + dwc_0: usb@8a00000 {
> + compatible = "snps,dwc3";
> + reg = <0x8a00000 0xcd00>;
> + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> + clock-names = "ref";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&qusb_phy_0>, <&ssphy_0>;
> + phy-names = "usb2-phy", "usb3-phy";
> + tx-fifo-resize;
> + snps,is-utmi-l1-suspend;
> + snps,hird-threshold = /bits/ 8 <0x0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_u3_susphy_quirk;
> + dr_mode = "host";
> + };
> + };
> +
> intc: interrupt-controller@b000000 {
> compatible = "qcom,msm-qgic2";
> reg = <0x0b000000 0x1000>, /* GICD */
> --
> 2.7.4
>
--
With best wishes
Dmitry
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes
2023-03-30 9:44 ` Dmitry Baryshkov
@ 2023-03-31 9:27 ` Varadarajan Narayanan
2023-03-31 10:19 ` Johan Hovold
0 siblings, 1 reply; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-31 9:27 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
On Thu, Mar 30, 2023 at 12:44:40PM +0300, Dmitry Baryshkov wrote:
> On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
> <quic_varada@quicinc.com> wrote:
> >
> > Add USB phy and controller related nodes
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > Changes in v5:
> > - Fix additional comments
> > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > - 'make dtbs_check' giving the following messages since
> > ipq9574 doesn't have power domains. Hope this is ok
> >
> > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
> > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
> > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>
> No, I think it is not.
There are no GDSCs in IPQ9574. Can you suggest how to proceed.
Thanks
Varada
> > Changes in v4:
> > - Use newer bindings without subnodes
> > - Fix coding style issues
> >
> > Changes in v3:
> > - Insert the nodes at proper location
> >
> > Changes in v2:
> > - Fixed issues flagged by Krzysztof
> > - Fix issues reported by make dtbs_check
> > - Remove NOC related clocks (to be added with proper
> > interconnect support)
> >
> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > ---
> > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 120 ++++++++++++++++++++++++++++++++++
> > 1 file changed, 120 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > index 2bb4053..8fa9e1a 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> > @@ -186,6 +186,33 @@
> > method = "smc";
> > };
> >
> > + reg_usb_3p3: s3300 {
> > + compatible = "regulator-fixed";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-name = "usb-phy-vdd-dummy";
> > + };
> > +
> > + reg_usb_1p8: s1800 {
> > + compatible = "regulator-fixed";
> > + regulator-min-microvolt = <1800000>;
> > + regulator-max-microvolt = <1800000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-name = "usb-phy-pll-dummy";
> > + };
> > +
> > + reg_usb_0p925: s0925 {
> > + compatible = "regulator-fixed";
> > + regulator-min-microvolt = <925000>;
> > + regulator-max-microvolt = <925000>;
> > + regulator-boot-on;
> > + regulator-always-on;
> > + regulator-name = "usb-phy-dummy";
> > + };
> > +
> > reserved-memory {
> > #address-cells = <2>;
> > #size-cells = <2>;
> > @@ -215,6 +242,52 @@
> > #size-cells = <1>;
> > ranges = <0 0 0 0xffffffff>;
> >
> > + qusb_phy_0: phy@7b000 {
> > + compatible = "qcom,ipq9574-qusb2-phy";
> > + reg = <0x0007b000 0x180>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > + <&xo_board_clk>;
> > + clock-names = "cfg_ahb",
> > + "ref";
> > +
> > + vdd-supply = <®_usb_0p925>;
> > + vdda-pll-supply = <®_usb_1p8>;
> > + vdda-phy-dpdm-supply = <®_usb_3p3>;
> > +
> > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
> > + status = "disabled";
> > + };
> > +
> > + ssphy_0: phy@7d000 {
>
> Nit: usually the label usb_0_qmpphy
>
> > + compatible = "qcom,ipq9574-qmp-usb3-phy";
> > + reg = <0x0007d000 0xa00>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&gcc GCC_USB0_AUX_CLK>,
> > + <&xo_board_clk>,
> > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > + <&gcc GCC_USB0_PIPE_CLK>;
> > + clock-names = "aux",
> > + "ref",
> > + "com_aux",
> > + "pipe";
> > +
> > + resets = <&gcc GCC_USB0_PHY_BCR>,
> > + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > + reset-names = "phy",
> > + "phy_phy";
> > +
> > + vdda-pll-supply = <®_usb_1p8>;
> > + vdda-phy-supply = <®_usb_0p925>;
> > +
> > + status = "disabled";
> > +
> > + #clock-cells = <0>;
> > + clock-output-names = "usb0_pipe_clk";
> > + };
> > +
> > pcie0_phy: phy@84000 {
> > compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy";
> > reg = <0x00084000 0x1bc>; /* Serdes PLL */
> > @@ -436,6 +509,53 @@
> > status = "disabled";
> > };
> >
> > + usb3: usb@8a00000 {
> > + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
> > + reg = <0x08af8800 0x400>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + clocks = <&gcc GCC_SNOC_USB_CLK>,
> > + <&gcc GCC_ANOC_USB_AXI_CLK>,
> > + <&gcc GCC_USB0_MASTER_CLK>,
> > + <&gcc GCC_USB0_SLEEP_CLK>,
> > + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > +
> > + clock-names = "sys_noc_axi",
> > + "anoc_axi",
> > + "master",
> > + "sleep",
> > + "mock_utmi";
> > +
> > + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
> > + <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > + assigned-clock-rates = <200000000>,
> > + <24000000>;
> > +
> > + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "pwr_event";
> > +
> > + resets = <&gcc GCC_USB_BCR>;
> > + status = "disabled";
> > +
> > + dwc_0: usb@8a00000 {
> > + compatible = "snps,dwc3";
> > + reg = <0x8a00000 0xcd00>;
> > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>;
> > + clock-names = "ref";
> > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> > + phys = <&qusb_phy_0>, <&ssphy_0>;
> > + phy-names = "usb2-phy", "usb3-phy";
> > + tx-fifo-resize;
> > + snps,is-utmi-l1-suspend;
> > + snps,hird-threshold = /bits/ 8 <0x0>;
> > + snps,dis_u2_susphy_quirk;
> > + snps,dis_u3_susphy_quirk;
> > + dr_mode = "host";
> > + };
> > + };
> > +
> > intc: interrupt-controller@b000000 {
> > compatible = "qcom,msm-qgic2";
> > reg = <0x0b000000 0x1000>, /* GICD */
> > --
> > 2.7.4
> >
>
>
> --
> With best wishes
> Dmitry
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes
2023-03-31 9:27 ` Varadarajan Narayanan
@ 2023-03-31 10:19 ` Johan Hovold
2023-04-05 8:58 ` Varadarajan Narayanan
0 siblings, 1 reply; 20+ messages in thread
From: Johan Hovold @ 2023-03-31 10:19 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: Dmitry Baryshkov, agross, andersson, konrad.dybcio, vkoul,
kishon, robh+dt, krzysztof.kozlowski+dt, gregkh, mturquette,
sboyd, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb, linux-clk
On Fri, Mar 31, 2023 at 02:57:11PM +0530, Varadarajan Narayanan wrote:
> On Thu, Mar 30, 2023 at 12:44:40PM +0300, Dmitry Baryshkov wrote:
> > On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
> > <quic_varada@quicinc.com> wrote:
> > >
> > > Add USB phy and controller related nodes
> > >
> > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > ---
> > > Changes in v5:
> > > - Fix additional comments
> > > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > > - 'make dtbs_check' giving the following messages since
> > > ipq9574 doesn't have power domains. Hope this is ok
> > >
> > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
> > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
> > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> >
> > No, I think it is not.
>
> There are no GDSCs in IPQ9574. Can you suggest how to proceed.
You need to update the binding and either make the power domains
property optional in the binding or dependent on the SoC.
> > > + ssphy_0: phy@7d000 {
> >
> > Nit: usually the label usb_0_qmpphy
> >
> > > + compatible = "qcom,ipq9574-qmp-usb3-phy";
> > > + reg = <0x0007d000 0xa00>;
> > > + #phy-cells = <0>;
> > > +
> > > + clocks = <&gcc GCC_USB0_AUX_CLK>,
> > > + <&xo_board_clk>,
> > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > > + <&gcc GCC_USB0_PIPE_CLK>;
> > > + clock-names = "aux",
> > > + "ref",
> > > + "com_aux",
This is not the right name for this clock so you need to update the
binding first.
Please be more careful.
> > > + "pipe";
> > > +
> > > + resets = <&gcc GCC_USB0_PHY_BCR>,
> > > + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > > + reset-names = "phy",
> > > + "phy_phy";
> > > +
> > > + vdda-pll-supply = <®_usb_1p8>;
> > > + vdda-phy-supply = <®_usb_0p925>;
> > > +
> > > + status = "disabled";
> > > +
> > > + #clock-cells = <0>;
> > > + clock-output-names = "usb0_pipe_clk";
> > > + };
Johan
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes
2023-03-31 10:19 ` Johan Hovold
@ 2023-04-05 8:58 ` Varadarajan Narayanan
2023-04-05 9:11 ` Johan Hovold
0 siblings, 1 reply; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-04-05 8:58 UTC (permalink / raw)
To: Johan Hovold
Cc: Dmitry Baryshkov, agross, andersson, konrad.dybcio, vkoul,
kishon, robh+dt, krzysztof.kozlowski+dt, gregkh, mturquette,
sboyd, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb, linux-clk
On Fri, Mar 31, 2023 at 12:19:10PM +0200, Johan Hovold wrote:
> On Fri, Mar 31, 2023 at 02:57:11PM +0530, Varadarajan Narayanan wrote:
> > On Thu, Mar 30, 2023 at 12:44:40PM +0300, Dmitry Baryshkov wrote:
> > > On Thu, 30 Mar 2023 at 11:42, Varadarajan Narayanan
> > > <quic_varada@quicinc.com> wrote:
> > > >
> > > > Add USB phy and controller related nodes
> > > >
> > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
> > > > ---
> > > > Changes in v5:
> > > > - Fix additional comments
> > > > - Edit nodes to match with qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > > > - 'make dtbs_check' giving the following messages since
> > > > ipq9574 doesn't have power domains. Hope this is ok
> > > >
> > > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: phy@7d000: 'power-domains' is a required property
> > > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
> > > > /local/mnt/workspace/varada/varda-linux/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dtb: usb@8a00000: 'power-domains' is a required property
> > > > From schema: /local/mnt/workspace/varada/varda-linux/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
> > >
> > > No, I think it is not.
> >
> > There are no GDSCs in IPQ9574. Can you suggest how to proceed.
>
> You need to update the binding and either make the power domains
> property optional in the binding or dependent on the SoC.
>
> > > > + ssphy_0: phy@7d000 {
> > >
> > > Nit: usually the label usb_0_qmpphy
> > >
> > > > + compatible = "qcom,ipq9574-qmp-usb3-phy";
> > > > + reg = <0x0007d000 0xa00>;
> > > > + #phy-cells = <0>;
> > > > +
> > > > + clocks = <&gcc GCC_USB0_AUX_CLK>,
> > > > + <&xo_board_clk>,
> > > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > > > + <&gcc GCC_USB0_PIPE_CLK>;
> > > > + clock-names = "aux",
> > > > + "ref",
> > > > + "com_aux",
>
> This is not the right name for this clock so you need to update the
> binding first.
>
> Please be more careful.
Thanks for your feedback. Have posted v6 with the above corrections.
-Varada
>
> > > > + "pipe";
> > > > +
> > > > + resets = <&gcc GCC_USB0_PHY_BCR>,
> > > > + <&gcc GCC_USB3PHY_0_PHY_BCR>;
> > > > + reset-names = "phy",
> > > > + "phy_phy";
> > > > +
> > > > + vdda-pll-supply = <®_usb_1p8>;
> > > > + vdda-phy-supply = <®_usb_0p925>;
> > > > +
> > > > + status = "disabled";
> > > > +
> > > > + #clock-cells = <0>;
> > > > + clock-output-names = "usb0_pipe_clk";
> > > > + };
>
> Johan
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes
2023-04-05 8:58 ` Varadarajan Narayanan
@ 2023-04-05 9:11 ` Johan Hovold
0 siblings, 0 replies; 20+ messages in thread
From: Johan Hovold @ 2023-04-05 9:11 UTC (permalink / raw)
To: Varadarajan Narayanan
Cc: Dmitry Baryshkov, agross, andersson, konrad.dybcio, vkoul,
kishon, robh+dt, krzysztof.kozlowski+dt, gregkh, mturquette,
sboyd, quic_wcheng, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-usb, linux-clk
On Wed, Apr 05, 2023 at 02:28:32PM +0530, Varadarajan Narayanan wrote:
> On Fri, Mar 31, 2023 at 12:19:10PM +0200, Johan Hovold wrote:
> > > > > + ssphy_0: phy@7d000 {
> > > >
> > > > Nit: usually the label usb_0_qmpphy
> > > >
> > > > > + compatible = "qcom,ipq9574-qmp-usb3-phy";
> > > > > + reg = <0x0007d000 0xa00>;
> > > > > + #phy-cells = <0>;
> > > > > +
> > > > > + clocks = <&gcc GCC_USB0_AUX_CLK>,
> > > > > + <&xo_board_clk>,
> > > > > + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>,
> > > > > + <&gcc GCC_USB0_PIPE_CLK>;
> > > > > + clock-names = "aux",
> > > > > + "ref",
> > > > > + "com_aux",
> >
> > This is not the right name for this clock so you need to update the
> > binding first.
> >
> > Please be more careful.
>
> Thanks for your feedback. Have posted v6 with the above corrections.
Thanks for the heads up. But for future submission, please try to
remember to add people that have provided feedback on CC when posting
new revisions.
Johan
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v5 8/8] arm64: dts: qcom: ipq9574: Enable USB
2023-03-30 8:40 [PATCH v5 0/8] Enable IPQ9754 USB Varadarajan Narayanan
` (6 preceding siblings ...)
2023-03-30 8:40 ` [PATCH v5 7/8] arm64: dts: qcom: ipq9574: Add USB related nodes Varadarajan Narayanan
@ 2023-03-30 8:40 ` Varadarajan Narayanan
7 siblings, 0 replies; 20+ messages in thread
From: Varadarajan Narayanan @ 2023-03-30 8:40 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon, robh+dt,
krzysztof.kozlowski+dt, gregkh, mturquette, sboyd, quic_wcheng,
linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-usb,
linux-clk
Cc: Varadarajan Narayanan
Turn on USB related nodes
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
---
Changes in v5:
- Move "host" mode specification to board dts
Changes in v2:
- Fix node placement and coding style
- "ok" -> "okay"
---
arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
index 8a6caae..387bda4 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
+++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
@@ -30,6 +30,10 @@
status = "okay";
};
+&dwc_0 {
+ dr_mode = "host";
+};
+
&pcie1_phy {
status = "okay";
};
@@ -57,6 +61,10 @@
status = "okay";
};
+&qusb_phy_0 {
+ status = "okay";
+};
+
&rpm_requests {
regulators {
compatible = "qcom,rpm-mp5496-regulators";
@@ -84,6 +92,10 @@
clock-frequency = <32000>;
};
+&ssphy_0 {
+ status = "okay";
+};
+
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
@@ -118,6 +130,10 @@
};
};
+&usb3 {
+ status = "okay";
+};
+
&xo_board_clk {
clock-frequency = <24000000>;
};
--
2.7.4
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^ permalink raw reply related [flat|nested] 20+ messages in thread