From: Chanwoo Choi <cw00.choi@samsung.com>
To: Leonard Crestez <leonard.crestez@nxp.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>
Cc: "MyungJoo Ham" <myungjoo.ham@samsung.com>,
"Kyungmin Park" <kyungmin.park@samsung.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
"Shawn Guo" <shawnguo@kernel.org>,
"Mark Rutland" <mark.rutland@arm.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Artur Świgoń" <a.swigon@partner.samsung.com>,
"Saravana Kannan" <saravanak@google.com>,
"Angus Ainslie" <angus@akkea.ca>,
"Martin Kepplinger" <martink@posteo.de>,
"Matthias Kaehlcke" <mka@chromium.org>,
"Krzysztof Kozlowski" <krzk@kernel.org>,
"Alexandre Bailon" <abailon@baylibre.com>,
"Georgi Djakov" <georgi.djakov@linaro.org>,
"Dong Aisheng" <aisheng.dong@nxp.com>,
"Abel Vesa" <abel.vesa@nxp.com>, "Jacky Bai" <ping.bai@nxp.com>,
"Anson Huang" <Anson.Huang@nxp.com>,
"Fabio Estevam" <fabio.estevam@nxp.com>,
"Viresh Kumar" <viresh.kumar@linaro.org>,
"Silvano di Ninno" <silvano.dininno@nxp.com>,
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
linux-clk@vger.kernel.org, linux-imx@nxp.com,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 3/5] dt-bindings: memory: Add bindings for imx8m ddr controller
Date: Fri, 15 Nov 2019 14:23:22 +0900 [thread overview]
Message-ID: <08a89e18-ec63-79c3-e018-0cd2f3baad78@samsung.com> (raw)
In-Reply-To: <58f3aea574bf3a38a42075e313fc2a5592c96ed2.1573756360.git.leonard.crestez@nxp.com>
Hi Leonard,
On 11/15/19 3:33 AM, Leonard Crestez wrote:
> Add devicetree bindings for the i.MX DDR Controller on imx8m series
> chips. It supports dynamic frequency switching between multiple data
> rates and this is exposed to Linux via the devfreq subsystem.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
> .../memory-controllers/fsl/imx8m-ddrc.yaml | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
> new file mode 100644
> index 000000000000..c9e6c22cb5be
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/memory-controllers/fsl/imx8m-ddrc.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: https://protect2.fireeye.com/url?k=7d43eac6-20dfeba6-7d426189-0cc47a31307c-fcd69516893e0615&u=http://devicetree.org/schemas/memory-controllers/fsl/imx8m-ddrc.yaml#
> +$schema: https://protect2.fireeye.com/url?k=b9d87e43-e4447f23-b9d9f50c-0cc47a31307c-9fbd3b55b25cfa6d&u=http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: i.MX8M DDR Controller
> +
> +maintainers:
> + - Leonard Crestez <leonard.crestez@nxp.com>
> +
> +description:
> + The DDRC block is integrated in i.MX8M for interfacing with DDR based
> + memories.
> +
> + It supports switching between different frequencies at runtime but during
> + this process RAM itself becomes briefly inaccessible so actual frequency
> + switching is implemented by TF-A code which runs from a SRAM area.
> +
> + The Linux driver for the DDRC doesn't even map registers (they're included
> + for the sake of "describing hardware"), it mostly just exposes firmware
> + capabilities through standard Linux mechanism like devfreq and OPP tables.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,imx8mn-ddrc
> + - fsl,imx8mm-ddrc
> + - fsl,imx8mq-ddrc
> + - const: fsl,imx8m-ddrc
> +
> + reg:
> + maxItems: 1
> + description:
> + Base address and size of DDRC CTL area.
> + This is not currently mapped by the imx8m-ddrc driver.
> +
> + clocks:
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: core
> + - const: pll
> + - const: alt
> + - const: apb
> +
> + operating-points-v2: true
> + opp-table: true
> +
> +required:
> + - reg
> + - compatible
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8mm-clock.h>
> + ddrc: memory-controller@3d400000 {
> + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
> + reg = <0x3d400000 0x400000>;
> + clock-names = "core", "pll", "alt", "apb";
> + clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
> + <&clk IMX8MM_DRAM_PLL>,
> + <&clk IMX8MM_CLK_DRAM_ALT>,
> + <&clk IMX8MM_CLK_DRAM_APB>;
> + operating-points-v2 = <&ddrc_opp_table>;
> + };
>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
next prev parent reply other threads:[~2019-11-15 5:17 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-14 18:33 [PATCH v6 0/5] PM / devfreq: Add dynamic scaling for imx8m ddr controller Leonard Crestez
2019-11-14 18:33 ` [PATCH v6 1/5] clk: imx8m: Set CLK_GET_RATE_NOCACHE on dram clocks Leonard Crestez
2019-11-14 18:33 ` [PATCH v6 2/5] clk: imx: Mark dram pll on 8mm and 8mn with CLK_GET_RATE_NOCACHE Leonard Crestez
2019-11-14 18:33 ` [PATCH v6 3/5] dt-bindings: memory: Add bindings for imx8m ddr controller Leonard Crestez
2019-11-15 5:23 ` Chanwoo Choi [this message]
2019-11-21 21:00 ` Rob Herring
2019-11-14 18:33 ` [PATCH v6 4/5] PM / devfreq: Add dynamic scaling " Leonard Crestez
2019-11-15 1:31 ` Chanwoo Choi
2019-11-18 14:37 ` Leonard Crestez
2019-11-22 1:47 ` Chanwoo Choi
2019-11-14 18:33 ` [PATCH v6 5/5] arm64: dts: imx8m: Add ddr controller nodes Leonard Crestez
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