From: Rajendra Nayak <rnayak@codeaurora.org>
To: linux-kernel@vger.kernel.org
Cc: ulf.hansson@linaro.org, Rajendra Nayak <rnayak@codeaurora.org>,
linux-scsi@vger.kernel.org, linux-pm@vger.kernel.org,
linux-arm-msm@vger.kernel.org, rafael@kernel.org,
dianders@chromium.org, dri-devel@lists.freedesktop.org,
linux-spi@vger.kernel.org, linux-serial@vger.kernel.org,
viresh.kumar@linaro.org, swboyd@chromium.org
Subject: [RFC v2 09/11] drm/msm/dpu: Use OPP API to set clk/perf state
Date: Wed, 20 Mar 2019 15:19:16 +0530 [thread overview]
Message-ID: <20190320094918.20234-10-rnayak@codeaurora.org> (raw)
In-Reply-To: <20190320094918.20234-1-rnayak@codeaurora.org>
On some qualcomm platforms DPU needs to express a perforamnce state
requirement on a power domain depennding on the clock rates.
Use OPP table from DT to register with OPP framework and use
dev_pm_opp_set_rate() to set the clk/perf state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 7 ++++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 9 +++++++++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
index 9f20f397f77d..db21a86b242b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
@@ -15,6 +15,7 @@
#include <linux/debugfs.h>
#include <linux/errno.h>
#include <linux/mutex.h>
+#include <linux/pm_opp.h>
#include <linux/sort.h>
#include <linux/clk.h>
#include <linux/bitmap.h>
@@ -298,7 +299,11 @@ static int _dpu_core_perf_set_core_clk_rate(struct dpu_kms *kms, u64 rate)
rate = core_clk->max_rate;
core_clk->rate = rate;
- return msm_dss_clk_set_rate(core_clk, 1);
+
+ if (dev_pm_opp_get_opp_table(&kms->pdev->dev))
+ return dev_pm_opp_set_rate(&kms->pdev->dev, core_clk->rate);
+ else
+ return msm_dss_clk_set_rate(core_clk, 1);
}
static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 885bf88afa3e..684bd6982aaf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -22,6 +22,7 @@
#include <linux/debugfs.h>
#include <linux/of_irq.h>
#include <linux/dma-buf.h>
+#include <linux/pm_opp.h>
#include "msm_drv.h"
#include "msm_mmu.h"
@@ -1014,6 +1015,12 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
if (!dpu_kms)
return -ENOMEM;
+ dev_pm_opp_set_clkname(dev, "core");
+
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret)
+ dev_err(dev, "failed to init OPP table: %d\n", ret);
+
mp = &dpu_kms->mp;
ret = msm_dss_parse_clock(pdev, mp);
if (ret) {
@@ -1040,6 +1047,7 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data)
struct dpu_kms *dpu_kms = platform_get_drvdata(pdev);
struct dss_module_power *mp = &dpu_kms->mp;
+ dev_pm_opp_of_remove_table(dev);
msm_dss_put_clk(mp->clk_config, mp->num_clk);
devm_kfree(&pdev->dev, mp->clk_config);
mp->num_clk = 0;
@@ -1078,6 +1086,7 @@ static int __maybe_unused dpu_runtime_suspend(struct device *dev)
return rc;
}
+ dev_pm_opp_set_rate(dev, 0);
rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, false);
if (rc)
DPU_ERROR("clock disable failed rc:%d\n", rc);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
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next prev parent reply other threads:[~2019-03-20 9:49 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-20 9:49 [RFC v2 00/11] DVFS in the OPP core Rajendra Nayak
2019-03-20 9:49 ` [RFC v2 01/11] OPP: Don't overwrite rounded clk rate Rajendra Nayak
2019-06-11 10:54 ` Viresh Kumar
2019-06-12 7:42 ` Rajendra Nayak
2019-06-12 8:25 ` Viresh Kumar
2019-06-13 9:54 ` Viresh Kumar
2019-06-14 5:27 ` Viresh Kumar
2019-06-17 3:50 ` Viresh Kumar
2019-06-17 4:07 ` Rajendra Nayak
2019-06-17 4:17 ` Viresh Kumar
2019-06-17 4:25 ` Rajendra Nayak
2019-06-14 5:54 ` Rajendra Nayak
2019-03-20 9:49 ` [RFC v2 02/11] OPP: Make dev_pm_opp_set_rate() with freq=0 as valid Rajendra Nayak
2019-06-14 6:32 ` Viresh Kumar
2019-06-17 4:04 ` Rajendra Nayak
2019-03-20 9:49 ` [RFC v2 03/11] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state Rajendra Nayak
2020-08-11 23:11 ` John Stultz
2020-08-12 1:33 ` John Stultz
2020-08-12 5:48 ` Rajendra Nayak
2020-08-12 7:35 ` Amit Pundir
2020-08-12 7:39 ` Rajendra Nayak
2020-08-12 9:26 ` Rajendra Nayak
2019-03-20 9:49 ` [RFC v2 04/11] spi: spi-geni-qcom: " Rajendra Nayak
2019-03-20 9:49 ` [RFC v2 05/11] arm64: dts: sdm845: Add OPP table for all qup devices Rajendra Nayak
2019-03-20 9:49 ` [RFC v2 06/11] scsi: ufs: Add support to manage multiple power domains in ufshcd-pltfrm Rajendra Nayak
2019-03-20 9:49 ` [RFC v2 07/11] scsi: ufs: Add support for specifying OPP tables in DT Rajendra Nayak
2019-03-20 9:49 ` [RFC v2 08/11] arm64: dts: sdm845: Add ufs opps and power-domains Rajendra Nayak
2019-05-14 7:53 ` Ulf Hansson
2019-05-14 7:53 ` Ulf Hansson
2019-03-20 9:49 ` Rajendra Nayak [this message]
2019-04-10 3:49 ` [RFC v2 09/11] drm/msm/dpu: Use OPP API to set clk/perf state Viresh Kumar
2019-04-10 3:49 ` Viresh Kumar
2019-03-20 9:49 ` [RFC v2 10/11] drm/msm: dsi: " Rajendra Nayak
2019-03-20 9:49 ` [RFC v2 11/11] arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domains Rajendra Nayak
2019-04-10 3:51 ` [RFC v2 00/11] DVFS in the OPP core Viresh Kumar
2019-04-10 3:51 ` Viresh Kumar
2019-05-21 6:22 ` Viresh Kumar
2019-05-24 6:03 ` Rajendra Nayak
2019-06-17 4:26 ` Viresh Kumar
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