* [PATCH v7 00/12] x86: PIE support to extend KASLR randomization
@ 2019-05-20 23:19 Thomas Garnier
2019-05-20 23:19 ` [PATCH v7 08/12] x86/acpi: Adapt assembly for PIE support Thomas Garnier
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Thomas Garnier @ 2019-05-20 23:19 UTC (permalink / raw)
To: kernel-hardening
Cc: kristen, Herbert Xu, David S. Miller, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, H. Peter Anvin, x86,
Andy Lutomirski, Juergen Gross, Alok Kataria, Rafael J. Wysocki,
Len Brown, Pavel Machek, Peter Zijlstra, Thomas Garnier,
Nadav Amit, Jann Horn, Ard Biesheuvel, Masahiro Yamada,
Andi Kleen, Andrew Morton, Feng Tang, Jan Beulich, Maran Wilson,
linux-crypto, linux-kernel, virtualization, linux-pm
Splitting the previous serie in two. This part contains assembly code
changes required for PIE but without any direct dependencies with the
rest of the patchset.
Changes:
- patch v7 (assembly):
- Split patchset and reorder changes.
- patch v6:
- Rebase on latest changes in jump tables and crypto.
- Fix wording on couple commits.
- Revisit checkpatch warnings.
- Moving to @chromium.org.
- patch v5:
- Adapt new crypto modules for PIE.
- Improve per-cpu commit message.
- Fix xen 32-bit build error with .quad.
- Remove extra code for ftrace.
- patch v4:
- Simplify early boot by removing global variables.
- Modify the mcount location script for __mcount_loc intead of the address
read in the ftrace implementation.
- Edit commit description to explain better where the kernel can be located.
- Streamlined the testing done on each patch proposal. Always testing
hibernation, suspend, ftrace and kprobe to ensure no regressions.
- patch v3:
- Update on message to describe longer term PIE goal.
- Minor change on ftrace if condition.
- Changed code using xchgq.
- patch v2:
- Adapt patch to work post KPTI and compiler changes
- Redo all performance testing with latest configs and compilers
- Simplify mov macro on PIE (MOVABS now)
- Reduce GOT footprint
- patch v1:
- Simplify ftrace implementation.
- Use gcc mstack-protector-guard-reg=%gs with PIE when possible.
- rfc v3:
- Use --emit-relocs instead of -pie to reduce dynamic relocation space on
mapped memory. It also simplifies the relocation process.
- Move the start the module section next to the kernel. Remove the need for
-mcmodel=large on modules. Extends module space from 1 to 2G maximum.
- Support for XEN PVH as 32-bit relocations can be ignored with
--emit-relocs.
- Support for GOT relocations previously done automatically with -pie.
- Remove need for dynamic PLT in modules.
- Support dymamic GOT for modules.
- rfc v2:
- Add support for global stack cookie while compiler default to fs without
mcmodel=kernel
- Change patch 7 to correctly jump out of the identity mapping on kexec load
preserve.
These patches make some of the changes necessary to build the kernel as
Position Independent Executable (PIE) on x86_64. Another patchset will
add the PIE option and larger architecture changes.
The patches:
- 1-2, 4-12: Change in assembly code to be PIE compliant.
- 3: Add a new _ASM_MOVABS macro to fetch a symbol address generically.
diffstat:
crypto/aegis128-aesni-asm.S | 6 +-
crypto/aegis128l-aesni-asm.S | 8 +--
crypto/aegis256-aesni-asm.S | 6 +-
crypto/aes-x86_64-asm_64.S | 45 ++++++++++------
crypto/aesni-intel_asm.S | 8 +--
crypto/camellia-aesni-avx-asm_64.S | 42 +++++++--------
crypto/camellia-aesni-avx2-asm_64.S | 44 ++++++++--------
crypto/camellia-x86_64-asm_64.S | 8 +--
crypto/cast5-avx-x86_64-asm_64.S | 50 ++++++++++--------
crypto/cast6-avx-x86_64-asm_64.S | 44 +++++++++-------
crypto/des3_ede-asm_64.S | 96 ++++++++++++++++++++++++------------
crypto/ghash-clmulni-intel_asm.S | 4 -
crypto/glue_helper-asm-avx.S | 4 -
crypto/glue_helper-asm-avx2.S | 6 +-
crypto/morus1280-avx2-asm.S | 4 -
crypto/morus1280-sse2-asm.S | 8 +--
crypto/morus640-sse2-asm.S | 6 +-
crypto/sha256-avx2-asm.S | 23 +++++---
entry/entry_64.S | 16 ++++--
include/asm/alternative.h | 6 +-
include/asm/asm.h | 1
include/asm/jump_label.h | 8 +--
include/asm/paravirt_types.h | 12 +++-
include/asm/pm-trace.h | 2
include/asm/processor.h | 6 +-
kernel/acpi/wakeup_64.S | 31 ++++++-----
kernel/head_64.S | 16 +++---
kernel/relocate_kernel_64.S | 2
power/hibernate_asm_64.S | 4 -
29 files changed, 299 insertions(+), 217 deletions(-)
Patchset is based on next-20190515.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v7 08/12] x86/acpi: Adapt assembly for PIE support
2019-05-20 23:19 [PATCH v7 00/12] x86: PIE support to extend KASLR randomization Thomas Garnier
@ 2019-05-20 23:19 ` Thomas Garnier
2019-06-10 23:52 ` Kees Cook
2019-05-20 23:19 ` [PATCH v7 10/12] x86/power/64: " Thomas Garnier
2019-06-10 21:32 ` [PATCH v7 00/12] x86: PIE support to extend KASLR randomization Kees Cook
2 siblings, 1 reply; 6+ messages in thread
From: Thomas Garnier @ 2019-05-20 23:19 UTC (permalink / raw)
To: kernel-hardening
Cc: kristen, Thomas Garnier, Pavel Machek, Rafael J . Wysocki,
Rafael J. Wysocki, Len Brown, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, H. Peter Anvin, x86, linux-pm, linux-kernel
From: Thomas Garnier <thgarnie@google.com>
Change the assembly code to use only relative references of symbols for the
kernel to be PIE compatible.
Position Independent Executable (PIE) support will allow to extend the
KASLR randomization range below 0xffffffff80000000.
Signed-off-by: Thomas Garnier <thgarnie@google.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
arch/x86/kernel/acpi/wakeup_64.S | 31 ++++++++++++++++---------------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S
index 510fa12aab73..e080e943e295 100644
--- a/arch/x86/kernel/acpi/wakeup_64.S
+++ b/arch/x86/kernel/acpi/wakeup_64.S
@@ -14,7 +14,7 @@
* Hooray, we are in Long 64-bit mode (but still running in low memory)
*/
ENTRY(wakeup_long64)
- movq saved_magic, %rax
+ movq saved_magic(%rip), %rax
movq $0x123456789abcdef0, %rdx
cmpq %rdx, %rax
jne bogus_64_magic
@@ -25,14 +25,14 @@ ENTRY(wakeup_long64)
movw %ax, %es
movw %ax, %fs
movw %ax, %gs
- movq saved_rsp, %rsp
+ movq saved_rsp(%rip), %rsp
- movq saved_rbx, %rbx
- movq saved_rdi, %rdi
- movq saved_rsi, %rsi
- movq saved_rbp, %rbp
+ movq saved_rbx(%rip), %rbx
+ movq saved_rdi(%rip), %rdi
+ movq saved_rsi(%rip), %rsi
+ movq saved_rbp(%rip), %rbp
- movq saved_rip, %rax
+ movq saved_rip(%rip), %rax
jmp *%rax
ENDPROC(wakeup_long64)
@@ -45,7 +45,7 @@ ENTRY(do_suspend_lowlevel)
xorl %eax, %eax
call save_processor_state
- movq $saved_context, %rax
+ leaq saved_context(%rip), %rax
movq %rsp, pt_regs_sp(%rax)
movq %rbp, pt_regs_bp(%rax)
movq %rsi, pt_regs_si(%rax)
@@ -64,13 +64,14 @@ ENTRY(do_suspend_lowlevel)
pushfq
popq pt_regs_flags(%rax)
- movq $.Lresume_point, saved_rip(%rip)
+ leaq .Lresume_point(%rip), %rax
+ movq %rax, saved_rip(%rip)
- movq %rsp, saved_rsp
- movq %rbp, saved_rbp
- movq %rbx, saved_rbx
- movq %rdi, saved_rdi
- movq %rsi, saved_rsi
+ movq %rsp, saved_rsp(%rip)
+ movq %rbp, saved_rbp(%rip)
+ movq %rbx, saved_rbx(%rip)
+ movq %rdi, saved_rdi(%rip)
+ movq %rsi, saved_rsi(%rip)
addq $8, %rsp
movl $3, %edi
@@ -82,7 +83,7 @@ ENTRY(do_suspend_lowlevel)
.align 4
.Lresume_point:
/* We don't restore %rax, it must be 0 anyway */
- movq $saved_context, %rax
+ leaq saved_context(%rip), %rax
movq saved_context_cr4(%rax), %rbx
movq %rbx, %cr4
movq saved_context_cr3(%rax), %rbx
--
2.21.0.1020.gf2820cf01a-goog
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v7 10/12] x86/power/64: Adapt assembly for PIE support
2019-05-20 23:19 [PATCH v7 00/12] x86: PIE support to extend KASLR randomization Thomas Garnier
2019-05-20 23:19 ` [PATCH v7 08/12] x86/acpi: Adapt assembly for PIE support Thomas Garnier
@ 2019-05-20 23:19 ` Thomas Garnier
2019-06-10 23:52 ` Kees Cook
2019-06-10 21:32 ` [PATCH v7 00/12] x86: PIE support to extend KASLR randomization Kees Cook
2 siblings, 1 reply; 6+ messages in thread
From: Thomas Garnier @ 2019-05-20 23:19 UTC (permalink / raw)
To: kernel-hardening
Cc: kristen, Thomas Garnier, Pavel Machek, Rafael J . Wysocki,
Rafael J. Wysocki, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
H. Peter Anvin, x86, linux-pm, linux-kernel
From: Thomas Garnier <thgarnie@google.com>
Change the assembly code to use only relative references of symbols for the
kernel to be PIE compatible.
Position Independent Executable (PIE) support will allow to extend the
KASLR randomization range below 0xffffffff80000000.
Signed-off-by: Thomas Garnier <thgarnie@google.com>
Acked-by: Pavel Machek <pavel@ucw.cz>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
arch/x86/power/hibernate_asm_64.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/power/hibernate_asm_64.S b/arch/x86/power/hibernate_asm_64.S
index 3008baa2fa95..9ed980efef72 100644
--- a/arch/x86/power/hibernate_asm_64.S
+++ b/arch/x86/power/hibernate_asm_64.S
@@ -24,7 +24,7 @@
#include <asm/frame.h>
ENTRY(swsusp_arch_suspend)
- movq $saved_context, %rax
+ leaq saved_context(%rip), %rax
movq %rsp, pt_regs_sp(%rax)
movq %rbp, pt_regs_bp(%rax)
movq %rsi, pt_regs_si(%rax)
@@ -115,7 +115,7 @@ ENTRY(restore_registers)
movq %rax, %cr4; # turn PGE back on
/* We don't restore %rax, it must be 0 anyway */
- movq $saved_context, %rax
+ leaq saved_context(%rip), %rax
movq pt_regs_sp(%rax), %rsp
movq pt_regs_bp(%rax), %rbp
movq pt_regs_si(%rax), %rsi
--
2.21.0.1020.gf2820cf01a-goog
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v7 00/12] x86: PIE support to extend KASLR randomization
2019-05-20 23:19 [PATCH v7 00/12] x86: PIE support to extend KASLR randomization Thomas Garnier
2019-05-20 23:19 ` [PATCH v7 08/12] x86/acpi: Adapt assembly for PIE support Thomas Garnier
2019-05-20 23:19 ` [PATCH v7 10/12] x86/power/64: " Thomas Garnier
@ 2019-06-10 21:32 ` Kees Cook
2 siblings, 0 replies; 6+ messages in thread
From: Kees Cook @ 2019-06-10 21:32 UTC (permalink / raw)
To: Thomas Garnier
Cc: kernel-hardening, kristen, Herbert Xu, David S. Miller,
Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin,
x86, Andy Lutomirski, Juergen Gross, Alok Kataria,
Rafael J. Wysocki, Len Brown, Pavel Machek, Peter Zijlstra,
Thomas Garnier, Nadav Amit, Jann Horn, Ard Biesheuvel,
Masahiro Yamada, Andi Kleen, Andrew Morton, Feng Tang,
Jan Beulich, Maran Wilson, linux-crypto, linux-kernel,
virtualization, linux-pm
On Mon, May 20, 2019 at 04:19:25PM -0700, Thomas Garnier wrote:
> Splitting the previous serie in two. This part contains assembly code
> changes required for PIE but without any direct dependencies with the
> rest of the patchset.
Thanks for doing this! It should be easier to land the "little" fixes so
there's less to review for the big PIE changes down the road.
--
Kees Cook
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v7 08/12] x86/acpi: Adapt assembly for PIE support
2019-05-20 23:19 ` [PATCH v7 08/12] x86/acpi: Adapt assembly for PIE support Thomas Garnier
@ 2019-06-10 23:52 ` Kees Cook
0 siblings, 0 replies; 6+ messages in thread
From: Kees Cook @ 2019-06-10 23:52 UTC (permalink / raw)
To: Thomas Garnier
Cc: kernel-hardening, kristen, Thomas Garnier, Pavel Machek,
Rafael J . Wysocki, Rafael J. Wysocki, Len Brown,
Thomas Gleixner, Ingo Molnar, Borislav Petkov, H. Peter Anvin,
x86, linux-pm, linux-kernel
On Mon, May 20, 2019 at 04:19:33PM -0700, Thomas Garnier wrote:
> From: Thomas Garnier <thgarnie@google.com>
>
> Change the assembly code to use only relative references of symbols for the
> kernel to be PIE compatible.
>
> Position Independent Executable (PIE) support will allow to extend the
> KASLR randomization range below 0xffffffff80000000.
>
> Signed-off-by: Thomas Garnier <thgarnie@google.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
-Kees
> Acked-by: Pavel Machek <pavel@ucw.cz>
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
> arch/x86/kernel/acpi/wakeup_64.S | 31 ++++++++++++++++---------------
> 1 file changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S
> index 510fa12aab73..e080e943e295 100644
> --- a/arch/x86/kernel/acpi/wakeup_64.S
> +++ b/arch/x86/kernel/acpi/wakeup_64.S
> @@ -14,7 +14,7 @@
> * Hooray, we are in Long 64-bit mode (but still running in low memory)
> */
> ENTRY(wakeup_long64)
> - movq saved_magic, %rax
> + movq saved_magic(%rip), %rax
> movq $0x123456789abcdef0, %rdx
> cmpq %rdx, %rax
> jne bogus_64_magic
> @@ -25,14 +25,14 @@ ENTRY(wakeup_long64)
> movw %ax, %es
> movw %ax, %fs
> movw %ax, %gs
> - movq saved_rsp, %rsp
> + movq saved_rsp(%rip), %rsp
>
> - movq saved_rbx, %rbx
> - movq saved_rdi, %rdi
> - movq saved_rsi, %rsi
> - movq saved_rbp, %rbp
> + movq saved_rbx(%rip), %rbx
> + movq saved_rdi(%rip), %rdi
> + movq saved_rsi(%rip), %rsi
> + movq saved_rbp(%rip), %rbp
>
> - movq saved_rip, %rax
> + movq saved_rip(%rip), %rax
> jmp *%rax
> ENDPROC(wakeup_long64)
>
> @@ -45,7 +45,7 @@ ENTRY(do_suspend_lowlevel)
> xorl %eax, %eax
> call save_processor_state
>
> - movq $saved_context, %rax
> + leaq saved_context(%rip), %rax
> movq %rsp, pt_regs_sp(%rax)
> movq %rbp, pt_regs_bp(%rax)
> movq %rsi, pt_regs_si(%rax)
> @@ -64,13 +64,14 @@ ENTRY(do_suspend_lowlevel)
> pushfq
> popq pt_regs_flags(%rax)
>
> - movq $.Lresume_point, saved_rip(%rip)
> + leaq .Lresume_point(%rip), %rax
> + movq %rax, saved_rip(%rip)
>
> - movq %rsp, saved_rsp
> - movq %rbp, saved_rbp
> - movq %rbx, saved_rbx
> - movq %rdi, saved_rdi
> - movq %rsi, saved_rsi
> + movq %rsp, saved_rsp(%rip)
> + movq %rbp, saved_rbp(%rip)
> + movq %rbx, saved_rbx(%rip)
> + movq %rdi, saved_rdi(%rip)
> + movq %rsi, saved_rsi(%rip)
>
> addq $8, %rsp
> movl $3, %edi
> @@ -82,7 +83,7 @@ ENTRY(do_suspend_lowlevel)
> .align 4
> .Lresume_point:
> /* We don't restore %rax, it must be 0 anyway */
> - movq $saved_context, %rax
> + leaq saved_context(%rip), %rax
> movq saved_context_cr4(%rax), %rbx
> movq %rbx, %cr4
> movq saved_context_cr3(%rax), %rbx
> --
> 2.21.0.1020.gf2820cf01a-goog
>
--
Kees Cook
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v7 10/12] x86/power/64: Adapt assembly for PIE support
2019-05-20 23:19 ` [PATCH v7 10/12] x86/power/64: " Thomas Garnier
@ 2019-06-10 23:52 ` Kees Cook
0 siblings, 0 replies; 6+ messages in thread
From: Kees Cook @ 2019-06-10 23:52 UTC (permalink / raw)
To: Thomas Garnier
Cc: kernel-hardening, kristen, Thomas Garnier, Pavel Machek,
Rafael J . Wysocki, Rafael J. Wysocki, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, H. Peter Anvin, x86, linux-pm,
linux-kernel
On Mon, May 20, 2019 at 04:19:35PM -0700, Thomas Garnier wrote:
> From: Thomas Garnier <thgarnie@google.com>
>
> Change the assembly code to use only relative references of symbols for the
> kernel to be PIE compatible.
>
> Position Independent Executable (PIE) support will allow to extend the
> KASLR randomization range below 0xffffffff80000000.
>
> Signed-off-by: Thomas Garnier <thgarnie@google.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
-Kees
> Acked-by: Pavel Machek <pavel@ucw.cz>
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> ---
> arch/x86/power/hibernate_asm_64.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/power/hibernate_asm_64.S b/arch/x86/power/hibernate_asm_64.S
> index 3008baa2fa95..9ed980efef72 100644
> --- a/arch/x86/power/hibernate_asm_64.S
> +++ b/arch/x86/power/hibernate_asm_64.S
> @@ -24,7 +24,7 @@
> #include <asm/frame.h>
>
> ENTRY(swsusp_arch_suspend)
> - movq $saved_context, %rax
> + leaq saved_context(%rip), %rax
> movq %rsp, pt_regs_sp(%rax)
> movq %rbp, pt_regs_bp(%rax)
> movq %rsi, pt_regs_si(%rax)
> @@ -115,7 +115,7 @@ ENTRY(restore_registers)
> movq %rax, %cr4; # turn PGE back on
>
> /* We don't restore %rax, it must be 0 anyway */
> - movq $saved_context, %rax
> + leaq saved_context(%rip), %rax
> movq pt_regs_sp(%rax), %rsp
> movq pt_regs_bp(%rax), %rbp
> movq pt_regs_si(%rax), %rsi
> --
> 2.21.0.1020.gf2820cf01a-goog
>
--
Kees Cook
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-06-10 23:52 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2019-05-20 23:19 [PATCH v7 00/12] x86: PIE support to extend KASLR randomization Thomas Garnier
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2019-06-10 23:52 ` Kees Cook
2019-05-20 23:19 ` [PATCH v7 10/12] x86/power/64: " Thomas Garnier
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