From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Peter Geis <pgwipeout@gmail.com>,
Nicolas Chauvet <kwizart@gmail.com>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>,
linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v1 03/17] clk: tegra: cclk: Add helpers for handling PLLX rate changes
Date: Wed, 16 Oct 2019 00:16:04 +0300 [thread overview]
Message-ID: <20191015211618.20758-4-digetx@gmail.com> (raw)
In-Reply-To: <20191015211618.20758-1-digetx@gmail.com>
CCLK should be re-parented away from PLLX if PLLX's rate is changing.
The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus
CCLK will be re-parented to PLLP before PLLX rate-change begins and then
switched back to PLLX after the rate-change completion. This patch adds
helper functions which perform CCLK re-parenting, these helpers will be
utilized by further patches.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 36 insertions(+)
diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c
index 9b41365c4331..cacb00796c99 100644
--- a/drivers/clk/tegra/clk-tegra-super-cclk.c
+++ b/drivers/clk/tegra/clk-tegra-super-cclk.c
@@ -21,6 +21,9 @@
#define PLLP_INDEX 4
#define PLLX_INDEX 8
+static struct tegra_clk_super_mux *cclk_super;
+static bool cclk_on_pllx;
+
static u8 cclk_super_get_parent(struct clk_hw *hw)
{
return tegra_clk_super_ops.get_parent(hw);
@@ -98,6 +101,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name,
struct clk *clk;
struct clk_init_data init;
+ if (WARN_ON(cclk_super))
+ return ERR_PTR(-EBUSY);
+
super = kzalloc(sizeof(*super), GFP_KERNEL);
if (!super)
return ERR_PTR(-ENOMEM);
@@ -126,6 +132,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name,
clk = clk_register(NULL, &super->hw);
if (IS_ERR(clk))
kfree(super);
+ else
+ cclk_super = super;
return clk;
}
+
+int tegra_cclk_pre_pllx_rate_change(void)
+{
+ if (IS_ERR_OR_NULL(cclk_super))
+ return -EINVAL;
+
+ if (cclk_super_get_parent(&cclk_super->hw) == PLLX_INDEX)
+ cclk_on_pllx = true;
+ else
+ cclk_on_pllx = false;
+
+ /*
+ * CPU needs to be temporarily re-parented away from PLLX if PLLX
+ * changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs.
+ */
+ if (cclk_on_pllx)
+ cclk_super_set_parent(&cclk_super->hw, PLLP_INDEX);
+
+ return 0;
+}
+
+void tegra_cclk_post_pllx_rate_change(void)
+{
+ if (cclk_on_pllx)
+ cclk_super_set_parent(&cclk_super->hw, PLLX_INDEX);
+}
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 2be38aa2c204..3285b0332ae8 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -709,6 +709,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name,
const char * const *parent_names, u8 num_parents,
unsigned long flags, void __iomem *reg, u8 clk_super_flags,
spinlock_t *lock);
+int tegra_cclk_pre_pllx_rate_change(void);
+void tegra_cclk_post_pllx_rate_change(void);
/**
* struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
--
2.23.0
next prev parent reply other threads:[~2019-10-15 21:18 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-15 21:16 [PATCH v1 00/17] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 01/17] clk: tegra: Add custom CCLK implementation Dmitry Osipenko
2019-10-28 14:57 ` Peter De Schrijver
2019-10-28 23:48 ` Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 02/17] clk: tegra: pll: Add pre/post rate-change hooks Dmitry Osipenko
2019-10-15 21:16 ` Dmitry Osipenko [this message]
2019-10-15 21:16 ` [PATCH v1 04/17] clk: tegra20: Support custom CCLK implementation Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 05/17] clk: tegra30: " Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 06/17] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Dmitry Osipenko
2019-10-16 5:13 ` Viresh Kumar
2019-10-17 2:32 ` Viresh Kumar
2019-10-15 21:16 ` [PATCH v1 07/17] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Dmitry Osipenko
2019-10-16 5:18 ` Viresh Kumar
2019-10-16 13:29 ` Dmitry Osipenko
2019-10-16 14:58 ` Peter Geis
2019-10-16 18:19 ` Dmitry Osipenko
2019-10-17 2:32 ` Viresh Kumar
2019-10-17 21:09 ` Dmitry Osipenko
2019-10-17 2:33 ` Viresh Kumar
2019-10-15 21:16 ` [PATCH v1 08/17] ARM: tegra: Remove tegra20-cpufreq platform device creation Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 09/17] ARM: dts: tegra20: Add CPU clock Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 10/17] ARM: dts: tegra30: " Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 11/17] ARM: dts: tegra20: Add CPU Operating Performance Points Dmitry Osipenko
2019-10-16 5:23 ` Viresh Kumar
2019-10-16 13:21 ` Dmitry Osipenko
2019-10-17 2:28 ` Viresh Kumar
2019-10-17 2:32 ` Viresh Kumar
2019-10-15 21:16 ` [PATCH v1 12/17] ARM: dts: tegra30: " Dmitry Osipenko
2019-10-17 2:33 ` Viresh Kumar
2019-10-15 21:16 ` [PATCH v1 13/17] ARM: dts: tegra20: paz00: Set up voltage regulators for DVFS Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 14/17] ARM: dts: tegra20: paz00: Add CPU Operating Performance Points Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 15/17] ARM: dts: tegra20: trimslice: " Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 16/17] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 17/17] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Dmitry Osipenko
2019-10-16 5:27 ` [PATCH v1 00/17] NVIDIA Tegra20 CPUFreq driver major update Viresh Kumar
2019-10-16 13:16 ` Dmitry Osipenko
2019-10-16 14:01 ` Thierry Reding
2019-10-16 14:20 ` Dmitry Osipenko
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