From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
"Rob Herring" <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Peter Geis <pgwipeout@gmail.com>,
"Nicolas Chauvet" <kwizart@gmail.com>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>,
<linux-pm@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1 01/17] clk: tegra: Add custom CCLK implementation
Date: Mon, 28 Oct 2019 16:57:06 +0200 [thread overview]
Message-ID: <20191028145706.GF27141@pdeschrijver-desktop.Nvidia.com> (raw)
In-Reply-To: <20191015211618.20758-2-digetx@gmail.com>
On Wed, Oct 16, 2019 at 12:16:02AM +0300, Dmitry Osipenko wrote:
> CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports
> multiple parents and it has internal clock divider which uses clock
> skipping technique, meaning that CPU's voltage should correspond to the
> parent clock rate and not CCLK. PLLX is the main CCLK parent that provides
> clock rates above 1GHz and it has special property such that the CCLK's
> internal divider is set into bypass mode when PLLX is set as a parent for
> CCLK.
>
> This patch forks generic Super Clock into CCLK implementation which takes
> into account all CCLK specifics. The proper CCLK implementation is needed
> by the upcoming Tegra20 CPUFreq driver update that will allow to utilize
> the generic cpufreq-dt driver by moving intermediate clock handling into
> the clock driver. Note that technically this all could be squashed into
> clk-super, but result will be messier.
>
> Note that currently all CCLKLP bits are left in the clk-super.c and only
> CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult
> to move the CCLKLP bits, but CCLKLP is not used by anything in kernel
> and thus better not to touch it for now.
..
> + super->reg = reg;
> + super->lock = lock;
> + super->width = 4;
> + super->flags = clk_super_flags;
> + super->frac_div.reg = reg + 4;
> + super->frac_div.shift = 16;
> + super->frac_div.width = 8;
> + super->frac_div.frac_width = 1;
> + super->frac_div.lock = lock;
> + super->frac_div.flags = TEGRA_DIVIDER_SUPER;
> + super->div_ops = &tegra_clk_frac_div_ops;
> +
This is not right. The super clock divider is not a divider, it's a
pulse skipper.
> + /* Data in .init is copied by clk_register(), so stack variable OK */
> + super->hw.init = &init;
> +
> + clk = clk_register(NULL, &super->hw);
> + if (IS_ERR(clk))
> + kfree(super);
> +
> + return clk;
> +}
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index f81c10654aa9..095595a5b8a8 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -699,6 +699,10 @@ struct clk *tegra_clk_register_super_clk(const char *name,
> const char * const *parent_names, u8 num_parents,
> unsigned long flags, void __iomem *reg, u8 clk_super_flags,
> spinlock_t *lock);
> +struct clk *tegra_clk_register_super_cclk(const char *name,
> + const char * const *parent_names, u8 num_parents,
> + unsigned long flags, void __iomem *reg, u8 clk_super_flags,
> + spinlock_t *lock);
>
> /**
> * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
> --
> 2.23.0
>
next prev parent reply other threads:[~2019-10-28 14:57 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-15 21:16 [PATCH v1 00/17] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 01/17] clk: tegra: Add custom CCLK implementation Dmitry Osipenko
2019-10-28 14:57 ` Peter De Schrijver [this message]
2019-10-28 23:48 ` Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 02/17] clk: tegra: pll: Add pre/post rate-change hooks Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 03/17] clk: tegra: cclk: Add helpers for handling PLLX rate changes Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 04/17] clk: tegra20: Support custom CCLK implementation Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 05/17] clk: tegra30: " Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 06/17] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Dmitry Osipenko
2019-10-16 5:13 ` Viresh Kumar
2019-10-17 2:32 ` Viresh Kumar
2019-10-15 21:16 ` [PATCH v1 07/17] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Dmitry Osipenko
2019-10-16 5:18 ` Viresh Kumar
2019-10-16 13:29 ` Dmitry Osipenko
2019-10-16 14:58 ` Peter Geis
2019-10-16 18:19 ` Dmitry Osipenko
2019-10-17 2:32 ` Viresh Kumar
2019-10-17 21:09 ` Dmitry Osipenko
2019-10-17 2:33 ` Viresh Kumar
2019-10-15 21:16 ` [PATCH v1 08/17] ARM: tegra: Remove tegra20-cpufreq platform device creation Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 09/17] ARM: dts: tegra20: Add CPU clock Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 10/17] ARM: dts: tegra30: " Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 11/17] ARM: dts: tegra20: Add CPU Operating Performance Points Dmitry Osipenko
2019-10-16 5:23 ` Viresh Kumar
2019-10-16 13:21 ` Dmitry Osipenko
2019-10-17 2:28 ` Viresh Kumar
2019-10-17 2:32 ` Viresh Kumar
2019-10-15 21:16 ` [PATCH v1 12/17] ARM: dts: tegra30: " Dmitry Osipenko
2019-10-17 2:33 ` Viresh Kumar
2019-10-15 21:16 ` [PATCH v1 13/17] ARM: dts: tegra20: paz00: Set up voltage regulators for DVFS Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 14/17] ARM: dts: tegra20: paz00: Add CPU Operating Performance Points Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 15/17] ARM: dts: tegra20: trimslice: " Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 16/17] ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS Dmitry Osipenko
2019-10-15 21:16 ` [PATCH v1 17/17] ARM: dts: tegra30: beaver: Add CPU Operating Performance Points Dmitry Osipenko
2019-10-16 5:27 ` [PATCH v1 00/17] NVIDIA Tegra20 CPUFreq driver major update Viresh Kumar
2019-10-16 13:16 ` Dmitry Osipenko
2019-10-16 14:01 ` Thierry Reding
2019-10-16 14:20 ` Dmitry Osipenko
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