From: bchihi@baylibre.com
To: daniel.lezcano@linaro.org,
angelogioacchino.delregno@collabora.com, rafael@kernel.org,
amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
rdunlap@infradead.org, ye.xingchen@zte.com.cn,
p.zabel@pengutronix.de
Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
khilman@baylibre.com, james.lo@mediatek.com,
rex-bc.chen@mediatek.com
Subject: [PATCH 2/4] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
Date: Tue, 7 Mar 2023 17:34:11 +0100 [thread overview]
Message-ID: <20230307163413.143334-3-bchihi@baylibre.com> (raw)
In-Reply-To: <20230307163413.143334-1-bchihi@baylibre.com>
From: Balsam CHIHI <bchihi@baylibre.com>
Add LVTS Driver support for MT8192.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 106 +++++++++++++++++++++++-
1 file changed, 104 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 7565def6b27c..b505c6b49031 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -80,6 +80,7 @@
#define LVTS_MSR_FILTERED_MODE 1
#define LVTS_HW_SHUTDOWN_MT8195 105000
+#define LVTS_HW_SHUTDOWN_MT8192 105000
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
static int coeff_b = LVTS_COEFF_B;
@@ -528,7 +529,7 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* The efuse blob values follows the sensor enumeration per thermal
* controller. The decoding of the stream is as follow:
*
- * stream index map for MCU Domain :
+ * stream index map for MCU Domain mt8195/mt8192 :
*
* <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
@@ -539,7 +540,7 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
* 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
*
- * stream index map for AP Domain :
+ * stream index map for AP Domain mt8195/mt8192 :
*
* <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
@@ -547,12 +548,22 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
* 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
*
+ * stream index map for AP Domain mt8195 :
+ *
* <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
* 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
*
* <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
* 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
*
+ * stream index map for AP Domain mt8192 :
+ *
+ * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5----->
+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C
+ *
+ * <-----ap--tc#3-----> <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
+ * 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
+ *
* The data description gives the offset of the calibration data in
* this bytes stream for each sensor.
*/
@@ -1246,6 +1257,85 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
}
};
+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
+ {
+ .cal_offset = { 0x04, 0x07 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU0 },
+ { .dt_id = MT8192_MCU_BIG_CPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x0d, 0x10 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU2 },
+ { .dt_id = MT8192_MCU_BIG_CPU3 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x16, 0x19, 0x1c, 0x1f },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
+ },
+ .num_lvts_sensor = 4,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ }
+};
+
+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
+ {
+ .cal_offset = { 0x25, 0x28 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_VPU0 },
+ { .dt_id = MT8192_AP_VPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x2e, 0x31 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_GPU0 },
+ { .dt_id = MT8192_AP_GPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x37, 0x3a },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_INFRA },
+ { .dt_id = MT8192_AP_CAM },
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x40, 0x43, 0x46 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_MD0 },
+ { .dt_id = MT8192_AP_MD1 },
+ { .dt_id = MT8192_AP_MD2 }
+ },
+ .num_lvts_sensor = 3,
+ .offset = 0x300,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ }
+};
+
static const struct lvts_data mt8195_lvts_mcu_data = {
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
@@ -1256,9 +1346,21 @@ static const struct lvts_data mt8195_lvts_ap_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
};
+static const struct lvts_data mt8192_lvts_mcu_data = {
+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
+};
+
+static const struct lvts_data mt8192_lvts_ap_data = {
+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
+};
+
static const struct of_device_id lvts_of_match[] = {
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
{},
};
MODULE_DEVICE_TABLE(of, lvts_of_match);
--
2.34.1
next prev parent reply other threads:[~2023-03-07 16:36 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-07 16:34 [PATCH 0/4] Add LVTS support for mt8192 bchihi
2023-03-07 16:34 ` [PATCH 1/4] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition " bchihi
2023-03-08 9:20 ` AngeloGioacchino Del Regno
2023-03-09 16:17 ` Krzysztof Kozlowski
2023-03-07 16:34 ` bchihi [this message]
2023-03-08 9:23 ` [PATCH 2/4] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support AngeloGioacchino Del Regno
2023-03-08 15:59 ` Balsam CHIHI
2023-03-07 16:34 ` [PATCH 3/4] arm64: dts: mediatek: mt8192: Add thermal zones and thermal nodes bchihi
2023-03-07 16:34 ` [PATCH 4/4] arm64: dts: mediatek: mt8192: Add temperature mitigation threshold bchihi
2023-03-09 5:04 ` [PATCH 0/4] Add LVTS support for mt8192 Chen-Yu Tsai
2023-03-09 10:47 ` Balsam CHIHI
2023-03-22 12:48 ` Balsam CHIHI
2023-03-25 4:33 ` Chen-Yu Tsai
2023-03-28 0:20 ` Balsam CHIHI
2023-03-28 3:12 ` Chen-Yu Tsai
2023-03-29 8:05 ` Balsam CHIHI
2023-04-24 22:21 ` Nícolas F. R. A. Prado
2023-04-25 8:36 ` Balsam CHIHI
2023-04-25 9:59 ` Chen-Yu Tsai
2023-04-25 11:28 ` Balsam CHIHI
2023-04-26 23:20 ` Nícolas F. R. A. Prado
2023-04-27 14:08 ` Balsam CHIHI
2023-04-28 20:00 ` Nícolas F. R. A. Prado
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