[PATCH 0/8] qcom-cpufreq-hw binding improvements

[PATCH 0/8] qcom-cpufreq-hw binding improvements

[Konrad Dybcio]

This series tries to better sanitize what's actually allowed on which
SoC and lowers the minimum frequency domain count to 1, as that's what's
present on at least QCM2290.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (8):
      dt-bindings: cpufreq: cpufreq-qcom-hw: Allow just 1 frequency domain
      dt-bindings: cpufreq: cpufreq-qcom-hw: Sanitize data per compatible
      dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCM2290
      arm64: dts: qcom: sc7180: Add SoC-specific compatible to cpufreq_hw
      arm64: dts: qcom: sdm845: Add SoC-specific compatible to cpufreq_hw
      arm64: dts: qcom: sm6115: Add SoC-specific compatible to cpufreq_hw
      arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw
      arm64: dts: qcom: sm8150: Add SoC-specific compatible to cpufreq_hw

 .../bindings/cpufreq/cpufreq-qcom-hw.yaml          | 118 ++++++++++++++++++++-
 arch/arm64/boot/dts/qcom/sc7180.dtsi               |   2 +-
 arch/arm64/boot/dts/qcom/sdm845.dtsi               |   2 +-
 arch/arm64/boot/dts/qcom/sm6115.dtsi               |   2 +-
 arch/arm64/boot/dts/qcom/sm6350.dtsi               |   2 +-
 arch/arm64/boot/dts/qcom/sm8150.dtsi               |   2 +-
 6 files changed, 120 insertions(+), 8 deletions(-)
---
base-commit: 709c6adf19dc558e44ab5c01659b09a16a2d3c82
change-id: 20230308-topic-cpufreq_bindings-5f78e3af96b3

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@linaro.org>

[PATCH 1/8] dt-bindings: cpufreq: cpufreq-qcom-hw: Allow just 1 frequency domain

[Konrad Dybcio]

Some SoCs implementing CPUFREQ-HW only have a single frequency domain.
Allow such case.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index e4aa8c67d532..aebf2254e45a 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -36,14 +36,14 @@ properties:
           - const: qcom,cpufreq-epss
 
   reg:
-    minItems: 2
+    minItems: 1
     items:
       - description: Frequency domain 0 register region
       - description: Frequency domain 1 register region
       - description: Frequency domain 2 register region
 
   reg-names:
-    minItems: 2
+    minItems: 1
     items:
       - const: freq-domain0
       - const: freq-domain1

-- 
2.39.2

Re: [PATCH 1/8] dt-bindings: cpufreq: cpufreq-qcom-hw: Allow just 1 frequency domain

[Rob Herring]

On Wed, 08 Mar 2023 02:26:58 +0100, Konrad Dybcio wrote:
> Some SoCs implementing CPUFREQ-HW only have a single frequency domain.
> Allow such case.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

[PATCH 2/8] dt-bindings: cpufreq: cpufreq-qcom-hw: Sanitize data per compatible

[Konrad Dybcio]

Introduce per-SoC compatibles for OSM targets (read: pre-sm8250) and
sanitize the number of interrupt{s,-names} and reg/-names per-compatible.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../bindings/cpufreq/cpufreq-qcom-hw.yaml          | 90 +++++++++++++++++++++-
 1 file changed, 89 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index aebf2254e45a..6f97e2effaca 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -20,6 +20,12 @@ properties:
     oneOf:
       - description: v1 of CPUFREQ HW
         items:
+          - enum:
+              - qcom,sc7180-cpufreq-hw
+              - qcom,sdm845-cpufreq-hw
+              - qcom,sm6115-cpufreq-hw
+              - qcom,sm6350-cpufreq-hw
+              - qcom,sm8150-cpufreq-hw
           - const: qcom,cpufreq-hw
 
       - description: v2 of CPUFREQ HW (EPSS)
@@ -85,6 +91,88 @@ required:
 
 additionalProperties: false
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,qdu1000-cpufreq-epss
+              - qcom,sc7180-cpufreq-hw
+              - qcom,sc8280xp-cpufreq-epss
+              - qcom,sdm845-cpufreq-hw
+              - qcom,sm6115-cpufreq-hw
+              - qcom,sm6350-cpufreq-hw
+              - qcom,sm6375-cpufreq-epss
+    then:
+      properties:
+        reg:
+          minItems: 2
+          maxItems: 2
+
+        reg-names:
+          minItems: 2
+          maxItems: 2
+
+        interrupts:
+          minItems: 2
+          maxItems: 2
+
+        interrupt-names:
+          minItems: 2
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sc7280-cpufreq-epss
+              - qcom,sm8250-cpufreq-epss
+              - qcom,sm8350-cpufreq-epss
+              - qcom,sm8450-cpufreq-epss
+              - qcom,sm8550-cpufreq-epss
+    then:
+      properties:
+        reg:
+          minItems: 3
+          maxItems: 3
+
+        reg-names:
+          minItems: 3
+          maxItems: 3
+
+        interrupts:
+          minItems: 3
+          maxItems: 3
+
+        interrupt-names:
+          minItems: 3
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sm8150-cpufreq-hw
+    then:
+      properties:
+        reg:
+          minItems: 3
+          maxItems: 3
+
+        reg-names:
+          minItems: 3
+          maxItems: 3
+
+        # On some SoCs the Prime core shares the LMH irq with Big cores
+        interrupts:
+          minItems: 2
+          maxItems: 2
+
+        interrupt-names:
+          minItems: 2
+
+
 examples:
   - |
     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
@@ -235,7 +323,7 @@ examples:
       #size-cells = <1>;
 
       cpufreq@17d43000 {
-        compatible = "qcom,cpufreq-hw";
+        compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
         reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
         reg-names = "freq-domain0", "freq-domain1";
 

-- 
2.39.2

Re: [PATCH 2/8] dt-bindings: cpufreq: cpufreq-qcom-hw: Sanitize data per compatible

[Rob Herring]

On Wed, 08 Mar 2023 02:26:59 +0100, Konrad Dybcio wrote:
> Introduce per-SoC compatibles for OSM targets (read: pre-sm8250) and
> sanitize the number of interrupt{s,-names} and reg/-names per-compatible.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  .../bindings/cpufreq/cpufreq-qcom-hw.yaml          | 90 +++++++++++++++++++++-
>  1 file changed, 89 insertions(+), 1 deletion(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH 3/8] dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCM2290

[Konrad Dybcio]

Document the OSM CPUFREQ_HW present on QCM2290, featuring just one
lonely frequency domain.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../bindings/cpufreq/cpufreq-qcom-hw.yaml          | 24 ++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index 6f97e2effaca..dc4e497b15ac 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -21,6 +21,7 @@ properties:
       - description: v1 of CPUFREQ HW
         items:
           - enum:
+              - qcom,qcm2290-cpufreq-hw
               - qcom,sc7180-cpufreq-hw
               - qcom,sdm845-cpufreq-hw
               - qcom,sm6115-cpufreq-hw
@@ -92,6 +93,29 @@ required:
 additionalProperties: false
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,qcm2290-cpufreq-hw
+    then:
+      properties:
+        reg:
+          minItems: 1
+          maxItems: 1
+
+        reg-names:
+          minItems: 1
+          maxItems: 1
+
+        interrupts:
+          minItems: 1
+          maxItems: 1
+
+        interrupt-names:
+          minItems: 1
+
   - if:
       properties:
         compatible:

-- 
2.39.2

Re: [PATCH 3/8] dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCM2290

[Rob Herring]

On Wed, 08 Mar 2023 02:27:00 +0100, Konrad Dybcio wrote:
> Document the OSM CPUFREQ_HW present on QCM2290, featuring just one
> lonely frequency domain.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>  .../bindings/cpufreq/cpufreq-qcom-hw.yaml          | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH 4/8] arm64: dts: qcom: sc7180: Add SoC-specific compatible to cpufreq_hw

[Konrad Dybcio]

Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index ebfa21e9ed8a..a80bdd0604e4 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -3570,7 +3570,7 @@ osm_l3: interconnect@18321000 {
 		};
 
 		cpufreq_hw: cpufreq@18323000 {
-			compatible = "qcom,cpufreq-hw";
+			compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
 			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
 			reg-names = "freq-domain0", "freq-domain1";
 

-- 
2.39.2

[PATCH 5/8] arm64: dts: qcom: sdm845: Add SoC-specific compatible to cpufreq_hw

[Konrad Dybcio]

Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 479859bd8ab3..5a7cc1ad8094 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -5222,7 +5222,7 @@ osm_l3: interconnect@17d41000 {
 		};
 
 		cpufreq_hw: cpufreq@17d43000 {
-			compatible = "qcom,cpufreq-hw";
+			compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
 			reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
 			reg-names = "freq-domain0", "freq-domain1";
 

-- 
2.39.2

[PATCH 6/8] arm64: dts: qcom: sm6115: Add SoC-specific compatible to cpufreq_hw

[Konrad Dybcio]

Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 4d6ec815b78b..fae30bf31e08 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -2114,7 +2114,7 @@ intc: interrupt-controller@f200000 {
 		};
 
 		cpufreq_hw: cpufreq@f521000 {
-			compatible = "qcom,cpufreq-hw";
+			compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
 			reg = <0x0 0x0f521000 0x0 0x1000>,
 			      <0x0 0x0f523000 0x0 0x1000>;
 

-- 
2.39.2

[PATCH 7/8] arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw

[Konrad Dybcio]

Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 1e1d366c92c1..c18ca947618e 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1995,7 +1995,7 @@ osm_l3: interconnect@18321000 {
 		};
 
 		cpufreq_hw: cpufreq@18323000 {
-			compatible = "qcom,cpufreq-hw";
+			compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
 			reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
 			reg-names = "freq-domain0", "freq-domain1";
 			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;

-- 
2.39.2

Re: [PATCH 7/8] arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw

[Luca Weiss]

Hi Konrad,

On Wed Mar 8, 2023 at 2:27 AM CET, Konrad Dybcio wrote:
> Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>

> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 1e1d366c92c1..c18ca947618e 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1995,7 +1995,7 @@ osm_l3: interconnect@18321000 {
>  		};
>  
>  		cpufreq_hw: cpufreq@18323000 {
> -			compatible = "qcom,cpufreq-hw";
> +			compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
>  			reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
>  			reg-names = "freq-domain0", "freq-domain1";
>  			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
>
> -- 
> 2.39.2

[PATCH 8/8] arm64: dts: qcom: sm8150: Add SoC-specific compatible to cpufreq_hw

[Konrad Dybcio]

Add a SoC-specific compatbile to cpufreq_hw for compliancy with bindings.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index fd20096cfc6e..e7e66bc3e6c4 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -4263,7 +4263,7 @@ osm_l3: interconnect@18321000 {
 		};
 
 		cpufreq_hw: cpufreq@18323000 {
-			compatible = "qcom,cpufreq-hw";
+			compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw";
 			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
 			      <0 0x18327800 0 0x1400>;
 			reg-names = "freq-domain0", "freq-domain1",

-- 
2.39.2

Re: (subset) [PATCH 0/8] qcom-cpufreq-hw binding improvements

[Bjorn Andersson]

On Wed, 08 Mar 2023 02:26:57 +0100, Konrad Dybcio wrote:
> This series tries to better sanitize what's actually allowed on which
> SoC and lowers the minimum frequency domain count to 1, as that's what's
> present on at least QCM2290.
> 
> 

Applied, thanks!

[4/8] arm64: dts: qcom: sc7180: Add SoC-specific compatible to cpufreq_hw
      commit: e4c17be956fbe133211c24b9fc9ba253ffc44db6
[5/8] arm64: dts: qcom: sdm845: Add SoC-specific compatible to cpufreq_hw
      commit: 236e7dd568ed4b839fb8abdf3ce7c77444e610e2
[6/8] arm64: dts: qcom: sm6115: Add SoC-specific compatible to cpufreq_hw
      commit: f33f95773e148cd0adbfc3135f2bfbf56a69f488
[7/8] arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw
      commit: 64917707914f95fa5827f2cc5bea2d5febe3a01b
[8/8] arm64: dts: qcom: sm8150: Add SoC-specific compatible to cpufreq_hw
      commit: b2e1f87070ead06fb2918edeeed4329f58d1b2ee

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH 0/8] qcom-cpufreq-hw binding improvements

[Viresh Kumar]

On 08-03-23, 02:26, Konrad Dybcio wrote:
> This series tries to better sanitize what's actually allowed on which
> SoC and lowers the minimum frequency domain count to 1, as that's what's
> present on at least QCM2290.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> Konrad Dybcio (8):
>       dt-bindings: cpufreq: cpufreq-qcom-hw: Allow just 1 frequency domain
>       dt-bindings: cpufreq: cpufreq-qcom-hw: Sanitize data per compatible
>       dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCM2290

Applied these three, thanks..

-- 
viresh