Re: [PATCH v7 4/5] PM / devfreq: Add dynamic scaling for imx8m ddr controller

[Chanwoo Choi <cw00.choi@samsung.com>]

On 11/27/19 4:44 AM, Rob Herring wrote:
> On Sun, Nov 24, 2019 at 4:53 PM Chanwoo Choi <cw00.choi@samsung.com> wrote:
>>
>> Hi Leonard,
>>
>> On 11/23/19 6:45 AM, Leonard Crestez wrote:
>>> Add driver for dynamic scaling the DDR Controller on imx8m chips. Actual
>>> frequency switching is implemented inside TF-A, this driver wraps the
>>> SMC calls and synchronizes the clk tree.
>>>
>>> The DRAM clocks on imx8m have the following structure (abridged):
>>>
>>>  +----------+       |\            +------+
>>>  | dram_pll |-------|M| dram_core |      |
>>>  +----------+       |U|---------->| D    |
>>>                  /--|X|           |  D   |
>>>    dram_alt_root |  |/            |   R  |
>>>                  |                |    C |
>>>             +---------+           |      |
>>>             |FIX DIV/4|           |      |
>>>             +---------+           |      |
>>>   composite:     |                |      |
>>>  +----------+    |                |      |
>>>  | dram_alt |----/                |      |
>>>  +----------+                     |      |
>>>  | dram_apb |-------------------->|      |
>>>  +----------+                     +------+
>>>
>>> The dram_pll is used for higher rates and dram_alt is used for lower
>>> rates. The dram_alt and dram_apb clocks are "imx composite" and their
>>> parent can also be modified.
>>>
>>> This driver will prepare/enable the new parents ahead of switching (so
>>> that the expected roots are enabled) and afterwards it will call
>>> clk_set_parent to ensure the parents in clock framework are up-to-date.
>>>
>>> The driver relies on dram_pll dram_alt and dram_apb being marked with
>>> CLK_GET_RATE_NOCACHE for rate updates.
>>>
>>> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
>>> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
>>> ---
>>>  drivers/devfreq/Kconfig      |   9 +
>>>  drivers/devfreq/Makefile     |   1 +
>>>  drivers/devfreq/imx8m-ddrc.c | 465 +++++++++++++++++++++++++++++++++++
>>>  3 files changed, 475 insertions(+)
>>>  create mode 100644 drivers/devfreq/imx8m-ddrc.c
>>>
>>> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
>>> index 59027d7ddf2a..5eac479dd05f 100644
>>> --- a/drivers/devfreq/Kconfig
>>> +++ b/drivers/devfreq/Kconfig
>>> @@ -89,10 +89,19 @@ config ARM_EXYNOS_BUS_DEVFREQ
>>>         Each memory bus group could contain many memoby bus block. It reads
>>>         PPMU counters of memory controllers by using DEVFREQ-event device
>>>         and adjusts the operating frequencies and voltages with OPP support.
>>>         This does not yet operate with optimal voltages.
>>>
>>> +config ARM_IMX8M_DDRC_DEVFREQ
>>> +     tristate "i.MX8M DDRC DEVFREQ Driver"
>>> +     depends on ARCH_MXC && HAVE_ARM_SMCCC
>>
>> I'll edit it as following and applied it.
> 
> You corrupted the URLs in the binding patch when applying the series:
> 
> Traceback (most recent call last):
>  File "/usr/local/lib/python3.6/dist-packages/jsonschema/validators.py",
> line 774, in resolve_from_url
>  document = self.store[url]
>  File "/usr/local/lib/python3.6/dist-packages/jsonschema/_utils.py",
> line 22, in __getitem__
>  return self.store[self.normalize(uri)]
> KeyError: 'https://protect2.fireeye.com/url?k=b51ff83f-e8cff0d7-b51e7370-000babff32e3-c25c03b8af1b12ee&u=http://devicetree.org/meta-schemas/core.yaml'
> 

I'm sorry the url was changed when I applied them
because of the internal security system..
I fixed and updated it to devfreq next branch.

Thanks,
Chanwoo Choi