* [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles
2024-04-24 10:15 [PATCH 0/3] arm64: qcom: Add cpufreq and clock support Tengfei Fan
@ 2024-04-24 10:15 ` Tengfei Fan
2024-04-24 17:03 ` Bjorn Andersson
` (2 more replies)
2024-04-24 10:15 ` [PATCH 2/3] arm64: dts: qcom: sm4450: Add cpufreq support Tengfei Fan
2024-04-24 10:15 ` [PATCH 3/3] arm64: dts: qcom: sm4450: Supply clock from cpufreq node to CPUs Tengfei Fan
2 siblings, 3 replies; 11+ messages in thread
From: Tengfei Fan @ 2024-04-24 10:15 UTC (permalink / raw)
To: rafael, viresh.kumar, robh, krzk+dt, conor+dt, andersson, konrad.dybcio
Cc: manivannan.sadhasivam, linux-pm, devicetree, linux-kernel,
linux-arm-msm, Tengfei Fan
Add compatible for EPSS CPUFREQ-HW on SM4450.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index 56fc71d6a081..1e9797f96410 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -38,6 +38,7 @@ properties:
- qcom,sc7280-cpufreq-epss
- qcom,sc8280xp-cpufreq-epss
- qcom,sdx75-cpufreq-epss
+ - qcom,sm4450-cpufreq-epss
- qcom,sm6375-cpufreq-epss
- qcom,sm8250-cpufreq-epss
- qcom,sm8350-cpufreq-epss
@@ -133,6 +134,7 @@ allOf:
- qcom,sc8280xp-cpufreq-epss
- qcom,sdm670-cpufreq-hw
- qcom,sdm845-cpufreq-hw
+ - qcom,sm4450-cpufreq-epss
- qcom,sm6115-cpufreq-hw
- qcom,sm6350-cpufreq-hw
- qcom,sm6375-cpufreq-epss
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles
2024-04-24 10:15 ` [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles Tengfei Fan
@ 2024-04-24 17:03 ` Bjorn Andersson
2024-04-24 22:08 ` Rob Herring
2024-04-25 5:21 ` Viresh Kumar
2 siblings, 0 replies; 11+ messages in thread
From: Bjorn Andersson @ 2024-04-24 17:03 UTC (permalink / raw)
To: Tengfei Fan
Cc: rafael, viresh.kumar, robh, krzk+dt, conor+dt, andersson,
konrad.dybcio, manivannan.sadhasivam, linux-pm, devicetree,
linux-kernel, linux-arm-msm
On Wed, Apr 24, 2024 at 06:15:01PM +0800, Tengfei Fan wrote:
> Add compatible for EPSS CPUFREQ-HW on SM4450.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Regards,
Bjorn
> ---
> Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> index 56fc71d6a081..1e9797f96410 100644
> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> @@ -38,6 +38,7 @@ properties:
> - qcom,sc7280-cpufreq-epss
> - qcom,sc8280xp-cpufreq-epss
> - qcom,sdx75-cpufreq-epss
> + - qcom,sm4450-cpufreq-epss
> - qcom,sm6375-cpufreq-epss
> - qcom,sm8250-cpufreq-epss
> - qcom,sm8350-cpufreq-epss
> @@ -133,6 +134,7 @@ allOf:
> - qcom,sc8280xp-cpufreq-epss
> - qcom,sdm670-cpufreq-hw
> - qcom,sdm845-cpufreq-hw
> + - qcom,sm4450-cpufreq-epss
> - qcom,sm6115-cpufreq-hw
> - qcom,sm6350-cpufreq-hw
> - qcom,sm6375-cpufreq-epss
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles
2024-04-24 10:15 ` [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles Tengfei Fan
2024-04-24 17:03 ` Bjorn Andersson
@ 2024-04-24 22:08 ` Rob Herring
2024-04-25 5:21 ` Viresh Kumar
2 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2024-04-24 22:08 UTC (permalink / raw)
To: Tengfei Fan
Cc: manivannan.sadhasivam, rafael, linux-kernel, viresh.kumar,
konrad.dybcio, linux-pm, krzk+dt, devicetree, conor+dt,
andersson, linux-arm-msm
On Wed, 24 Apr 2024 18:15:01 +0800, Tengfei Fan wrote:
> Add compatible for EPSS CPUFREQ-HW on SM4450.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles
2024-04-24 10:15 ` [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles Tengfei Fan
2024-04-24 17:03 ` Bjorn Andersson
2024-04-24 22:08 ` Rob Herring
@ 2024-04-25 5:21 ` Viresh Kumar
2 siblings, 0 replies; 11+ messages in thread
From: Viresh Kumar @ 2024-04-25 5:21 UTC (permalink / raw)
To: Tengfei Fan
Cc: rafael, robh, krzk+dt, conor+dt, andersson, konrad.dybcio,
manivannan.sadhasivam, linux-pm, devicetree, linux-kernel,
linux-arm-msm
On 24-04-24, 18:15, Tengfei Fan wrote:
> Add compatible for EPSS CPUFREQ-HW on SM4450.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Applied. Thanks.
--
viresh
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/3] arm64: dts: qcom: sm4450: Add cpufreq support
2024-04-24 10:15 [PATCH 0/3] arm64: qcom: Add cpufreq and clock support Tengfei Fan
2024-04-24 10:15 ` [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles Tengfei Fan
@ 2024-04-24 10:15 ` Tengfei Fan
2024-04-24 23:41 ` Dmitry Baryshkov
2024-04-24 10:15 ` [PATCH 3/3] arm64: dts: qcom: sm4450: Supply clock from cpufreq node to CPUs Tengfei Fan
2 siblings, 1 reply; 11+ messages in thread
From: Tengfei Fan @ 2024-04-24 10:15 UTC (permalink / raw)
To: rafael, viresh.kumar, robh, krzk+dt, conor+dt, andersson, konrad.dybcio
Cc: manivannan.sadhasivam, linux-pm, devicetree, linux-kernel,
linux-arm-msm, Tengfei Fan
Add a description of a SM4450 cpufreq-epss controller and references to
it from CPU nodes.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 29 ++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 603c962661cc..92badfd5b0e1 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -29,6 +29,14 @@ sleep_clk: sleep-clk {
clock-frequency = <32000>;
#clock-cells = <0>;
};
+
+ bi_tcxo_div2: bi-tcxo-div2-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ };
};
cpus {
@@ -43,6 +51,7 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
@@ -67,6 +76,7 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
@@ -85,6 +95,7 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
@@ -103,6 +114,7 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
@@ -121,6 +133,7 @@ CPU4: cpu@400 {
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_400: l2-cache {
@@ -139,6 +152,7 @@ CPU5: cpu@500 {
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_500: l2-cache {
@@ -157,6 +171,7 @@ CPU6: cpu@600 {
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
@@ -175,6 +190,7 @@ CPU7: cpu@700 {
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
+ qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_700: l2-cache {
@@ -526,6 +542,19 @@ rpmhcc: clock-controller {
};
};
+ cpufreq_hw: cpufreq@17d91000 {
+ compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss";
+ reg = <0 0x17d91000 0 0x1000>,
+ <0 0x17d92000 0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+ clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
};
timer {
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 2/3] arm64: dts: qcom: sm4450: Add cpufreq support
2024-04-24 10:15 ` [PATCH 2/3] arm64: dts: qcom: sm4450: Add cpufreq support Tengfei Fan
@ 2024-04-24 23:41 ` Dmitry Baryshkov
2024-04-25 3:18 ` Tengfei Fan
0 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2024-04-24 23:41 UTC (permalink / raw)
To: Tengfei Fan
Cc: rafael, viresh.kumar, robh, krzk+dt, conor+dt, andersson,
konrad.dybcio, manivannan.sadhasivam, linux-pm, devicetree,
linux-kernel, linux-arm-msm
On Wed, 24 Apr 2024 at 13:16, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>
> Add a description of a SM4450 cpufreq-epss controller and references to
> it from CPU nodes.
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm4450.dtsi | 29 ++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
With the next patch being squashed in:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: sm4450: Add cpufreq support
2024-04-24 23:41 ` Dmitry Baryshkov
@ 2024-04-25 3:18 ` Tengfei Fan
0 siblings, 0 replies; 11+ messages in thread
From: Tengfei Fan @ 2024-04-25 3:18 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: rafael, viresh.kumar, robh, krzk+dt, conor+dt, andersson,
konrad.dybcio, manivannan.sadhasivam, linux-pm, devicetree,
linux-kernel, linux-arm-msm
On 4/25/2024 7:41 AM, Dmitry Baryshkov wrote:
> On Wed, 24 Apr 2024 at 13:16, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>>
>> Add a description of a SM4450 cpufreq-epss controller and references to
>> it from CPU nodes.
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm4450.dtsi | 29 ++++++++++++++++++++++++++++
>> 1 file changed, 29 insertions(+)
>
> With the next patch being squashed in:
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
Clock support patch[PATCH 3/3] will be squashed in this patch in the new
version patch series.
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: sm4450: Supply clock from cpufreq node to CPUs
2024-04-24 10:15 [PATCH 0/3] arm64: qcom: Add cpufreq and clock support Tengfei Fan
2024-04-24 10:15 ` [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM4450 compatibles Tengfei Fan
2024-04-24 10:15 ` [PATCH 2/3] arm64: dts: qcom: sm4450: Add cpufreq support Tengfei Fan
@ 2024-04-24 10:15 ` Tengfei Fan
2024-04-24 11:23 ` Dmitry Baryshkov
2 siblings, 1 reply; 11+ messages in thread
From: Tengfei Fan @ 2024-04-24 10:15 UTC (permalink / raw)
To: rafael, viresh.kumar, robh, krzk+dt, conor+dt, andersson, konrad.dybcio
Cc: manivannan.sadhasivam, linux-pm, devicetree, linux-kernel,
linux-arm-msm, Tengfei Fan
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply
clocks to the CPU cores. But this relationship is not represented in DTS
so far.
So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
---
arch/arm64/boot/dts/qcom/sm4450.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
index 92badfd5b0e1..8d75c4f9731c 100644
--- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
@@ -47,6 +47,7 @@ CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
@@ -72,6 +73,7 @@ CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD0>;
@@ -91,6 +93,7 @@ CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD0>;
@@ -110,6 +113,7 @@ CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD0>;
@@ -129,6 +133,7 @@ CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x400>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD0>;
@@ -148,6 +153,7 @@ CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x500>;
+ clocks = <&cpufreq_hw 0>;
enable-method = "psci";
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD0>;
@@ -167,6 +173,7 @@ CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0 0x600>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD0>;
@@ -186,6 +193,7 @@ CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a78";
reg = <0x0 0x700>;
+ clocks = <&cpufreq_hw 1>;
enable-method = "psci";
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD0>;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: sm4450: Supply clock from cpufreq node to CPUs
2024-04-24 10:15 ` [PATCH 3/3] arm64: dts: qcom: sm4450: Supply clock from cpufreq node to CPUs Tengfei Fan
@ 2024-04-24 11:23 ` Dmitry Baryshkov
2024-04-25 3:17 ` Tengfei Fan
0 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2024-04-24 11:23 UTC (permalink / raw)
To: Tengfei Fan
Cc: rafael, viresh.kumar, robh, krzk+dt, conor+dt, andersson,
konrad.dybcio, manivannan.sadhasivam, linux-pm, devicetree,
linux-kernel, linux-arm-msm
On Wed, 24 Apr 2024 at 13:17, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>
> Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply
> clocks to the CPU cores. But this relationship is not represented in DTS
> so far.
>
> So let's make cpufreq node as the clock provider and CPU nodes as the
> consumers. The clock index for each CPU node is based on the frequency
> domain index.
Is there any reason why this is not a part of the previous patch?
>
> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/sm4450.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> index 92badfd5b0e1..8d75c4f9731c 100644
> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
> @@ -47,6 +47,7 @@ CPU0: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x0>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> power-domains = <&CPU_PD0>;
> @@ -72,6 +73,7 @@ CPU1: cpu@100 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x100>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> next-level-cache = <&L2_100>;
> power-domains = <&CPU_PD0>;
> @@ -91,6 +93,7 @@ CPU2: cpu@200 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x200>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> next-level-cache = <&L2_200>;
> power-domains = <&CPU_PD0>;
> @@ -110,6 +113,7 @@ CPU3: cpu@300 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x300>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> next-level-cache = <&L2_300>;
> power-domains = <&CPU_PD0>;
> @@ -129,6 +133,7 @@ CPU4: cpu@400 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x400>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> next-level-cache = <&L2_400>;
> power-domains = <&CPU_PD0>;
> @@ -148,6 +153,7 @@ CPU5: cpu@500 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x500>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> next-level-cache = <&L2_500>;
> power-domains = <&CPU_PD0>;
> @@ -167,6 +173,7 @@ CPU6: cpu@600 {
> device_type = "cpu";
> compatible = "arm,cortex-a78";
> reg = <0x0 0x600>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> next-level-cache = <&L2_600>;
> power-domains = <&CPU_PD0>;
> @@ -186,6 +193,7 @@ CPU7: cpu@700 {
> device_type = "cpu";
> compatible = "arm,cortex-a78";
> reg = <0x0 0x700>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> next-level-cache = <&L2_700>;
> power-domains = <&CPU_PD0>;
> --
> 2.25.1
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH 3/3] arm64: dts: qcom: sm4450: Supply clock from cpufreq node to CPUs
2024-04-24 11:23 ` Dmitry Baryshkov
@ 2024-04-25 3:17 ` Tengfei Fan
0 siblings, 0 replies; 11+ messages in thread
From: Tengfei Fan @ 2024-04-25 3:17 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: rafael, viresh.kumar, robh, krzk+dt, conor+dt, andersson,
konrad.dybcio, manivannan.sadhasivam, linux-pm, devicetree,
linux-kernel, linux-arm-msm
On 4/24/2024 7:23 PM, Dmitry Baryshkov wrote:
> On Wed, 24 Apr 2024 at 13:17, Tengfei Fan <quic_tengfan@quicinc.com> wrote:
>>
>> Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply
>> clocks to the CPU cores. But this relationship is not represented in DTS
>> so far.
>>
>> So let's make cpufreq node as the clock provider and CPU nodes as the
>> consumers. The clock index for each CPU node is based on the frequency
>> domain index.
>
> Is there any reason why this is not a part of the previous patch?
Before, I understood that clock and cpufreq support are two functions,
so they were divided into two patches.
I will squash this patch in cpufreq support patch in the new version
patch series.
>
>>
>> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm4450.dtsi | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> index 92badfd5b0e1..8d75c4f9731c 100644
>> --- a/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi
>> @@ -47,6 +47,7 @@ CPU0: cpu@0 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a55";
>> reg = <0x0 0x0>;
>> + clocks = <&cpufreq_hw 0>;
>> enable-method = "psci";
>> next-level-cache = <&L2_0>;
>> power-domains = <&CPU_PD0>;
>> @@ -72,6 +73,7 @@ CPU1: cpu@100 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a55";
>> reg = <0x0 0x100>;
>> + clocks = <&cpufreq_hw 0>;
>> enable-method = "psci";
>> next-level-cache = <&L2_100>;
>> power-domains = <&CPU_PD0>;
>> @@ -91,6 +93,7 @@ CPU2: cpu@200 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a55";
>> reg = <0x0 0x200>;
>> + clocks = <&cpufreq_hw 0>;
>> enable-method = "psci";
>> next-level-cache = <&L2_200>;
>> power-domains = <&CPU_PD0>;
>> @@ -110,6 +113,7 @@ CPU3: cpu@300 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a55";
>> reg = <0x0 0x300>;
>> + clocks = <&cpufreq_hw 0>;
>> enable-method = "psci";
>> next-level-cache = <&L2_300>;
>> power-domains = <&CPU_PD0>;
>> @@ -129,6 +133,7 @@ CPU4: cpu@400 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a55";
>> reg = <0x0 0x400>;
>> + clocks = <&cpufreq_hw 0>;
>> enable-method = "psci";
>> next-level-cache = <&L2_400>;
>> power-domains = <&CPU_PD0>;
>> @@ -148,6 +153,7 @@ CPU5: cpu@500 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a55";
>> reg = <0x0 0x500>;
>> + clocks = <&cpufreq_hw 0>;
>> enable-method = "psci";
>> next-level-cache = <&L2_500>;
>> power-domains = <&CPU_PD0>;
>> @@ -167,6 +173,7 @@ CPU6: cpu@600 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a78";
>> reg = <0x0 0x600>;
>> + clocks = <&cpufreq_hw 1>;
>> enable-method = "psci";
>> next-level-cache = <&L2_600>;
>> power-domains = <&CPU_PD0>;
>> @@ -186,6 +193,7 @@ CPU7: cpu@700 {
>> device_type = "cpu";
>> compatible = "arm,cortex-a78";
>> reg = <0x0 0x700>;
>> + clocks = <&cpufreq_hw 1>;
>> enable-method = "psci";
>> next-level-cache = <&L2_700>;
>> power-domains = <&CPU_PD0>;
>> --
>> 2.25.1
>>
>>
>
>
--
Thx and BRs,
Tengfei Fan
^ permalink raw reply [flat|nested] 11+ messages in thread