[PATCH v2 0/2] Add critical interrupt and cooling maps for TSENS in SC7180 and configuration in yaml

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* [PATCH v2 0/2] Add critical interrupt and cooling maps for TSENS in SC7180 and configuration in yaml
@ 2020-01-06 13:29 Rajeshwari
  2020-01-06 13:29 ` [PATCH v2 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180 Rajeshwari
  2020-01-06 13:29 ` [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml Rajeshwari
  0 siblings, 2 replies; 8+ messages in thread
From: Rajeshwari @ 2020-01-06 13:29 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Rob Herring, Amit Kucheria,
	Zhang Rui, Daniel Lezcano, Mark Rutland
  Cc: linux-arm-msm, devicetree, linux-pm, linux-kernel, sanm, sivaa,
	manaf, Rajeshwari

Added critical interrupt support in TSENS node and cooling maps in Thermal-zones node
and configuration for SC7180 in yaml.

changes in v2:
* Removed renamings from thermal-zones.

Rajeshwari (2):
  arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for
    TSENS in SC7180
  dt-bindings: thermal: tsens: Add configuration in yaml

 .../devicetree/bindings/thermal/qcom-tsens.yaml    |   1 +
 arch/arm64/boot/dts/qcom/sc7180.dtsi               | 197 ++++++++++++++++++++-
 2 files changed, 194 insertions(+), 4 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v2 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180
  2020-01-06 13:29 [PATCH v2 0/2] Add critical interrupt and cooling maps for TSENS in SC7180 and configuration in yaml Rajeshwari
@ 2020-01-06 13:29 ` Rajeshwari
  2020-01-07  5:27   ` Amit Kucheria
  2020-01-07  5:48   ` Bjorn Andersson
  2020-01-06 13:29 ` [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml Rajeshwari
  1 sibling, 2 replies; 8+ messages in thread
From: Rajeshwari @ 2020-01-06 13:29 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Rob Herring, Amit Kucheria,
	Zhang Rui, Daniel Lezcano, Mark Rutland
  Cc: linux-arm-msm, devicetree, linux-pm, linux-kernel, sanm, sivaa,
	manaf, Rajeshwari

Added critical interrupt support in TSENS node and cooling maps in Thermal-zones node.

Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 197 ++++++++++++++++++++++++++++++++++-
 1 file changed, 193 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 3676bfd..c414ce0 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
 	interrupt-parent = <&intc>;
@@ -78,6 +79,7 @@
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			next-level-cache = <&L2_0>;
+			#cooling-cells = <2>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_0: l2-cache {
 				compatible = "cache";
@@ -94,6 +96,7 @@
 			reg = <0x0 0x100>;
 			enable-method = "psci";
 			next-level-cache = <&L2_100>;
+			#cooling-cells = <2>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_100: l2-cache {
 				compatible = "cache";
@@ -107,6 +110,7 @@
 			reg = <0x0 0x200>;
 			enable-method = "psci";
 			next-level-cache = <&L2_200>;
+			#cooling-cells = <2>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_200: l2-cache {
 				compatible = "cache";
@@ -120,6 +124,7 @@
 			reg = <0x0 0x300>;
 			enable-method = "psci";
 			next-level-cache = <&L2_300>;
+			#cooling-cells = <2>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_300: l2-cache {
 				compatible = "cache";
@@ -133,6 +138,7 @@
 			reg = <0x0 0x400>;
 			enable-method = "psci";
 			next-level-cache = <&L2_400>;
+			#cooling-cells = <2>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_400: l2-cache {
 				compatible = "cache";
@@ -146,6 +152,7 @@
 			reg = <0x0 0x500>;
 			enable-method = "psci";
 			next-level-cache = <&L2_500>;
+			#cooling-cells = <2>;
 			qcom,freq-domain = <&cpufreq_hw 0>;
 			L2_500: l2-cache {
 				compatible = "cache";
@@ -159,6 +166,7 @@
 			reg = <0x0 0x600>;
 			enable-method = "psci";
 			next-level-cache = <&L2_600>;
+			#cooling-cells = <2>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_600: l2-cache {
 				compatible = "cache";
@@ -172,6 +180,7 @@
 			reg = <0x0 0x700>;
 			enable-method = "psci";
 			next-level-cache = <&L2_700>;
+			#cooling-cells = <2>;
 			qcom,freq-domain = <&cpufreq_hw 1>;
 			L2_700: l2-cache {
 				compatible = "cache";
@@ -1058,8 +1067,9 @@
 			reg = <0 0x0c263000 0 0x1ff>, /* TM */
 				<0 0x0c222000 0 0x1ff>; /* SROT */
 			#qcom,sensors = <15>;
-			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "uplow";
+			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow","critical";
 			#thermal-sensor-cells = <1>;
 		};
 
@@ -1068,8 +1078,9 @@
 			reg = <0 0x0c265000 0 0x1ff>, /* TM */
 				<0 0x0c223000 0 0x1ff>; /* SROT */
 			#qcom,sensors = <10>;
-			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-names = "uplow";
+			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "uplow","critical";
 			#thermal-sensor-cells = <1>;
 		};
 
@@ -1326,6 +1337,27 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu0_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu0_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu1-thermal {
@@ -1353,6 +1385,27 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu1_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu1_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu2-thermal {
@@ -1380,6 +1433,27 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu2_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu2_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu3-thermal {
@@ -1407,6 +1481,27 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu3_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu3_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu4-thermal {
@@ -1434,6 +1529,27 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu4_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu4_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu5-thermal {
@@ -1461,6 +1577,27 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu5_alert0>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu5_alert1>;
+					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu6-thermal {
@@ -1488,6 +1625,19 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu6_alert0>;
+					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu6_alert1>;
+					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu7-thermal {
@@ -1515,6 +1665,19 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu7_alert0>;
+					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu7_alert1>;
+					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu8-thermal {
@@ -1542,6 +1705,19 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu8_alert0>;
+					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu8_alert1>;
+					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		cpu9-thermal {
@@ -1569,6 +1745,19 @@
 					type = "critical";
 				};
 			};
+
+			cooling-maps {
+				map0 {
+					trip = <&cpu9_alert0>;
+					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+				map1 {
+					trip = <&cpu9_alert1>;
+					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
 		};
 
 		aoss0-thermal {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180
  2020-01-06 13:29 ` [PATCH v2 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180 Rajeshwari
@ 2020-01-07  5:27   ` Amit Kucheria
  2020-01-07  5:48   ` Bjorn Andersson
  1 sibling, 0 replies; 8+ messages in thread
From: Amit Kucheria @ 2020-01-07  5:27 UTC (permalink / raw)
  To: Rajeshwari
  Cc: Andy Gross, Bjorn Andersson, Rob Herring, Zhang Rui,
	Daniel Lezcano, Mark Rutland, linux-arm-msm, DTML, Linux PM list,
	Linux Kernel Mailing List, sanm, sivaa, manaf

On Mon, Jan 6, 2020 at 7:00 PM Rajeshwari <rkambl@codeaurora.org> wrote:
>
> Added critical interrupt support in TSENS node and cooling maps in Thermal-zones node.
>
> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>

Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>

> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 197 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 193 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 3676bfd..c414ce0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -10,6 +10,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/phy/phy-qcom-qusb2.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/thermal/thermal.h>
>
>  / {
>         interrupt-parent = <&intc>;
> @@ -78,6 +79,7 @@
>                         reg = <0x0 0x0>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_0>;
> +                       #cooling-cells = <2>;
>                         qcom,freq-domain = <&cpufreq_hw 0>;
>                         L2_0: l2-cache {
>                                 compatible = "cache";
> @@ -94,6 +96,7 @@
>                         reg = <0x0 0x100>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_100>;
> +                       #cooling-cells = <2>;
>                         qcom,freq-domain = <&cpufreq_hw 0>;
>                         L2_100: l2-cache {
>                                 compatible = "cache";
> @@ -107,6 +110,7 @@
>                         reg = <0x0 0x200>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_200>;
> +                       #cooling-cells = <2>;
>                         qcom,freq-domain = <&cpufreq_hw 0>;
>                         L2_200: l2-cache {
>                                 compatible = "cache";
> @@ -120,6 +124,7 @@
>                         reg = <0x0 0x300>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_300>;
> +                       #cooling-cells = <2>;
>                         qcom,freq-domain = <&cpufreq_hw 0>;
>                         L2_300: l2-cache {
>                                 compatible = "cache";
> @@ -133,6 +138,7 @@
>                         reg = <0x0 0x400>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_400>;
> +                       #cooling-cells = <2>;
>                         qcom,freq-domain = <&cpufreq_hw 0>;
>                         L2_400: l2-cache {
>                                 compatible = "cache";
> @@ -146,6 +152,7 @@
>                         reg = <0x0 0x500>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_500>;
> +                       #cooling-cells = <2>;
>                         qcom,freq-domain = <&cpufreq_hw 0>;
>                         L2_500: l2-cache {
>                                 compatible = "cache";
> @@ -159,6 +166,7 @@
>                         reg = <0x0 0x600>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_600>;
> +                       #cooling-cells = <2>;
>                         qcom,freq-domain = <&cpufreq_hw 1>;
>                         L2_600: l2-cache {
>                                 compatible = "cache";
> @@ -172,6 +180,7 @@
>                         reg = <0x0 0x700>;
>                         enable-method = "psci";
>                         next-level-cache = <&L2_700>;
> +                       #cooling-cells = <2>;
>                         qcom,freq-domain = <&cpufreq_hw 1>;
>                         L2_700: l2-cache {
>                                 compatible = "cache";
> @@ -1058,8 +1067,9 @@
>                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
>                                 <0 0x0c222000 0 0x1ff>; /* SROT */
>                         #qcom,sensors = <15>;
> -                       interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
> -                       interrupt-names = "uplow";
> +                       interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "uplow","critical";
>                         #thermal-sensor-cells = <1>;
>                 };
>
> @@ -1068,8 +1078,9 @@
>                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
>                                 <0 0x0c223000 0 0x1ff>; /* SROT */
>                         #qcom,sensors = <10>;
> -                       interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
> -                       interrupt-names = "uplow";
> +                       interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "uplow","critical";
>                         #thermal-sensor-cells = <1>;
>                 };
>
> @@ -1326,6 +1337,27 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu0_alert0>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu0_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 cpu1-thermal {
> @@ -1353,6 +1385,27 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu1_alert0>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu1_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 cpu2-thermal {
> @@ -1380,6 +1433,27 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu2_alert0>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu2_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 cpu3-thermal {
> @@ -1407,6 +1481,27 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu3_alert0>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu3_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 cpu4-thermal {
> @@ -1434,6 +1529,27 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu4_alert0>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu4_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 cpu5-thermal {
> @@ -1461,6 +1577,27 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu5_alert0>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu5_alert1>;
> +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 cpu6-thermal {
> @@ -1488,6 +1625,19 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu6_alert0>;
> +                                       cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu6_alert1>;
> +                                       cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 cpu7-thermal {
> @@ -1515,6 +1665,19 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu7_alert0>;
> +                                       cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu7_alert1>;
> +                                       cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 cpu8-thermal {
> @@ -1542,6 +1705,19 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu8_alert0>;
> +                                       cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu8_alert1>;
> +                                       cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 cpu9-thermal {
> @@ -1569,6 +1745,19 @@
>                                         type = "critical";
>                                 };
>                         };
> +
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu9_alert0>;
> +                                       cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                               map1 {
> +                                       trip = <&cpu9_alert1>;
> +                                       cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                                        <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
>                 };
>
>                 aoss0-thermal {
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180
  2020-01-06 13:29 ` [PATCH v2 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180 Rajeshwari
  2020-01-07  5:27   ` Amit Kucheria
@ 2020-01-07  5:48   ` Bjorn Andersson
  1 sibling, 0 replies; 8+ messages in thread
From: Bjorn Andersson @ 2020-01-07  5:48 UTC (permalink / raw)
  To: Rajeshwari
  Cc: Andy Gross, Rob Herring, Amit Kucheria, Zhang Rui,
	Daniel Lezcano, Mark Rutland, linux-arm-msm, devicetree,
	linux-pm, linux-kernel, sanm, sivaa, manaf

On Mon 06 Jan 05:29 PST 2020, Rajeshwari wrote:

> Added critical interrupt support in TSENS node and cooling maps in Thermal-zones node.
> 
> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>

Patch applied, with Amit's tag.

Thanks,
Bjorn

> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 197 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 193 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 3676bfd..c414ce0 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -10,6 +10,7 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/phy/phy-qcom-qusb2.h>
>  #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/thermal/thermal.h>
>  
>  / {
>  	interrupt-parent = <&intc>;
> @@ -78,6 +79,7 @@
>  			reg = <0x0 0x0>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_0>;
> +			#cooling-cells = <2>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_0: l2-cache {
>  				compatible = "cache";
> @@ -94,6 +96,7 @@
>  			reg = <0x0 0x100>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_100>;
> +			#cooling-cells = <2>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_100: l2-cache {
>  				compatible = "cache";
> @@ -107,6 +110,7 @@
>  			reg = <0x0 0x200>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_200>;
> +			#cooling-cells = <2>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_200: l2-cache {
>  				compatible = "cache";
> @@ -120,6 +124,7 @@
>  			reg = <0x0 0x300>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_300>;
> +			#cooling-cells = <2>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_300: l2-cache {
>  				compatible = "cache";
> @@ -133,6 +138,7 @@
>  			reg = <0x0 0x400>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_400>;
> +			#cooling-cells = <2>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_400: l2-cache {
>  				compatible = "cache";
> @@ -146,6 +152,7 @@
>  			reg = <0x0 0x500>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_500>;
> +			#cooling-cells = <2>;
>  			qcom,freq-domain = <&cpufreq_hw 0>;
>  			L2_500: l2-cache {
>  				compatible = "cache";
> @@ -159,6 +166,7 @@
>  			reg = <0x0 0x600>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_600>;
> +			#cooling-cells = <2>;
>  			qcom,freq-domain = <&cpufreq_hw 1>;
>  			L2_600: l2-cache {
>  				compatible = "cache";
> @@ -172,6 +180,7 @@
>  			reg = <0x0 0x700>;
>  			enable-method = "psci";
>  			next-level-cache = <&L2_700>;
> +			#cooling-cells = <2>;
>  			qcom,freq-domain = <&cpufreq_hw 1>;
>  			L2_700: l2-cache {
>  				compatible = "cache";
> @@ -1058,8 +1067,9 @@
>  			reg = <0 0x0c263000 0 0x1ff>, /* TM */
>  				<0 0x0c222000 0 0x1ff>; /* SROT */
>  			#qcom,sensors = <15>;
> -			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "uplow";
> +			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "uplow","critical";
>  			#thermal-sensor-cells = <1>;
>  		};
>  
> @@ -1068,8 +1078,9 @@
>  			reg = <0 0x0c265000 0 0x1ff>, /* TM */
>  				<0 0x0c223000 0 0x1ff>; /* SROT */
>  			#qcom,sensors = <10>;
> -			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
> -			interrupt-names = "uplow";
> +			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "uplow","critical";
>  			#thermal-sensor-cells = <1>;
>  		};
>  
> @@ -1326,6 +1337,27 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu0_alert0>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu0_alert1>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu1-thermal {
> @@ -1353,6 +1385,27 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu1_alert0>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu1_alert1>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu2-thermal {
> @@ -1380,6 +1433,27 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu2_alert0>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu2_alert1>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu3-thermal {
> @@ -1407,6 +1481,27 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu3_alert0>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu3_alert1>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu4-thermal {
> @@ -1434,6 +1529,27 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu4_alert0>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu4_alert1>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu5-thermal {
> @@ -1461,6 +1577,27 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu5_alert0>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu5_alert1>;
> +					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu6-thermal {
> @@ -1488,6 +1625,19 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu6_alert0>;
> +					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu6_alert1>;
> +					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu7-thermal {
> @@ -1515,6 +1665,19 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu7_alert0>;
> +					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu7_alert1>;
> +					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu8-thermal {
> @@ -1542,6 +1705,19 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu8_alert0>;
> +					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu8_alert1>;
> +					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		cpu9-thermal {
> @@ -1569,6 +1745,19 @@
>  					type = "critical";
>  				};
>  			};
> +
> +			cooling-maps {
> +				map0 {
> +					trip = <&cpu9_alert0>;
> +					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +				map1 {
> +					trip = <&cpu9_alert1>;
> +					cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +							 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +				};
> +			};
>  		};
>  
>  		aoss0-thermal {
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
> of Code Aurora Forum, hosted by The Linux Foundation
> 

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml
  2020-01-06 13:29 [PATCH v2 0/2] Add critical interrupt and cooling maps for TSENS in SC7180 and configuration in yaml Rajeshwari
  2020-01-06 13:29 ` [PATCH v2 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180 Rajeshwari
@ 2020-01-06 13:29 ` Rajeshwari
  2020-01-06 19:15   ` Bjorn Andersson
                     ` (2 more replies)
  1 sibling, 3 replies; 8+ messages in thread
From: Rajeshwari @ 2020-01-06 13:29 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Rob Herring, Amit Kucheria,
	Zhang Rui, Daniel Lezcano, Mark Rutland
  Cc: linux-arm-msm, devicetree, linux-pm, linux-kernel, sanm, sivaa,
	manaf, Rajeshwari

Added configuration in dt-bindings for SC7180.

Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
---
 Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index eef13b9..c0ed030 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -38,6 +38,7 @@ properties:
           - enum:
               - qcom,msm8996-tsens
               - qcom,msm8998-tsens
+              - qcom,sc7180-tsens
               - qcom,sdm845-tsens
           - const: qcom,tsens-v2
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml
  2020-01-06 13:29 ` [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml Rajeshwari
@ 2020-01-06 19:15   ` Bjorn Andersson
  2020-01-06 23:03   ` Rob Herring
  2020-01-07  5:28   ` Amit Kucheria
  2 siblings, 0 replies; 8+ messages in thread
From: Bjorn Andersson @ 2020-01-06 19:15 UTC (permalink / raw)
  To: Rajeshwari
  Cc: Andy Gross, Rob Herring, Amit Kucheria, Zhang Rui,
	Daniel Lezcano, Mark Rutland, linux-arm-msm, devicetree,
	linux-pm, linux-kernel, sanm, sivaa, manaf

On Mon 06 Jan 05:29 PST 2020, Rajeshwari wrote:

> Added configuration in dt-bindings for SC7180.
> 

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> index eef13b9..c0ed030 100644
> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> @@ -38,6 +38,7 @@ properties:
>            - enum:
>                - qcom,msm8996-tsens
>                - qcom,msm8998-tsens
> +              - qcom,sc7180-tsens
>                - qcom,sdm845-tsens
>            - const: qcom,tsens-v2
>  
> -- 
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
> of Code Aurora Forum, hosted by The Linux Foundation
> 

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml
  2020-01-06 13:29 ` [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml Rajeshwari
  2020-01-06 19:15   ` Bjorn Andersson
@ 2020-01-06 23:03   ` Rob Herring
  2020-01-07  5:28   ` Amit Kucheria
  2 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2020-01-06 23:03 UTC (permalink / raw)
  To: Rajeshwari
  Cc: Andy Gross, Bjorn Andersson, Amit Kucheria, Zhang Rui,
	Daniel Lezcano, Mark Rutland, linux-arm-msm, devicetree,
	linux-pm, linux-kernel, sanm, sivaa, manaf, Rajeshwari

On Mon,  6 Jan 2020 18:59:29 +0530, Rajeshwari wrote:
> Added configuration in dt-bindings for SC7180.
> 
> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml
  2020-01-06 13:29 ` [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml Rajeshwari
  2020-01-06 19:15   ` Bjorn Andersson
  2020-01-06 23:03   ` Rob Herring
@ 2020-01-07  5:28   ` Amit Kucheria
  2 siblings, 0 replies; 8+ messages in thread
From: Amit Kucheria @ 2020-01-07  5:28 UTC (permalink / raw)
  To: Rajeshwari
  Cc: Andy Gross, Bjorn Andersson, Rob Herring, Zhang Rui,
	Daniel Lezcano, Mark Rutland, linux-arm-msm, DTML, Linux PM list,
	Linux Kernel Mailing List, sanm, sivaa, manaf

On Mon, Jan 6, 2020 at 7:00 PM Rajeshwari <rkambl@codeaurora.org> wrote:
>
> Added configuration in dt-bindings for SC7180.
>
> Signed-off-by: Rajeshwari <rkambl@codeaurora.org>

Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>

> ---
>  Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> index eef13b9..c0ed030 100644
> --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
> @@ -38,6 +38,7 @@ properties:
>            - enum:
>                - qcom,msm8996-tsens
>                - qcom,msm8998-tsens
> +              - qcom,sc7180-tsens
>                - qcom,sdm845-tsens
>            - const: qcom,tsens-v2
>
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2020-01-07  5:48 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-06 13:29 [PATCH v2 0/2] Add critical interrupt and cooling maps for TSENS in SC7180 and configuration in yaml Rajeshwari
2020-01-06 13:29 ` [PATCH v2 1/2] arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180 Rajeshwari
2020-01-07  5:27   ` Amit Kucheria
2020-01-07  5:48   ` Bjorn Andersson
2020-01-06 13:29 ` [PATCH v2 2/2] dt-bindings: thermal: tsens: Add configuration in yaml Rajeshwari
2020-01-06 19:15   ` Bjorn Andersson
2020-01-06 23:03   ` Rob Herring
2020-01-07  5:28   ` Amit Kucheria

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