From: Jeff LaBundy <jeff@labundy.com>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: Thierry Reding <thierry.reding@gmail.com>,
linux-pwm@vger.kernel.org, Lee Jones <lee.jones@linaro.org>,
kernel@pengutronix.de
Subject: Re: [PATCH v3] pwm: iqs620a: Fix overflow and optimize calculations
Date: Thu, 14 Jan 2021 22:07:20 -0600 [thread overview]
Message-ID: <20210115040720.GC27243@labundy.com> (raw)
In-Reply-To: <20210114215026.163424-1-u.kleine-koenig@pengutronix.de>
Hi Uwe,
Thank you for your work here; it's coming together quite nicely.
On Thu, Jan 14, 2021 at 10:50:26PM +0100, Uwe Kleine-König wrote:
> If state->duty_cycle is 0x100000000000000, the previous calculation of
> duty_scale overflows and yields a duty cycle ratio of 0% instead of
> 100%. Fix this by clamping the requested duty cycle to the maximal
> possible duty cycle first. This way it is possible to use a native
> integer division instead of a (depending on the architecture) more
> expensive 64bit division.
>
> With this change in place duty_scale cannot be bigger than 256 which
> allows to simplify the calculation of duty_val.
>
> Fixes: 6f0841a8197b ("pwm: Add support for Azoteq IQS620A PWM generator")
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
> drivers/pwm/pwm-iqs620a.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pwm/pwm-iqs620a.c b/drivers/pwm/pwm-iqs620a.c
> index 5ede8255926e..eb03f60c5db8 100644
> --- a/drivers/pwm/pwm-iqs620a.c
> +++ b/drivers/pwm/pwm-iqs620a.c
> @@ -46,7 +46,9 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> {
> struct iqs620_pwm_private *iqs620_pwm;
> struct iqs62x_core *iqs62x;
> - u64 duty_scale;
> + unsigned duty_cycle;
> + unsigned duty_scale;
> +
> int ret;
>
Nit: there is a rogue newline here. I'm also not such a fan of mixing
shorthand 'unsigned' with existing 'unsigned int' (as in probe).
> if (state->polarity != PWM_POLARITY_NORMAL)
> @@ -70,7 +72,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> * For lower duty cycles (e.g. 0), the PWM output is simply disabled to
> * allow an external pull-down resistor to hold the GPIO3/LTX pin low.
> */
> - duty_scale = div_u64(state->duty_cycle * 256, IQS620_PWM_PERIOD_NS);
> + duty_cycle = min_t(u64, state->duty_cycle, IQS620_PWM_PERIOD_NS);
> + duty_scale = duty_cycle * 256 / IQS620_PWM_PERIOD_NS;
>
> mutex_lock(&iqs620_pwm->lock);
>
> @@ -82,7 +85,7 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> }
>
> if (duty_scale) {
> - u8 duty_val = min_t(u64, duty_scale - 1, 0xff);
> + u8 duty_val = duty_scale - 1;
>
> ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,
> duty_val);
> --
> 2.29.2
>
That being said, the patch is functionally correct and I validated all
corner cases with actual hardware. Feel free to add to future cosmetic
revisions:
Tested-by: Jeff LaBundy <jeff@labundy.com>
Kind regards,
Jeff LaBundy
next prev parent reply other threads:[~2021-01-15 4:08 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-14 21:50 [PATCH v3] pwm: iqs620a: Fix overflow and optimize calculations Uwe Kleine-König
2021-01-15 4:07 ` Jeff LaBundy [this message]
2021-01-15 7:32 ` [PATCH v4] " Uwe Kleine-König
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