From: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
To: Jeff LaBundy <jeff@labundy.com>
Cc: linux-pwm@vger.kernel.org,
Thierry Reding <thierry.reding@gmail.com>,
Lee Jones <lee.jones@linaro.org>,
kernel@pengutronix.de
Subject: [PATCH v4] pwm: iqs620a: Fix overflow and optimize calculations
Date: Fri, 15 Jan 2021 08:32:39 +0100 [thread overview]
Message-ID: <20210115073239.2tnf5o4j7ushfpsz@pengutronix.de> (raw)
In-Reply-To: <20210115040720.GC27243@labundy.com>
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If state->duty_cycle is 0x100000000000000, the previous calculation of
duty_scale overflows and yields a duty cycle ratio of 0% instead of
100%. Fix this by clamping the requested duty cycle to the maximal
possible duty cycle first. This way it is possible to use a native
integer division instead of a (depending on the architecture) more
expensive 64bit division.
With this change in place duty_scale cannot be bigger than 256 which
allows to simplify the calculation of duty_val.
Fixes: 6f0841a8197b ("pwm: Add support for Azoteq IQS620A PWM generator")
Tested-by: Jeff LaBundy <jeff@labundy.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
Hi Jeff,
On Thu, Jan 14, 2021 at 10:07:20PM -0600, Jeff LaBundy wrote:
> Thank you for your work here; it's coming together quite nicely.
Thank you for your prompt feedback, it adds much to the fun to be able
to rely on someone who cares and looks into patches.
> On Thu, Jan 14, 2021 at 10:50:26PM +0100, Uwe Kleine-König wrote:
> > struct iqs620_pwm_private *iqs620_pwm;
> > struct iqs62x_core *iqs62x;
> > - u64 duty_scale;
> > + unsigned duty_cycle;
> > + unsigned duty_scale;
> > +
> > int ret;
> >
>
> Nit: there is a rogue newline here. I'm also not such a fan of mixing
> shorthand 'unsigned' with existing 'unsigned int' (as in probe).
full ack. checkpatch even warns about unsigned without int. *sigh*
> > [...]
>
> That being said, the patch is functionally correct and I validated all
> corner cases with actual hardware. Feel free to add to future cosmetic
> revisions:
>
> Tested-by: Jeff LaBundy <jeff@labundy.com>
done, thanks
These are the only changes since v3 (i.e.
- use unsigned int instead of unsigned
- remove empty line
- add Tested-by
)
Best regards
Uwe
drivers/pwm/pwm-iqs620a.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/pwm/pwm-iqs620a.c b/drivers/pwm/pwm-iqs620a.c
index 5ede8255926e..14b18fb4f527 100644
--- a/drivers/pwm/pwm-iqs620a.c
+++ b/drivers/pwm/pwm-iqs620a.c
@@ -46,7 +46,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
{
struct iqs620_pwm_private *iqs620_pwm;
struct iqs62x_core *iqs62x;
- u64 duty_scale;
+ unsigned int duty_cycle;
+ unsigned int duty_scale;
int ret;
if (state->polarity != PWM_POLARITY_NORMAL)
@@ -70,7 +71,8 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
* For lower duty cycles (e.g. 0), the PWM output is simply disabled to
* allow an external pull-down resistor to hold the GPIO3/LTX pin low.
*/
- duty_scale = div_u64(state->duty_cycle * 256, IQS620_PWM_PERIOD_NS);
+ duty_cycle = min_t(u64, state->duty_cycle, IQS620_PWM_PERIOD_NS);
+ duty_scale = duty_cycle * 256 / IQS620_PWM_PERIOD_NS;
mutex_lock(&iqs620_pwm->lock);
@@ -82,7 +84,7 @@ static int iqs620_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
}
if (duty_scale) {
- u8 duty_val = min_t(u64, duty_scale - 1, 0xff);
+ u8 duty_val = duty_scale - 1;
ret = regmap_write(iqs62x->regmap, IQS620_PWM_DUTY_CYCLE,
duty_val);
--
2.29.2
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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prev parent reply other threads:[~2021-01-15 7:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-14 21:50 [PATCH v3] pwm: iqs620a: Fix overflow and optimize calculations Uwe Kleine-König
2021-01-15 4:07 ` Jeff LaBundy
2021-01-15 7:32 ` Uwe Kleine-König [this message]
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