From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Ulf Hansson" <ulf.hansson@linaro.org>,
"Viresh Kumar" <vireshk@kernel.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Peter De Schrijver" <pdeschrijver@nvidia.com>,
"Mikko Perttunen" <mperttunen@nvidia.com>,
"Peter Chen" <peter.chen@kernel.org>,
"Lee Jones" <lee.jones@linaro.org>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Nishanth Menon" <nm@ti.com>,
"Adrian Hunter" <adrian.hunter@intel.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-pm@vger.kernel.org, linux-usb@vger.kernel.org,
linux-staging@lists.linux.dev, linux-pwm@vger.kernel.org,
linux-mmc@vger.kernel.org, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
Mark Brown <broonie@kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Richard Weinberger <richard@nod.at>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Lucas Stach <dev@lynxeye.de>, Stefan Agner <stefan@agner.ch>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
David Heidelberg <david@ixit.cz>
Subject: [PATCH v12 26/35] soc/tegra: fuse: Use resource-managed helpers
Date: Mon, 20 Sep 2021 21:11:36 +0300 [thread overview]
Message-ID: <20210920181145.19543-27-digetx@gmail.com> (raw)
In-Reply-To: <20210920181145.19543-1-digetx@gmail.com>
Use resource-managed helpers to make code cleaner and more correct,
properly releasing all resources in case of driver probe error.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/soc/tegra/fuse/fuse-tegra.c | 32 ++++++++++++++------------
drivers/soc/tegra/fuse/fuse-tegra20.c | 33 ++++++++++++++++++++++++---
2 files changed, 48 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index cc032729a143..fe4f935ce73a 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -182,6 +182,12 @@ static const struct nvmem_cell_info tegra_fuse_cells[] = {
},
};
+static void tegra_fuse_restore(void *base)
+{
+ fuse->clk = NULL;
+ fuse->base = base;
+}
+
static int tegra_fuse_probe(struct platform_device *pdev)
{
void __iomem *base = fuse->base;
@@ -189,13 +195,16 @@ static int tegra_fuse_probe(struct platform_device *pdev)
struct resource *res;
int err;
+ err = devm_add_action(&pdev->dev, tegra_fuse_restore, base);
+ if (err)
+ return err;
+
/* take over the memory region from the early initialization */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fuse->phys = res->start;
fuse->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(fuse->base)) {
err = PTR_ERR(fuse->base);
- fuse->base = base;
return err;
}
@@ -205,19 +214,20 @@ static int tegra_fuse_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
PTR_ERR(fuse->clk));
- fuse->base = base;
return PTR_ERR(fuse->clk);
}
platform_set_drvdata(pdev, fuse);
fuse->dev = &pdev->dev;
- pm_runtime_enable(&pdev->dev);
+ err = devm_pm_runtime_enable(&pdev->dev);
+ if (err)
+ return err;
if (fuse->soc->probe) {
err = fuse->soc->probe(fuse);
if (err < 0)
- goto restore;
+ return err;
}
memset(&nvmem, 0, sizeof(nvmem));
@@ -241,7 +251,7 @@ static int tegra_fuse_probe(struct platform_device *pdev)
err = PTR_ERR(fuse->nvmem);
dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
err);
- goto restore;
+ return err;
}
fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse");
@@ -249,7 +259,7 @@ static int tegra_fuse_probe(struct platform_device *pdev)
err = PTR_ERR(fuse->rst);
dev_err(&pdev->dev, "failed to get FUSE reset: %pe\n",
fuse->rst);
- goto restore;
+ return err;
}
/*
@@ -258,26 +268,20 @@ static int tegra_fuse_probe(struct platform_device *pdev)
*/
err = pm_runtime_resume_and_get(&pdev->dev);
if (err)
- goto restore;
+ return err;
err = reset_control_reset(fuse->rst);
pm_runtime_put(&pdev->dev);
if (err < 0) {
dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err);
- goto restore;
+ return err;
}
/* release the early I/O memory mapping */
iounmap(base);
return 0;
-
-restore:
- fuse->clk = NULL;
- fuse->base = base;
- pm_runtime_disable(&pdev->dev);
- return err;
}
static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev)
diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c
index 8ec9fc5e5e4b..12503f563e36 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra20.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra20.c
@@ -94,9 +94,28 @@ static bool dma_filter(struct dma_chan *chan, void *filter_param)
return of_device_is_compatible(np, "nvidia,tegra20-apbdma");
}
+static void tegra20_fuse_release_channel(void *data)
+{
+ struct tegra_fuse *fuse = data;
+
+ dma_release_channel(fuse->apbdma.chan);
+ fuse->apbdma.chan = NULL;
+}
+
+static void tegra20_fuse_free_coherent(void *data)
+{
+ struct tegra_fuse *fuse = data;
+
+ dma_free_coherent(fuse->dev, sizeof(u32), fuse->apbdma.virt,
+ fuse->apbdma.phys);
+ fuse->apbdma.virt = NULL;
+ fuse->apbdma.phys = 0x0;
+}
+
static int tegra20_fuse_probe(struct tegra_fuse *fuse)
{
dma_cap_mask_t mask;
+ int err;
dma_cap_zero(mask);
dma_cap_set(DMA_SLAVE, mask);
@@ -105,13 +124,21 @@ static int tegra20_fuse_probe(struct tegra_fuse *fuse)
if (!fuse->apbdma.chan)
return -EPROBE_DEFER;
+ err = devm_add_action_or_reset(fuse->dev, tegra20_fuse_release_channel,
+ fuse);
+ if (err)
+ return err;
+
fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32),
&fuse->apbdma.phys,
GFP_KERNEL);
- if (!fuse->apbdma.virt) {
- dma_release_channel(fuse->apbdma.chan);
+ if (!fuse->apbdma.virt)
return -ENOMEM;
- }
+
+ err = devm_add_action_or_reset(fuse->dev, tegra20_fuse_free_coherent,
+ fuse);
+ if (err)
+ return err;
fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
--
2.32.0
next prev parent reply other threads:[~2021-09-21 2:44 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-20 18:11 [PATCH v12 00/35] NVIDIA Tegra power management patches for 5.16 Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 01/35] opp: Change type of dev_pm_opp_attach_genpd(names) argument Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 02/35] soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 03/35] soc/tegra: pmc: Disable PMC state syncing Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 04/35] soc/tegra: Don't print error message when OPPs not available Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 05/35] dt-bindings: clock: tegra-car: Document new clock sub-nodes Dmitry Osipenko
2021-09-23 21:09 ` Rob Herring
2021-10-15 0:16 ` Stephen Boyd
2021-10-15 0:43 ` Dmitry Osipenko
2021-10-15 0:45 ` Stephen Boyd
2021-10-15 1:02 ` Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 06/35] clk: tegra: Support runtime PM and power domain Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 07/35] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 08/35] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 09/35] gpu: host1x: Add runtime PM and OPP support Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 10/35] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 11/35] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 12/35] drm/tegra: hdmi: Add OPP support Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 13/35] drm/tegra: gr2d: Support generic power domain and runtime PM Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 14/35] drm/tegra: gr3d: " Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 15/35] drm/tegra: vic: Support system suspend Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 16/35] usb: chipidea: tegra: Add runtime PM and OPP support Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 17/35] bus: tegra-gmi: " Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 18/35] pwm: tegra: " Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 19/35] mmc: sdhci-tegra: " Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 20/35] mtd: rawnand: tegra: " Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 21/35] spi: tegra20-slink: Add " Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 22/35] media: dt: bindings: tegra-vde: Convert to schema Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 23/35] media: dt: bindings: tegra-vde: Document OPP and power domain Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 24/35] media: staging: tegra-vde: Support generic " Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 25/35] soc/tegra: fuse: Reset hardware Dmitry Osipenko
2021-09-20 18:11 ` Dmitry Osipenko [this message]
2021-09-20 18:11 ` [PATCH v12 27/35] soc/tegra: regulators: Prepare for suspend Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 28/35] soc/tegra: pmc: Rename 3d power domains Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 29/35] soc/tegra: pmc: Rename core power domain Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 30/35] soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30 Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 31/35] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 32/35] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 33/35] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 34/35] ARM: tegra: Add Memory Client resets to Tegra30 " Dmitry Osipenko
2021-09-20 18:11 ` [PATCH v12 35/35] ARM: tegra20/30: Disable unused host1x hardware Dmitry Osipenko
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