[PATCH v2 0/5] H3/M3-W cpuidle support

[PATCH v2 0/5] H3/M3-W cpuidle support

[Ulrich Hecht]

Hi!

This series adds CPU idle support for H3 and M3-W. It's a straight up-port
from the BSP.  This revision removes the superfluous status properties from
the idle states and fixes Khiem's e-mail address.

I don't think we have any information on whether all M3ULCB boards have an
ES1.0 SoC yet, do we?

CU
Uli


Dien Pham (2):
  arm64: dts: r8a7795: Add cpuidle support for CA53 cores
  arm64: dts: r8a7796: Add cpuidle support for CA53 cores

Khiem Nguyen (2):
  arm64: dts: r8a7795: Add cpuidle support for CA57 cores
  arm64: dts: r8a7796: Add cpuidle support for CA57 cores

Takeshi Kihara (1):
  arm64: dts: r8a7796-m3ulcb: Disable cpuidle support for CA53 cores

 arch/arm64/boot/dts/renesas/r8a7795.dtsi       | 30 ++++++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 22 +++++++++++++++++++
 arch/arm64/boot/dts/renesas/r8a7796.dtsi       | 28 ++++++++++++++++++++++++
 3 files changed, 80 insertions(+)

-- 
2.7.4

[PATCH v2 1/5] arm64: dts: r8a7795: Add cpuidle support for CA57 cores

[Ulrich Hecht]

From: Khiem Nguyen <khiem.nguyen.xt@renesas.com>

Enable cpuidle (core shutdown) support for R-Car H3 CA57 cores.

Parameters were found after evaluation by gaku.inami.xw@bp.renesas.com; they
help to keep the performance and reduce the power consumption.

Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
[dien.pham.ry: Apply new cpuidle parameters]
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index a81ed2b..7ae974d 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -155,6 +155,7 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -168,6 +169,7 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -181,6 +183,7 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -194,6 +197,7 @@
 			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -261,6 +265,19 @@
 			cache-unified;
 			cache-level = <2>;
 		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <400>;
+				exit-latency-us = <500>;
+				min-residency-us = <4000>;
+			};
+		};
 	};
 
 	extal_clk: extal {
-- 
2.7.4

Re: [PATCH v2 1/5] arm64: dts: r8a7795: Add cpuidle support for CA57 cores

[Geert Uytterhoeven]

On Fri, Jan 18, 2019 at 11:48 AM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> From: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
>
> Enable cpuidle (core shutdown) support for R-Car H3 CA57 cores.
>
> Parameters were found after evaluation by gaku.inami.xw@bp.renesas.com; they
> help to keep the performance and reduce the power consumption.
>
> Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
> [dien.pham.ry: Apply new cpuidle parameters]
> Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores

[Ulrich Hecht]

From: Dien Pham <dien.pham.ry@renesas.com>

Enables cpuidle (core shutdown) support for R-Car H3 CA53 cores.

Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 7ae974d..483ba3b 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -211,6 +211,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -223,6 +224,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -235,6 +237,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -247,6 +250,7 @@
 			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -277,6 +281,15 @@
 				exit-latency-us = <500>;
 				min-residency-us = <4000>;
 			};
+
+			CPU_SLEEP_1: cpu-sleep-1 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <700>;
+				exit-latency-us = <700>;
+				min-residency-us = <5000>;
+			};
 		};
 	};
 
-- 
2.7.4

Re: [PATCH v2 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores

[Eugeniu Rosca]

On Fri, Jul 26, 2019 at 11:13:29AM +0200, Rosca, Eugeniu (ADITG/ESM1) wrote:
[..]
> The culprit BSP commits are:
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?id=3c3b44c752c4ee
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?id=902ff7caa32dc71c
> 
> Further narrowing it down, it turns out the CA57 cpuidle support is
> not responsible for generating the issue. It's all about the CA53 idle
> enablement. The reference target is H3-ES2.0-Salvator-X (the problem
> originally emerged on M3-based customer HW).
[..]

Small amendment to the above (based on vanilla testing):

 Version                              Issue reproduced?
                                      (H3-ES2.0-Salvator-X)
 v5.3-rc1-96-g6789f873ed37              No
 v5.3-rc1-96-g6789f873ed37 + [1]        No
 v5.3-rc1-96-g6789f873ed37 + [2]        No
 v5.3-rc1-96-g6789f873ed37 + [1] + [2]  Yes

[1] https://patchwork.kernel.org/patch/10769701/
("[v2,1/5] arm64: dts: r8a7795: Add cpuidle support for CA57 cores")

[2] https://patchwork.kernel.org/patch/10769689/
("[v2,2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores")

-- 
Best Regards,
Eugeniu.

Re: [PATCH v2 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores

[Geert Uytterhoeven]

Hi Eugniu,

CC cpuidle people

On Fri, Jul 26, 2019 at 11:47 AM Eugeniu Rosca <erosca@de.adit-jv.com> wrote:
> On Fri, Jul 26, 2019 at 11:13:29AM +0200, Rosca, Eugeniu (ADITG/ESM1) wrote:
> [..]
> > The culprit BSP commits are:
> > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?id=3c3b44c752c4ee
> > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?id=902ff7caa32dc71c
> >
> > Further narrowing it down, it turns out the CA57 cpuidle support is
> > not responsible for generating the issue. It's all about the CA53 idle
> > enablement. The reference target is H3-ES2.0-Salvator-X (the problem
> > originally emerged on M3-based customer HW).
> [..]
>
> Small amendment to the above (based on vanilla testing):
>
>  Version                              Issue reproduced?
>                                       (H3-ES2.0-Salvator-X)
>  v5.3-rc1-96-g6789f873ed37              No
>  v5.3-rc1-96-g6789f873ed37 + [1]        No
>  v5.3-rc1-96-g6789f873ed37 + [2]        No
>  v5.3-rc1-96-g6789f873ed37 + [1] + [2]  Yes
>
> [1] https://patchwork.kernel.org/patch/10769701/
> ("[v2,1/5] arm64: dts: r8a7795: Add cpuidle support for CA57 cores")
>
> [2] https://patchwork.kernel.org/patch/10769689/
> ("[v2,2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores")

Thanks for your report and investigation!

Unfortunately your original report didn't make it to lore.kernel.org, and
probably also not to the list, due to the large audio attachment.

For the newly CCed people, the issue is about consistent dropouts during
audio playback using an in-house application, introduced by adding cpuidle
support to _both_ the big and LITTLE cores.

Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores

[Lorenzo Pieralisi]

On Mon, Jul 29, 2019 at 09:44:52AM +0200, Geert Uytterhoeven wrote:
> Hi Eugniu,
> 
> CC cpuidle people
> 
> On Fri, Jul 26, 2019 at 11:47 AM Eugeniu Rosca <erosca@de.adit-jv.com> wrote:
> > On Fri, Jul 26, 2019 at 11:13:29AM +0200, Rosca, Eugeniu (ADITG/ESM1) wrote:
> > [..]
> > > The culprit BSP commits are:
> > > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?id=3c3b44c752c4ee
> > > https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git/commit/?id=902ff7caa32dc71c
> > >
> > > Further narrowing it down, it turns out the CA57 cpuidle support is
> > > not responsible for generating the issue. It's all about the CA53 idle
> > > enablement. The reference target is H3-ES2.0-Salvator-X (the problem
> > > originally emerged on M3-based customer HW).
> > [..]
> >
> > Small amendment to the above (based on vanilla testing):
> >
> >  Version                              Issue reproduced?
> >                                       (H3-ES2.0-Salvator-X)
> >  v5.3-rc1-96-g6789f873ed37              No
> >  v5.3-rc1-96-g6789f873ed37 + [1]        No
> >  v5.3-rc1-96-g6789f873ed37 + [2]        No
> >  v5.3-rc1-96-g6789f873ed37 + [1] + [2]  Yes
> >
> > [1] https://patchwork.kernel.org/patch/10769701/
> > ("[v2,1/5] arm64: dts: r8a7795: Add cpuidle support for CA57 cores")
> >
> > [2] https://patchwork.kernel.org/patch/10769689/
> > ("[v2,2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores")
> 
> Thanks for your report and investigation!
> 
> Unfortunately your original report didn't make it to lore.kernel.org, and
> probably also not to the list, due to the large audio attachment.
> 
> For the newly CCed people, the issue is about consistent dropouts
> during audio playback using an in-house application, introduced by
> adding cpuidle support to _both_ the big and LITTLE cores.

CPUidle entry/exit latencies are certainly bringing the issue
about, I am not an audio expert but I suspect buffering should
be tuned to cope with those _increased_ latencies or possibly
idle states disabled for certain specific use cases - there
is no silver bullet, entering deep idle states will increase
latencies, there is no way around it.

I am happy to help you debug the issue further.

Lorenzo

Re: [PATCH v2 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores

[Eugeniu Rosca]

Hello Geert, hello Lorenzo,

Many thanks for your comments and for the willingness to help.

For your information, we've recently discovered that, with all the
findings already described being absolutely valid for the reference
targets, disabling CPUidle on the customer HW is apparently not enough
to fix the audio dropouts. We will first try to identify those
differences (both HW and SW) which keep the issue reproducible on the
customer boards. Once this is hopefully understood, we'll come back
with feedback.

This investigation also happens to overlap with my vacation. Hence I
plan to update you on this topic in 2-4 weeks from now.

Thanks again.

Best regards,
Eugeniu.

Re: [PATCH v2 2/5] arm64: dts: r8a7795: Add cpuidle support for CA53 cores

[Geert Uytterhoeven]

On Fri, Jan 18, 2019 at 11:48 AM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> From: Dien Pham <dien.pham.ry@renesas.com>
>
> Enables cpuidle (core shutdown) support for R-Car H3 CA53 cores.
>
> Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 3/5] arm64: dts: r8a7796: Add cpuidle support for CA57 cores

[Ulrich Hecht]

From: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>

Enable cpuidle (core shutdown) support for R-Car M3-W CA57 cores.

Parameters were found after evaluation by gaku.inami.xw@bp.renesas.com; they
help to keep the performance and reduce the power consumption.

Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[dien.pham.ry: Apply new cpuidle parameters]
Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 3a9f8c7..212ffd6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -160,6 +160,7 @@
 			power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -173,6 +174,7 @@
 			power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
 			next-level-cache = <&L2_CA57>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_0>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
 			operating-points-v2 = <&cluster0_opp>;
 			capacity-dmips-mhz = <1024>;
@@ -240,6 +242,19 @@
 			cache-unified;
 			cache-level = <2>;
 		};
+
+		idle-states {
+			entry-method = "psci";
+
+			CPU_SLEEP_0: cpu-sleep-0 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <400>;
+				exit-latency-us = <500>;
+				min-residency-us = <4000>;
+			};
+		};
 	};
 
 	extal_clk: extal {
-- 
2.7.4

Re: [PATCH v2 3/5] arm64: dts: r8a7796: Add cpuidle support for CA57 cores

[Geert Uytterhoeven]

On Fri, Jan 18, 2019 at 11:48 AM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> From: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
>
> Enable cpuidle (core shutdown) support for R-Car M3-W CA57 cores.
>
> Parameters were found after evaluation by gaku.inami.xw@bp.renesas.com; they
> help to keep the performance and reduce the power consumption.
>
> Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@rvc.renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [dien.pham.ry: Apply new cpuidle parameters]
> Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 4/5] arm64: dts: r8a7796: Add cpuidle support for CA53 cores

[Ulrich Hecht]

From: Dien Pham <dien.pham.ry@renesas.com>

Enable cpuidle (core shutdown) support for R-Car M3-W CA53 cores.

Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 212ffd6..81af1ee 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -188,6 +188,7 @@
 			power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -200,6 +201,7 @@
 			power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -212,6 +214,7 @@
 			power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -224,6 +227,7 @@
 			power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
 			next-level-cache = <&L2_CA53>;
 			enable-method = "psci";
+			cpu-idle-states = <&CPU_SLEEP_1>;
 			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
 			operating-points-v2 = <&cluster1_opp>;
 			capacity-dmips-mhz = <535>;
@@ -254,6 +258,15 @@
 				exit-latency-us = <500>;
 				min-residency-us = <4000>;
 			};
+
+			CPU_SLEEP_1: cpu-sleep-1 {
+				compatible = "arm,idle-state";
+				arm,psci-suspend-param = <0x0010000>;
+				local-timer-stop;
+				entry-latency-us = <700>;
+				exit-latency-us = <700>;
+				min-residency-us = <5000>;
+			};
 		};
 	};
 
-- 
2.7.4

Re: [PATCH v2 4/5] arm64: dts: r8a7796: Add cpuidle support for CA53 cores

[Geert Uytterhoeven]

On Fri, Jan 18, 2019 at 11:48 AM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> From: Dien Pham <dien.pham.ry@renesas.com>
>
> Enable cpuidle (core shutdown) support for R-Car M3-W CA53 cores.
>
> Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 5/5] arm64: dts: r8a7796-m3ulcb: Disable cpuidle support for CA53 cores

[Ulrich Hecht]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

The revision of the R8A7796 SoC on the M3ULCB board is ES1.0. This revision
can not use cpuidle for CA53 cores.

Therefore, this patch disables cpuidle support for CA53 cores.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
---
 arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 9e4594c..cf96675 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -14,6 +14,12 @@
 	model = "Renesas M3ULCB board based on r8a7796";
 	compatible = "renesas,m3ulcb", "renesas,r8a7796";
 
+	cpus {
+		idle-states {
+			/delete-node/ cpu-sleep-1;
+		};
+	};
+
 	memory@48000000 {
 		device_type = "memory";
 		/* first 128MB is reserved for secure area. */
@@ -26,6 +32,22 @@
 	};
 };
 
+&a53_0 {
+	/delete-property/ cpu-idle-states;
+};
+
+&a53_1 {
+	/delete-property/ cpu-idle-states;
+};
+
+&a53_2 {
+	/delete-property/ cpu-idle-states;
+};
+
+&a53_3 {
+	/delete-property/ cpu-idle-states;
+};
+
 &du {
 	clocks = <&cpg CPG_MOD 724>,
 		 <&cpg CPG_MOD 723>,
-- 
2.7.4

Re: [PATCH v2 0/5] H3/M3-W cpuidle support

[Geert Uytterhoeven]

Hi Uli,

(Replying to an old series, now we have received more background
 information)

On Fri, Jan 18, 2019 at 11:48 AM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> This series adds CPU idle support for H3 and M3-W. It's a straight up-port
> from the BSP.  This revision removes the superfluous status properties from
> the idle states and fixes Khiem's e-mail address.

> Dien Pham (2):
>   arm64: dts: r8a7795: Add cpuidle support for CA53 cores
>   arm64: dts: r8a7796: Add cpuidle support for CA53 cores
>
> Khiem Nguyen (2):
>   arm64: dts: r8a7795: Add cpuidle support for CA57 cores
>   arm64: dts: r8a7796: Add cpuidle support for CA57 cores

Thanks for the update!

I took the liberty to create a topic branch[1] for the first 4 patches,
and include it in yesterday's renesas-drivers-2019-08-27-v5.3-rc6.

> I don't think we have any information on whether all M3ULCB boards have an
> ES1.0 SoC yet, do we?

> Takeshi Kihara (1):
>   arm64: dts: r8a7796-m3ulcb: Disable cpuidle support for CA53 cores

This is just one possible mitigation for a system controller issue, to
prevent conflicts between powering off CPU cores or the 3D Graphics
Engine, and changing the state of another power domain through SYSC,
which could lead to CPG state machine lock-ups.
Other mitigations are to make use of the new System Controller External
Request Mask Register[2], present in newer SoCs and SoC revisions, or to
keep some power areas always powered.

However, we believe this issue cannot happen in the upstream kernel, as
upstream has no support for graphics acceleration yet.

Hence I think this series (modulo the last patch) is ready to be queued
in renesas-devel for v5.5.

Thanks for your comments!

[1] git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#topic/rcar3-cpuidle-v2
[2] "[PATCH v2 0/7] soc: renesas: rcar-gen3-sysc: Fix power request conflicts"
    (https://lore.kernel.org/linux-renesas-soc/20190828113618.6672-1-geert+renesas@glider.be/)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 0/5] H3/M3-W cpuidle support

[Geert Uytterhoeven]

On Wed, Aug 28, 2019 at 2:04 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> (Replying to an old series, now we have received more background
>  information)
>
> On Fri, Jan 18, 2019 at 11:48 AM Ulrich Hecht <uli+renesas@fpond.eu> wrote:
> > This series adds CPU idle support for H3 and M3-W. It's a straight up-port
> > from the BSP.  This revision removes the superfluous status properties from
> > the idle states and fixes Khiem's e-mail address.
>
> > Dien Pham (2):
> >   arm64: dts: r8a7795: Add cpuidle support for CA53 cores
> >   arm64: dts: r8a7796: Add cpuidle support for CA53 cores
> >
> > Khiem Nguyen (2):
> >   arm64: dts: r8a7795: Add cpuidle support for CA57 cores
> >   arm64: dts: r8a7796: Add cpuidle support for CA57 cores

> > Takeshi Kihara (1):
> >   arm64: dts: r8a7796-m3ulcb: Disable cpuidle support for CA53 cores

> Hence I think this series (modulo the last patch) is ready to be queued
> in renesas-devel for v5.5.

First 4 patches queued.


Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds