[PATCH 00/12] Add USB2.0 support

[PATCH 00/12] Add USB2.0 support

[Biju Das]

This series adds USB 2.0 support for the RZ/G1C SoC. RZ/G1C
SoC is similar to R-Car Gen2 SoC, but there are some differences

- It has a shared pll reset register for hsusb0/hsusb1 and this register 
  reside in hsusb0 block.

- Each USB host needs to deassert the pll reset of hsusb block apart from
  initializing interrupt enable,OVC detection timer and suspend/resume timer
  register.

To address the above scenarios, created a ehci-r8a77470 host controller
driver.

This patchset is based on linux_next next-20190401 branch.

V1-->V2
 * Incorporated Rob's review comment
   Ref: https://patchwork.kernel.org/patch/10655853/
 * Incorporated Shimoda-San's review comment
   Ref: https://patchwork.kernel.org/patch/10655855/
 * Created ehci-r8a77470 host driver.

Biju Das (12):
  dt-bindings: phy: rcar-gen2: Add r8a77470 support
  phy: renesas: phy-rcar-gen2: Add support for r8a77470
  dt-bindings: usb: ehci-r8a77470 devicetree binding document
  usb: host: ehci-r8a77470: Add EHCI support for Renesas RZ/G1C devices
  ARM: shmobile: Enable USB [EO]HCI HCD PLATFORM support in
    shmobile_defconfig
  dt-bindings: usb: renesas_usbhs: Add support for r8a77470
  ARM: dts: r8a77470: Add USB PHY DT support
  ARM: dts: iwg23s-sbc: Enable USB Phy[01]
  ARM: dts: r8a77470: Add USB2.0 Host (EHCI/OHCI) device
  ARM: dts: iwg23s-sbc: Enable USB USB2.0 Host
  ARM: dts: r8a77470: Add HSUSB device nodes
  ARM: dts: iwg23s-sbc: Enable HS-USB

 .../devicetree/bindings/phy/rcar-gen2-phy.txt      |  57 +++-
 .../devicetree/bindings/usb/ehci-r8a77470.txt      |  35 +++
 .../devicetree/bindings/usb/renesas_usbhs.txt      |   1 +
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts          |  36 +++
 arch/arm/boot/dts/r8a77470.dtsi                    | 121 ++++++++
 arch/arm/configs/shmobile_defconfig                |   2 +
 drivers/phy/renesas/phy-rcar-gen2.c                |  88 +++++-
 drivers/usb/host/Kconfig                           |   9 +
 drivers/usb/host/Makefile                          |   1 +
 drivers/usb/host/ehci-r8a77470.c                   | 327 +++++++++++++++++++++
 10 files changed, 671 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/ehci-r8a77470.txt
 create mode 100644 drivers/usb/host/ehci-r8a77470.c

-- 
2.7.4

[PATCH 01/12] dt-bindings: phy: rcar-gen2: Add r8a77470 support

[Biju Das]

Add USB PHY support for r8a77470 SoC. Renesas RZ/G1C (R8A77470)
USB PHY is similar to the R-Car Gen2 family, but has the below
feature compared to other RZ/G1 and R-Car Gen2/3 SoCs

It has a shared pll reset for usbphy0/usbphy1 and this register
reside in usbphy0 block.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
V1-->V2
  * Incorporated Rob's review comment
    https://patchwork.kernel.org/patch/10655853/
---
 .../devicetree/bindings/phy/rcar-gen2-phy.txt      | 57 ++++++++++++++++++++--
 1 file changed, 53 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
index 4f0879a..ac96d64 100644
--- a/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rcar-gen2-phy.txt
@@ -7,6 +7,7 @@ Required properties:
 - compatible: "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC.
 	      "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC.
 	      "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC.
+	      "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC.
 	      "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC.
 	      "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC.
 	      "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC.
@@ -30,7 +31,7 @@ channels. These subnodes must contain the following properties:
 - #phy-cells: see phy-bindings.txt in the same directory, must be <1>.
 
 The phandle's argument in the PHY specifier is the USB controller selector for
-the USB channel; see the selector meanings below:
+the USB channel other than r8a77470 SoC; see the selector meanings below:
 
 +-----------+---------------+---------------+
 |\ Selector |               |               |
@@ -41,6 +42,16 @@ the USB channel; see the selector meanings below:
 | 2         | PCI EHCI/OHCI | xHCI          |
 +-----------+---------------+---------------+
 
+For r8a77470 SoC;see the selector meaning below:
+
++-----------+---------------+---------------+
+|\ Selector |               |               |
++ --------- +       0       |       1       |
+| Channel  \|               |               |
++-----------+---------------+---------------+
+| 0         | EHCI/OHCI     | HS-USB        |
++-----------+---------------+---------------+
+
 Example (Lager board):
 
 	usb-phy@e6590100 {
@@ -48,15 +59,53 @@ Example (Lager board):
 		reg = <0 0xe6590100 0 0x100>;
 		#address-cells = <1>;
 		#size-cells = <0>;
-		clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
+		clocks = <&cpg CPG_MOD 704>;
 		clock-names = "usbhs";
+		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+		resets = <&cpg 704>;
 
-		usb-channel@0 {
+		usb0: usb-channel@0 {
 			reg = <0>;
 			#phy-cells = <1>;
 		};
-		usb-channel@2 {
+		usb2: usb-channel@2 {
 			reg = <2>;
 			#phy-cells = <1>;
 		};
 	};
+
+Example (iWave RZ/G1C sbc):
+
+	usbphy0: usb-phy0@e6590100 {
+		compatible = "renesas,usb-phy-r8a77470",
+			     "renesas,rcar-gen2-usb-phy";
+		reg = <0 0xe6590100 0 0x100>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cpg CPG_MOD 704>;
+		clock-names = "usbhs";
+		power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+		resets = <&cpg 704>;
+
+		usb0: usb-channel@0 {
+			reg = <0>;
+			#phy-cells = <1>;
+		};
+	};
+
+	usbphy1: usb-phy@e6598100 {
+		compatible = "renesas,usb-phy-r8a77470",
+			     "renesas,rcar-gen2-usb-phy";
+		reg = <0 0xe6598100 0 0x100>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&cpg CPG_MOD 706>;
+		clock-names = "usbhs";
+		power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+		resets = <&cpg 706>;
+
+		usb1: usb-channel@0 {
+			reg = <0>;
+			#phy-cells = <1>;
+		};
+	};
-- 
2.7.4

[PATCH 02/12] phy: renesas: phy-rcar-gen2: Add support for r8a77470

[Biju Das]

This patch adds support for RZ/G1C (r8a77470) SoC. RZ/G1C SoC has a
PLL register shared between hsusb0 and hsusb1. Compared to other RZ/G1
and R-Car Gen2/3, USB Host needs to deassert the pll reset.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
V1-->V2
 * Incorporated shimoda-san's review comment
 Ref: https://patchwork.kernel.org/patch/10655855/
---
 drivers/phy/renesas/phy-rcar-gen2.c | 88 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 86 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/renesas/phy-rcar-gen2.c b/drivers/phy/renesas/phy-rcar-gen2.c
index 72eeb06..4dfab93 100644
--- a/drivers/phy/renesas/phy-rcar-gen2.c
+++ b/drivers/phy/renesas/phy-rcar-gen2.c
@@ -4,6 +4,7 @@
  *
  * Copyright (C) 2014 Renesas Solutions Corp.
  * Copyright (C) 2014 Cogent Embedded, Inc.
+ * Copyright (C) 2019 Renesas Electronics Corp.
  */
 
 #include <linux/clk.h>
@@ -15,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/atomic.h>
+#include <linux/sys_soc.h>
 
 #define USBHS_LPSTS			0x02
 #define USBHS_UGCTRL			0x80
@@ -35,6 +37,8 @@
 #define USBHS_UGCTRL2_USB0SEL		0x00000030
 #define USBHS_UGCTRL2_USB0SEL_PCI	0x00000010
 #define USBHS_UGCTRL2_USB0SEL_HS_USB	0x00000030
+#define USBHS_UGCTRL2_USB0SEL_USB20	0x00000010
+#define USBHS_UGCTRL2_USB0SEL_HS_USB20	0x00000020
 
 /* USB General status register (UGSTS) */
 #define USBHS_UGSTS_LOCK		0x00000100 /* From technical update */
@@ -180,6 +184,60 @@ static int rcar_gen2_phy_power_off(struct phy *p)
 	return 0;
 }
 
+static int rz_g1c_phy_power_on(struct phy *p)
+{
+	struct rcar_gen2_phy *phy = phy_get_drvdata(p);
+	struct rcar_gen2_phy_driver *drv = phy->channel->drv;
+	void __iomem *base = drv->base;
+	unsigned long flags;
+	u32 value;
+
+	spin_lock_irqsave(&drv->lock, flags);
+
+	/* Power on USBHS PHY */
+	value = readl(base + USBHS_UGCTRL);
+	value &= ~USBHS_UGCTRL_PLLRESET;
+	writel(value, base + USBHS_UGCTRL);
+
+	/* As per the data sheet wait 340 micro sec for power stable */
+	udelay(340);
+
+	if (phy->select_value == USBHS_UGCTRL2_USB0SEL_HS_USB20) {
+		value = readw(base + USBHS_LPSTS);
+		value |= USBHS_LPSTS_SUSPM;
+		writew(value, base + USBHS_LPSTS);
+	}
+
+	spin_unlock_irqrestore(&drv->lock, flags);
+
+	return 0;
+}
+
+static int rz_g1c_phy_power_off(struct phy *p)
+{
+	struct rcar_gen2_phy *phy = phy_get_drvdata(p);
+	struct rcar_gen2_phy_driver *drv = phy->channel->drv;
+	void __iomem *base = drv->base;
+	unsigned long flags;
+	u32 value;
+
+	spin_lock_irqsave(&drv->lock, flags);
+	/* Power off USBHS PHY */
+	if (phy->select_value == USBHS_UGCTRL2_USB0SEL_HS_USB20) {
+		value = readw(base + USBHS_LPSTS);
+		value &= ~USBHS_LPSTS_SUSPM;
+		writew(value, base + USBHS_LPSTS);
+	}
+
+	value = readl(base + USBHS_UGCTRL);
+	value |= USBHS_UGCTRL_PLLRESET;
+	writel(value, base + USBHS_UGCTRL);
+
+	spin_unlock_irqrestore(&drv->lock, flags);
+
+	return 0;
+}
+
 static const struct phy_ops rcar_gen2_phy_ops = {
 	.init		= rcar_gen2_phy_init,
 	.exit		= rcar_gen2_phy_exit,
@@ -188,6 +246,14 @@ static const struct phy_ops rcar_gen2_phy_ops = {
 	.owner		= THIS_MODULE,
 };
 
+static const struct phy_ops rz_g1c_phy_ops = {
+	.init		= rcar_gen2_phy_init,
+	.exit		= rcar_gen2_phy_exit,
+	.power_on	= rz_g1c_phy_power_on,
+	.power_off	= rz_g1c_phy_power_off,
+	.owner		= THIS_MODULE,
+};
+
 static const struct of_device_id rcar_gen2_phy_match_table[] = {
 	{ .compatible = "renesas,usb-phy-r8a7790" },
 	{ .compatible = "renesas,usb-phy-r8a7791" },
@@ -224,11 +290,22 @@ static const u32 select_mask[] = {
 	[2]	= USBHS_UGCTRL2_USB2SEL,
 };
 
-static const u32 select_value[][PHYS_PER_CHANNEL] = {
+static const u32 pci_select_value[][PHYS_PER_CHANNEL] = {
 	[0]	= { USBHS_UGCTRL2_USB0SEL_PCI, USBHS_UGCTRL2_USB0SEL_HS_USB },
 	[2]	= { USBHS_UGCTRL2_USB2SEL_PCI, USBHS_UGCTRL2_USB2SEL_USB30 },
 };
 
+static const u32 usb20_select_value[][PHYS_PER_CHANNEL] = {
+	{ USBHS_UGCTRL2_USB0SEL_USB20, USBHS_UGCTRL2_USB0SEL_HS_USB20 },
+};
+
+static struct soc_device_attribute soc_r8a77470[] = {
+	{
+		.soc_id = "r8a77470",
+	},
+	{ /* sentinel */ }
+};
+
 static int rcar_gen2_phy_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -238,6 +315,8 @@ static int rcar_gen2_phy_probe(struct platform_device *pdev)
 	struct resource *res;
 	void __iomem *base;
 	struct clk *clk;
+	const struct phy_ops *gen2_phy_ops = &rcar_gen2_phy_ops;
+	const u32 (*select_value)[PHYS_PER_CHANNEL]  = pci_select_value;
 	int i = 0;
 
 	if (!dev->of_node) {
@@ -266,6 +345,11 @@ static int rcar_gen2_phy_probe(struct platform_device *pdev)
 	drv->clk = clk;
 	drv->base = base;
 
+	if (soc_device_match(soc_r8a77470)) {
+		select_value = usb20_select_value;
+		gen2_phy_ops = &rz_g1c_phy_ops;
+	}
+
 	drv->num_channels = of_get_child_count(dev->of_node);
 	drv->channels = devm_kcalloc(dev, drv->num_channels,
 				     sizeof(struct rcar_gen2_channel),
@@ -297,7 +381,7 @@ static int rcar_gen2_phy_probe(struct platform_device *pdev)
 			phy->select_value = select_value[channel_num][n];
 
 			phy->phy = devm_phy_create(dev, NULL,
-						   &rcar_gen2_phy_ops);
+						   gen2_phy_ops);
 			if (IS_ERR(phy->phy)) {
 				dev_err(dev, "Failed to create PHY\n");
 				return PTR_ERR(phy->phy);
-- 
2.7.4

[PATCH 03/12] dt-bindings: usb: ehci-r8a77470 devicetree binding document

[Biju Das]

Add device tree binding document for Renesas r8a77470(a.k.a RZ/G1C)
on-chip EHCI controller driver.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
V1-->V2
  * New patch
---
 .../devicetree/bindings/usb/ehci-r8a77470.txt      | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/ehci-r8a77470.txt

diff --git a/Documentation/devicetree/bindings/usb/ehci-r8a77470.txt b/Documentation/devicetree/bindings/usb/ehci-r8a77470.txt
new file mode 100644
index 0000000..4646adcf
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ehci-r8a77470.txt
@@ -0,0 +1,35 @@
+Renesas R8A77470(RZ/G1C) USB EHCI controller
+
+Required properties:
+ - compatible		: must be "renesas,r8a77470"
+ - reg			: physical base addresses of the controller and length
+			  of memory mapped region
+ - interrupts		: one EHCI interrupt should be described here
+ - clocks		: a list of phandle + clock specifier pairs.
+ - phys			: see usb-hcd.txt in the current directory
+ - resets		: phandle + reset specifier pair
+
+Additionally the properties from usb-hcd.txt (in the current directory) are
+supported.
+
+Example:
+
+	ehci0: usb@ee080100 {
+		compatible = "renesas,ehci-r8a77470";
+		reg = <0 0xee080100 0 0x800>;
+		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cpg CPG_MOD 703>;
+		phys = <&usb0 0>;
+		phy-names = "usb";
+		resets = <&cpg 703>;
+	};
+
+	ehci1: usb@ee0c0100 {
+		compatible = "renesas,ehci-r8a77470";
+		reg = <0 0xee0c0100 0 0x800>;
+		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cpg CPG_MOD 705>;
+		phys = <&usb0 1>, <&usb1 0>;
+		phy-names = "usb";
+		resets = <&cpg 705>;
+	};
-- 
2.7.4

[PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for Renesas RZ/G1C devices

[Biju Das]

This patch adds the glue code required to ensure the on-chip EHCI
controller works on RZ/G1C(a.k.a R8A77470) SoC's from Renesas.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
V1-->V2
  * New patch
---
 drivers/usb/host/Kconfig         |   9 ++
 drivers/usb/host/Makefile        |   1 +
 drivers/usb/host/ehci-r8a77470.c | 327 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 337 insertions(+)
 create mode 100644 drivers/usb/host/ehci-r8a77470.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index d809671..a474aa9 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -237,6 +237,15 @@ config USB_EHCI_HCD_STI
 	  Enable support for the on-chip EHCI controller found on
 	  STMicroelectronics consumer electronics SoC's.
 
+config USB_EHCI_HCD_R8A77470
+	tristate "Support for Renesas R8A77470 on-chip EHCI USB controller"
+	depends on ARCH_R8A77470 && OF
+	select GENERIC_PHY
+	select USB_EHCI_HCD_PLATFORM
+	help
+	  Enable support for the on-chip EHCI controller found on
+	  Renesas RZ/G1C(R8A77470) SoC's.
+
 config USB_EHCI_HCD_AT91
         tristate  "Support for Atmel on-chip EHCI USB controller"
         depends on USB_EHCI_HCD && ARCH_AT91
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 84514f7..785a1d1 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_USB_EHCI_HCD_OMAP)	+= ehci-omap.o
 obj-$(CONFIG_USB_EHCI_HCD_ORION)	+= ehci-orion.o
 obj-$(CONFIG_USB_EHCI_HCD_SPEAR)	+= ehci-spear.o
 obj-$(CONFIG_USB_EHCI_HCD_STI)	+= ehci-st.o
+obj-$(CONFIG_USB_EHCI_HCD_R8A77470)	+= ehci-r8a77470.o
 obj-$(CONFIG_USB_EHCI_EXYNOS)	+= ehci-exynos.o
 obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o
 obj-$(CONFIG_USB_EHCI_TEGRA)	+= ehci-tegra.o
diff --git a/drivers/usb/host/ehci-r8a77470.c b/drivers/usb/host/ehci-r8a77470.c
new file mode 100644
index 0000000..d57f6f1
--- /dev/null
+++ b/drivers/usb/host/ehci-r8a77470.c
@@ -0,0 +1,327 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas R8A77470 ehci driver
+ *
+ * Copyright (C) 2019 Renesas Electronics Corp.
+ *
+ * Derived from ehci-platform.c
+ */
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/hrtimer.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/of.h>
+
+#include "ehci.h"
+
+/******* USB2.0 Host registers (original offset is +0x100) *******/
+#define USB2_INT_ENABLE			0x100
+#define USB2_SPD_RSM_TIMSET		0x20c
+#define USB2_OC_TIMSET			0x210
+
+#define USB2_INT_ENABLE_USBH_INTB_EN	BIT(2)
+#define USB2_INT_ENABLE_USBH_INTA_EN	BIT(1)
+#define USB2_INT_ENABLE_INIT		(USB2_INT_ENABLE_USBH_INTB_EN | \
+					 USB2_INT_ENABLE_USBH_INTA_EN)
+
+#define USB2_SPD_RSM_TIMSET_INIT	0x014e029b
+#define USB2_OC_TIMSET_INIT		0x000209ab
+
+#define DRIVER_DESC "EHCI renesas r8a77470 driver"
+#define EHCI_MAX_CLKS 4
+#define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
+
+struct ehci_platform_priv {
+	struct clk *clks[EHCI_MAX_CLKS];
+	struct reset_control *rsts;
+	bool reset_on_resume;
+};
+
+static const char hcd_name[] = "ehci-r8a77470";
+
+static int r8a77470_ehci_platform_reset(struct usb_hcd *hcd)
+{
+	struct platform_device *pdev = to_platform_device(hcd->self.controller);
+	struct usb_ehci_pdata *pdata = dev_get_platdata(&pdev->dev);
+	struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+	ehci->caps = hcd->regs + pdata->caps_offset;
+	return ehci_setup(hcd);
+}
+
+static int r8a77470_ehci_platform_power_on(struct platform_device *dev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(dev);
+	struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
+	int clk, ret;
+
+	for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) {
+		ret = clk_prepare_enable(priv->clks[clk]);
+		if (ret)
+			goto err_disable_clks;
+	}
+
+	writel(USB2_INT_ENABLE_INIT, hcd->regs + USB2_INT_ENABLE);
+	writel(USB2_SPD_RSM_TIMSET_INIT, hcd->regs + USB2_SPD_RSM_TIMSET);
+	writel(USB2_OC_TIMSET_INIT, hcd->regs + USB2_OC_TIMSET);
+	return 0;
+
+err_disable_clks:
+	while (--clk >= 0)
+		clk_disable_unprepare(priv->clks[clk]);
+
+	return ret;
+}
+
+static void r8a77470_ehci_platform_power_off(struct platform_device *dev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(dev);
+	struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
+	int clk;
+
+	writel(0, hcd->regs + USB2_INT_ENABLE);
+	for (clk = EHCI_MAX_CLKS - 1; clk >= 0; clk--)
+		if (priv->clks[clk])
+			clk_disable_unprepare(priv->clks[clk]);
+}
+
+static struct hc_driver __read_mostly ehci_platform_hc_driver;
+
+static const struct ehci_driver_overrides platform_overrides __initconst = {
+	.reset =		r8a77470_ehci_platform_reset,
+	.extra_priv_size =	sizeof(struct ehci_platform_priv),
+};
+
+static struct usb_ehci_pdata ehci_platform_defaults = {
+	.power_on =		r8a77470_ehci_platform_power_on,
+	.power_suspend =	r8a77470_ehci_platform_power_off,
+	.power_off =		r8a77470_ehci_platform_power_off,
+};
+
+static int r8a77470_ehci_platform_probe(struct platform_device *dev)
+{
+	struct usb_hcd *hcd;
+	struct resource *res_mem;
+	struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
+	struct ehci_platform_priv *priv;
+	struct ehci_hcd *ehci;
+	int err, irq, clk = 0;
+
+	if (usb_disabled())
+		return -ENODEV;
+
+	/*
+	 * Use reasonable defaults so platforms don't have to provide these
+	 * with DT probing on ARM.
+	 */
+	if (!pdata)
+		pdata = &ehci_platform_defaults;
+
+	err = dma_coerce_mask_and_coherent(&dev->dev,
+		pdata->dma_mask_64 ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
+	if (err) {
+		dev_err(&dev->dev, "Error: DMA mask configuration failed\n");
+		return err;
+	}
+
+	irq = platform_get_irq(dev, 0);
+	if (irq < 0) {
+		dev_err(&dev->dev, "no irq provided");
+		return irq;
+	}
+
+	hcd = usb_create_hcd(&ehci_platform_hc_driver, &dev->dev,
+			     dev_name(&dev->dev));
+	if (!hcd)
+		return -ENOMEM;
+
+	platform_set_drvdata(dev, hcd);
+	dev->dev.platform_data = pdata;
+	priv = hcd_to_ehci_priv(hcd);
+	ehci = hcd_to_ehci(hcd);
+
+	if (pdata == &ehci_platform_defaults && dev->dev.of_node) {
+		for (clk = 0; clk < EHCI_MAX_CLKS; clk++) {
+			priv->clks[clk] = of_clk_get(dev->dev.of_node, clk);
+			if (IS_ERR(priv->clks[clk])) {
+				err = PTR_ERR(priv->clks[clk]);
+				if (err == -EPROBE_DEFER)
+					goto err_put_clks;
+				priv->clks[clk] = NULL;
+				break;
+			}
+		}
+	}
+
+	priv->rsts = devm_reset_control_array_get_optional_shared(&dev->dev);
+	if (IS_ERR(priv->rsts)) {
+		err = PTR_ERR(priv->rsts);
+		goto err_put_clks;
+	}
+
+	err = reset_control_deassert(priv->rsts);
+	if (err)
+		goto err_put_clks;
+
+	res_mem = platform_get_resource(dev, IORESOURCE_MEM, 0);
+	hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
+	if (IS_ERR(hcd->regs)) {
+		err = PTR_ERR(hcd->regs);
+		goto err_reset;
+	}
+	hcd->rsrc_start = res_mem->start;
+	hcd->rsrc_len = resource_size(res_mem);
+
+	if (pdata->power_on) {
+		err = pdata->power_on(dev);
+		if (err < 0)
+			goto err_reset;
+	}
+
+	err = usb_add_hcd(hcd, irq, IRQF_SHARED);
+	if (err)
+		goto err_power;
+
+	device_wakeup_enable(hcd->self.controller);
+	device_enable_async_suspend(hcd->self.controller);
+	platform_set_drvdata(dev, hcd);
+
+	return err;
+
+err_power:
+	if (pdata->power_off)
+		pdata->power_off(dev);
+err_reset:
+	reset_control_assert(priv->rsts);
+err_put_clks:
+	while (--clk >= 0)
+		clk_put(priv->clks[clk]);
+
+	if (pdata == &ehci_platform_defaults)
+		dev->dev.platform_data = NULL;
+
+	usb_put_hcd(hcd);
+
+	return err;
+}
+
+static int r8a77470_ehci_platform_remove(struct platform_device *dev)
+{
+	struct usb_hcd *hcd = platform_get_drvdata(dev);
+	struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev);
+	struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
+	int clk;
+
+	usb_remove_hcd(hcd);
+
+	if (pdata->power_off)
+		pdata->power_off(dev);
+
+	reset_control_assert(priv->rsts);
+
+	for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++)
+		clk_put(priv->clks[clk]);
+
+	usb_put_hcd(hcd);
+
+	if (pdata == &ehci_platform_defaults)
+		dev->dev.platform_data = NULL;
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int ehci_platform_suspend(struct device *dev)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	struct usb_ehci_pdata *pdata = dev_get_platdata(dev);
+	struct platform_device *pdev = to_platform_device(dev);
+	bool do_wakeup = device_may_wakeup(dev);
+	int ret;
+
+	ret = ehci_suspend(hcd, do_wakeup);
+	if (ret)
+		return ret;
+
+	if (pdata->power_suspend)
+		pdata->power_suspend(pdev);
+
+	return ret;
+}
+
+static int ehci_platform_resume(struct device *dev)
+{
+	struct usb_hcd *hcd = dev_get_drvdata(dev);
+	struct usb_ehci_pdata *pdata = dev_get_platdata(dev);
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd);
+	struct device *companion_dev;
+	int err;
+
+	if (pdata->power_on) {
+		err = pdata->power_on(pdev);
+		if (err < 0)
+			return err;
+	}
+
+	companion_dev = usb_of_get_companion_dev(hcd->self.controller);
+	if (companion_dev) {
+		device_pm_wait_for_dev(hcd->self.controller, companion_dev);
+		put_device(companion_dev);
+	}
+
+	ehci_resume(hcd, priv->reset_on_resume);
+	return 0;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct of_device_id r8a77470_ehci_ids[] = {
+	{ .compatible = "renesas,ehci-r8a77470", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, r8a77470_ehci_ids);
+
+static SIMPLE_DEV_PM_OPS(ehci_platform_pm_ops, ehci_platform_suspend,
+	ehci_platform_resume);
+
+static struct platform_driver ehci_platform_driver = {
+	.probe		= r8a77470_ehci_platform_probe,
+	.remove		= r8a77470_ehci_platform_remove,
+	.shutdown	= usb_hcd_platform_shutdown,
+	.driver		= {
+		.name	= "r8a77470-ehci",
+		.pm	= &ehci_platform_pm_ops,
+		.of_match_table = r8a77470_ehci_ids,
+	}
+};
+
+static int __init ehci_platform_init(void)
+{
+	if (usb_disabled())
+		return -ENODEV;
+
+	pr_info("%s: " DRIVER_DESC "\n", hcd_name);
+
+	ehci_init_driver(&ehci_platform_hc_driver, &platform_overrides);
+	return platform_driver_register(&ehci_platform_driver);
+}
+module_init(ehci_platform_init);
+
+static void __exit ehci_platform_cleanup(void)
+{
+	platform_driver_unregister(&ehci_platform_driver);
+}
+module_exit(ehci_platform_cleanup);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Biju Das <biju.das@bp.renesas.com>");
+MODULE_LICENSE("GPL");
-- 
2.7.4

[PATCH 05/12] ARM: shmobile: Enable USB [EO]HCI HCD PLATFORM support in shmobile_defconfig

[Biju Das]

The USB [EO]HCI controller on RZ/G1C SoC doesn't have PCI bridge like
other R-Car Gen2 devices. So enable generic USB [EO]HCI HCD PLATFORM
support in shmobile_defconfig.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
V1-->V2
 * New patch
---
 arch/arm/configs/shmobile_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 9b0efac..6fad590 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -146,7 +146,9 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_R8A77470=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_R8A66597_HCD=y
 CONFIG_USB_RENESAS_USBHS=y
 CONFIG_USB_GADGET=y
-- 
2.7.4

[PATCH 06/12] dt-bindings: usb: renesas_usbhs: Add support for r8a77470

[Biju Das]

Document support for RZ/G1C (R8A77470) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
V1-->V2
  * New patch
---
 Documentation/devicetree/bindings/usb/renesas_usbhs.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
index d93b6a1..b8acc2a 100644
--- a/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
+++ b/Documentation/devicetree/bindings/usb/renesas_usbhs.txt
@@ -6,6 +6,7 @@ Required properties:
 	- "renesas,usbhs-r8a7743" for r8a7743 (RZ/G1M) compatible device
 	- "renesas,usbhs-r8a7744" for r8a7744 (RZ/G1N) compatible device
 	- "renesas,usbhs-r8a7745" for r8a7745 (RZ/G1E) compatible device
+	- "renesas,usbhs-r8a77470" for r8a77470 (RZ/G1C) compatible device
 	- "renesas,usbhs-r8a774a1" for r8a774a1 (RZ/G2M) compatible device
 	- "renesas,usbhs-r8a774c0" for r8a774c0 (RZ/G2E) compatible device
 	- "renesas,usbhs-r8a7790" for r8a7790 (R-Car H2) compatible device
-- 
2.7.4

[PATCH 07/12] ARM: dts: r8a77470: Add USB PHY DT support

[Biju Das]

Define the r8a77470 generic part of the USB PHY device node.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
V1-->V2
 * New patch
---
 arch/arm/boot/dts/r8a77470.dtsi | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 493cf2b..d6438fb 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -325,6 +325,42 @@
 			status = "disabled";
 		};
 
+		usbphy0: usb-phy@e6590100 {
+			compatible = "renesas,usb-phy-r8a77470",
+				     "renesas,rcar-gen2-usb-phy";
+			reg = <0 0xe6590100 0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cpg CPG_MOD 704>;
+			clock-names = "usbhs";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 704>;
+			status = "disabled";
+
+			usb0: usb-channel@0 {
+				reg = <0>;
+				#phy-cells = <1>;
+			};
+		};
+
+		usbphy1: usb-phy@e6598100 {
+			compatible = "renesas,usb-phy-r8a77470",
+				     "renesas,rcar-gen2-usb-phy";
+			reg = <0 0xe6598100 0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&cpg CPG_MOD 706>;
+			clock-names = "usbhs";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 706>;
+			status = "disabled";
+
+			usb1: usb-channel@0 {
+				reg = <0>;
+				#phy-cells = <1>;
+			};
+		};
+
 		usb_dmac00: dma-controller@e65a0000 {
 			compatible = "renesas,r8a77470-usb-dmac",
 				     "renesas,usb-dmac";
-- 
2.7.4

[PATCH 08/12] ARM: dts: iwg23s-sbc: Enable USB Phy[01]

[Biju Das]

Enable USB phy[01] on iWave iwg23s sbc based on RZ/G1C SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
V1-->V2
 * No change
---
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 9f9eb15..96bb2fb 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -214,6 +214,16 @@
 		function = "sdhi2";
 		power-source = <1800>;
 	};
+
+	usb0_pins: usb0 {
+		groups = "usb0";
+		function = "usb0";
+	};
+
+	usb1_pins: usb1 {
+		groups = "usb1";
+		function = "usb1";
+	};
 };
 
 &qspi0 {
@@ -274,3 +284,17 @@
 	sd-uhs-sdr50;
 	status = "okay";
 };
+
+&usbphy0 {
+	pinctrl-0 = <&usb0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&usbphy1 {
+	pinctrl-0 = <&usb1_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
-- 
2.7.4

[PATCH 09/12] ARM: dts: r8a77470: Add USB2.0 Host (EHCI/OHCI) device

[Biju Das]

Define the r8a77470 generic part of the USB2.0 Host Controller device
nodes (ehci[01]/ohci[01]).

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
V1-->V2
 * New patch
---
 arch/arm/boot/dts/r8a77470.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index d6438fb..c8a4651 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -624,6 +624,56 @@
 			status = "disabled";
 		};
 
+		ohci0: usb@ee080000 {
+			compatible = "generic-ohci";
+			reg = <0 0xee080000 0 0x100>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			phys = <&usb0 0>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			status = "disabled";
+		};
+
+		ohci1: usb@ee0c0000 {
+			compatible = "generic-ohci";
+			reg = <0 0xee0c0000 0 0x100>;
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 705>;
+			phys = <&usb0 1>, <&usb1 0>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 705>;
+			status = "disabled";
+		};
+
+		ehci0: usb@ee080100 {
+			compatible = "renesas,ehci-r8a77470";
+			reg = <0 0xee080100 0 0x800>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 703>;
+			phys = <&usb0 0>;
+			phy-names = "usb";
+			companion = <&ohci0>;
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 703>;
+			status = "disabled";
+		};
+
+		ehci1: usb@ee0c0100 {
+			compatible = "renesas,ehci-r8a77470";
+			reg = <0 0xee0c0100 0 0x800>;
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 705>;
+			phys = <&usb0 1>, <&usb1 0>;
+			phy-names = "usb";
+			companion = <&ohci1>;
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 705>;
+			status = "disabled";
+		};
+
 		sdhi0: sd@ee100000 {
 			compatible = "renesas,sdhi-r8a77470",
 				     "renesas,rcar-gen2-sdhi";
-- 
2.7.4

[PATCH 10/12] ARM: dts: iwg23s-sbc: Enable USB USB2.0 Host

[Biju Das]

Enable USB2.0 host on the iwg23s sbc.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
V1-->V2
 * No change
---
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 96bb2fb..f84ec16 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -106,6 +106,10 @@
 	};
 };
 
+&ehci1 {
+	status = "okay";
+};
+
 &extal_clk {
 	clock-frequency = <20000000>;
 };
@@ -166,6 +170,10 @@
 	};
 };
 
+&ohci1 {
+	status = "okay";
+};
+
 &pfc {
 	avb_pins: avb {
 		groups = "avb_mdio", "avb_gmii_tx_rx";
-- 
2.7.4

[PATCH 11/12] ARM: dts: r8a77470: Add HSUSB device nodes

[Biju Das]

Define the r8a77470 generic part of the HSUSB0/1 device nodes.

Currently the renesas_usbhs driver doesn't handle multiple phys and we
don't have a proper hardware to validate such driver changes.

So for hsusb1 it is assumed that usbphy0 will be enabled by either
channel0 host or device.

In future, if any boards support hsusb1, we will need to add multiple phy
support in the renesas_usbhs driver and override the board dts to enable
the same. 

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
V1-->V2
 * New patch
---
 arch/arm/boot/dts/r8a77470.dtsi | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index c8a4651..d1037d7 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -325,6 +325,23 @@
 			status = "disabled";
 		};
 
+		hsusb0: hsusb@e6590000 {
+			compatible = "renesas,usbhs-r8a77470",
+				     "renesas,rcar-gen2-usbhs";
+			reg = <0 0xe6590000 0 0x100>;
+			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 704>;
+			dmas = <&usb_dmac00 0>, <&usb_dmac00 1>,
+			       <&usb_dmac10 0>, <&usb_dmac10 1>;
+			dma-names = "ch0", "ch1", "ch2", "ch3";
+			renesas,buswait = <4>;
+			phys = <&usb0 1>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 704>;
+			status = "disabled";
+		};
+
 		usbphy0: usb-phy@e6590100 {
 			compatible = "renesas,usb-phy-r8a77470",
 				     "renesas,rcar-gen2-usb-phy";
@@ -343,6 +360,24 @@
 			};
 		};
 
+		hsusb1: hsusb@e6598000 {
+			compatible = "renesas,usbhs-r8a77470",
+				     "renesas,rcar-gen2-usbhs";
+			reg = <0 0xe6598000 0 0x100>;
+			interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 706>;
+			dmas = <&usb_dmac01 0>, <&usb_dmac01 1>,
+			       <&usb_dmac11 0>, <&usb_dmac11 1>;
+			dma-names = "ch0", "ch1", "ch2", "ch3";
+			renesas,buswait = <4>;
+			/* We need to turn on usbphy0 to make usbphy1 to work */
+			phys = <&usb1 1>;
+			phy-names = "usb";
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 706>;
+			status = "disabled";
+		};
+
 		usbphy1: usb-phy@e6598100 {
 			compatible = "renesas,usb-phy-r8a77470",
 				     "renesas,rcar-gen2-usb-phy";
-- 
2.7.4

[PATCH 12/12] ARM: dts: iwg23s-sbc: Enable HS-USB

[Biju Das]

Enable HS-USB device for the iWave SBC based on RZ/G1C.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
V1-->V2
 * New patch
---
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index f84ec16..c8fbc7f 100644
--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
@@ -123,6 +123,10 @@
 	};
 };
 
+&hsusb0 {
+	status = "okay";
+};
+
 &i2c3 {
 	pinctrl-0 = <&i2c3_pins>;
 	pinctrl-names = "default";
-- 
2.7.4

Re: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for Renesas RZ/G1C devices

[Greg Kroah-Hartman]

On Mon, Apr 01, 2019 at 01:53:44PM +0100, Biju Das wrote:
> This patch adds the glue code required to ensure the on-chip EHCI
> controller works on RZ/G1C(a.k.a R8A77470) SoC's from Renesas.
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> ---
> V1-->V2
>   * New patch
> ---
>  drivers/usb/host/Kconfig         |   9 ++
>  drivers/usb/host/Makefile        |   1 +
>  drivers/usb/host/ehci-r8a77470.c | 327 +++++++++++++++++++++++++++++++++++++++
>  3 files changed, 337 insertions(+)
>  create mode 100644 drivers/usb/host/ehci-r8a77470.c
> 
> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
> index d809671..a474aa9 100644
> --- a/drivers/usb/host/Kconfig
> +++ b/drivers/usb/host/Kconfig
> @@ -237,6 +237,15 @@ config USB_EHCI_HCD_STI
>  	  Enable support for the on-chip EHCI controller found on
>  	  STMicroelectronics consumer electronics SoC's.
>  
> +config USB_EHCI_HCD_R8A77470
> +	tristate "Support for Renesas R8A77470 on-chip EHCI USB controller"
> +	depends on ARCH_R8A77470 && OF

COMPILE_TEST so that others can also test-build this to ensure that we
do not break anything over time?

thanks,

greg k-h

Re: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for Renesas RZ/G1C devices

[Alan Stern]

On Mon, 1 Apr 2019, Biju Das wrote:

> This patch adds the glue code required to ensure the on-chip EHCI
> controller works on RZ/G1C(a.k.a R8A77470) SoC's from Renesas.

You should explain what this new glue code does.  And why is it needed? 
Can't you use the existing ehci-platform driver instead?

Alan Stern

RE: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for Renesas RZ/G1C devices

[Biju Das]

Hi Alan,

Thanks for the feedback.

> Subject: Re: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for
> Renesas RZ/G1C devices
> 
> On Mon, 1 Apr 2019, Biju Das wrote:
> 
> > This patch adds the glue code required to ensure the on-chip EHCI
> > controller works on RZ/G1C(a.k.a R8A77470) SoC's from Renesas.
> 
> You should explain what this new glue code does.  And why is it needed?

Glue code initializes  following  registers on the host 

1) initializing interrupt enable
2) OVC detection timer
3) suspend/ resume timer register

Without glue code, interrupt generation is disabled.
 
> Can't you use the existing ehci-platform driver instead?
> 
This driver is almost similar to generic ehci-platform except that it needs to do
some platform initialization as mentioned above. If  I am correct, we cannot do 
any platform initialization in generic code. 

The reason for the new driver is because of the below discussion
https://patchwork.kernel.org/patch/10655853/

regards,
Biju

RE: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for Renesas RZ/G1C devices

[Alan Stern]

On Mon, 1 Apr 2019, Biju Das wrote:

> Hi Alan,
> 
> Thanks for the feedback.
> 
> > Subject: Re: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for
> > Renesas RZ/G1C devices
> > 
> > On Mon, 1 Apr 2019, Biju Das wrote:
> > 
> > > This patch adds the glue code required to ensure the on-chip EHCI
> > > controller works on RZ/G1C(a.k.a R8A77470) SoC's from Renesas.
> > 
> > You should explain what this new glue code does.  And why is it needed?
> 
> Glue code initializes  following  registers on the host 
> 
> 1) initializing interrupt enable
> 2) OVC detection timer
> 3) suspend/ resume timer register
> 
> Without glue code, interrupt generation is disabled.

Good.  This information should be added to the patch description.

> > Can't you use the existing ehci-platform driver instead?
> > 
> This driver is almost similar to generic ehci-platform except that it needs to do
> some platform initialization as mentioned above. If  I am correct, we cannot do 
> any platform initialization in generic code. 

Are you sure you can't?

Also, have you considered modifying ehci-platform.c, in a 
general-purpose way, such that you could use it and still get this 
platform-specific work done?  For example, you could add some callbacks 
to the usb_ehci_pdata structure.  Or maybe you can use the callbacks 
that are already present, with no modifications needed.

> The reason for the new driver is because of the below discussion
> https://patchwork.kernel.org/patch/10655853/

I didn't notice anything in that discussion which would prevent you 
from using ehci-platform.c (possibly with a few modifications).

Alan Stern

RE: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for Renesas RZ/G1C devices

[Biju Das]

Hi Greg,

Thanks for the feedback.

> Subject: Re: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for
> Renesas RZ/G1C devices
> 
> On Mon, Apr 01, 2019 at 01:53:44PM +0100, Biju Das wrote:
> > This patch adds the glue code required to ensure the on-chip EHCI
> > controller works on RZ/G1C(a.k.a R8A77470) SoC's from Renesas.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > ---
> > V1-->V2
> >   * New patch
> > ---
> >  drivers/usb/host/Kconfig         |   9 ++
> >  drivers/usb/host/Makefile        |   1 +
> >  drivers/usb/host/ehci-r8a77470.c | 327
> > +++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 337 insertions(+)
> >  create mode 100644 drivers/usb/host/ehci-r8a77470.c
> >
> > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index
> > d809671..a474aa9 100644
> > --- a/drivers/usb/host/Kconfig
> > +++ b/drivers/usb/host/Kconfig
> > @@ -237,6 +237,15 @@ config USB_EHCI_HCD_STI
> >  	  Enable support for the on-chip EHCI controller found on
> >  	  STMicroelectronics consumer electronics SoC's.
> >
> > +config USB_EHCI_HCD_R8A77470
> > +	tristate "Support for Renesas R8A77470 on-chip EHCI USB controller"
> > +	depends on ARCH_R8A77470 && OF
> 
> COMPILE_TEST so that others can also test-build this to ensure that we do
> not break anything over time?

OK.  Will send V3 with below changes

depends on (ARCH_R8A77470 && OF) || COMPILE_TEST

regards,
Biju

RE: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for Renesas RZ/G1C devices

[Yoshihiro Shimoda]

Hi Biju-san,

Thank you for the patch!

> From: Biju Das, Sent: Monday, April 1, 2019 9:54 PM
<snip>
> +/******* USB2.0 Host registers (original offset is +0x100) *******/
> +#define USB2_INT_ENABLE			0x100
> +#define USB2_SPD_RSM_TIMSET		0x20c
> +#define USB2_OC_TIMSET			0x210
> +
> +#define USB2_INT_ENABLE_USBH_INTB_EN	BIT(2)
> +#define USB2_INT_ENABLE_USBH_INTA_EN	BIT(1)
> +#define USB2_INT_ENABLE_INIT		(USB2_INT_ENABLE_USBH_INTB_EN | \
> +					 USB2_INT_ENABLE_USBH_INTA_EN)
> +
> +#define USB2_SPD_RSM_TIMSET_INIT	0x014e029b
> +#define USB2_OC_TIMSET_INIT		0x000209ab

I should have notice this codes at the previous patch though,
I'm thinking we can reuse the R-Car Gen3 codes because these values
are similar with the phy-rcar-gen3-usb2.c like below:
----------------------------------------------------------------------
/* INT_ENABLE */
#define USB2_INT_ENABLE_UCOM_INTEN	BIT(3)
#define USB2_INT_ENABLE_USBH_INTB_EN	BIT(2)
#define USB2_INT_ENABLE_USBH_INTA_EN	BIT(1)
#define USB2_INT_ENABLE_INIT		(USB2_INT_ENABLE_UCOM_INTEN | \
					 USB2_INT_ENABLE_USBH_INTB_EN | \
					 USB2_INT_ENABLE_USBH_INTA_EN)
<snip>
/* SPD_RSM_TIMSET */
#define USB2_SPD_RSM_TIMSET_INIT	0x014e029b

/* OC_TIMSET */
#define USB2_OC_TIMSET_INIT		0x000209ab
----------------------------------------------------------------------

If so, we can use ehci-platform.c and ohci-platform.c as-is. In this case,
the "phy: renesas: phy-rcar-gen2: Add support for r8a77470" driver should
be initialized at first to release PLLRESET. And then, the phy-rcar-gen3-usb2
driver would be initialized as second step. I think we can set these resisters
at phy_init timing because the following patch did so:

  https://patchwork.kernel.org/patch/10655855/

What do you think?

Best regards,
Yoshihiro Shimoda

RE: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for Renesas RZ/G1C devices

[Biju Das]

Hi Shimoda-San,

Thanks for the feedback.

> Subject: RE: [PATCH 04/12] usb: host: ehci-r8a77470: Add EHCI support for
> Renesas RZ/G1C devices
> 
> Hi Biju-san,
> 
> Thank you for the patch!
> 
> > From: Biju Das, Sent: Monday, April 1, 2019 9:54 PM
> <snip>
> > +/******* USB2.0 Host registers (original offset is +0x100) *******/
> > +#define USB2_INT_ENABLE			0x100
> > +#define USB2_SPD_RSM_TIMSET		0x20c
> > +#define USB2_OC_TIMSET			0x210
> > +
> > +#define USB2_INT_ENABLE_USBH_INTB_EN	BIT(2)
> > +#define USB2_INT_ENABLE_USBH_INTA_EN	BIT(1)
> > +#define USB2_INT_ENABLE_INIT
> 	(USB2_INT_ENABLE_USBH_INTB_EN | \
> > +					 USB2_INT_ENABLE_USBH_INTA_EN)
> > +
> > +#define USB2_SPD_RSM_TIMSET_INIT	0x014e029b
> > +#define USB2_OC_TIMSET_INIT		0x000209ab
> 
> I should have notice this codes at the previous patch though, I'm thinking we
> can reuse the R-Car Gen3 codes because these values are similar with the
> phy-rcar-gen3-usb2.c like below:
> ----------------------------------------------------------------------
> /* INT_ENABLE */
> #define USB2_INT_ENABLE_UCOM_INTEN	BIT(3)
> #define USB2_INT_ENABLE_USBH_INTB_EN	BIT(2)
> #define USB2_INT_ENABLE_USBH_INTA_EN	BIT(1)
> #define USB2_INT_ENABLE_INIT
> 	(USB2_INT_ENABLE_UCOM_INTEN | \
> 					 USB2_INT_ENABLE_USBH_INTB_EN
> | \
> 					 USB2_INT_ENABLE_USBH_INTA_EN)
> <snip>
> /* SPD_RSM_TIMSET */
> #define USB2_SPD_RSM_TIMSET_INIT	0x014e029b
> 
> /* OC_TIMSET */
> #define USB2_OC_TIMSET_INIT		0x000209ab
> ----------------------------------------------------------------------
> 
> If so, we can use ehci-platform.c and ohci-platform.c as-is. In this case, the
> "phy: renesas: phy-rcar-gen2: Add support for r8a77470" driver should be
> initialized at first to release PLLRESET. And then, the phy-rcar-gen3-usb2
> driver would be initialized as second step. I think we can set these resisters at
> phy_init timing because the following patch did so:
> 
>   https://patchwork.kernel.org/patch/10655855/
> 
> What do you think?

Good catch. This solution will avoid overlapping regions as mentioned by Rob in the below patch and  also will avoid modifying ehci-platform.c  as suggested by Alen. 
https://patchwork.kernel.org/patch/10655853/

I will send V3 based on this solution. Please let me know, if you think otherwise.

Regards,
Biju

Re: [PATCH 03/12] dt-bindings: usb: ehci-r8a77470 devicetree binding document

[Rob Herring]

On Mon,  1 Apr 2019 13:53:43 +0100, Biju Das wrote:
> Add device tree binding document for Renesas r8a77470(a.k.a RZ/G1C)
> on-chip EHCI controller driver.
> 
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> ---
> V1-->V2
>   * New patch
> ---
>  .../devicetree/bindings/usb/ehci-r8a77470.txt      | 35 ++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/ehci-r8a77470.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

RE: [PATCH 03/12] dt-bindings: usb: ehci-r8a77470 devicetree binding document

[Biju Das]

Hi Rob,

Thanks for the review.  I guess we need to drop this patch, if the solution proposed by Shimoda-San is acceptable by everyone.
The same result can be achieved without using this driver. I have posted V3 based on this. please see the link below.

https://patchwork.kernel.org/patch/10883263/

ehci-r8a77479 driver = generic ehci driver + phy initialization code of rcar-gen3-usb2 driver.

Regards,
Biju

> Subject: Re: [PATCH 03/12] dt-bindings: usb: ehci-r8a77470 devicetree
> binding document
> 
> On Mon,  1 Apr 2019 13:53:43 +0100, Biju Das wrote:
> > Add device tree binding document for Renesas r8a77470(a.k.a RZ/G1C)
> > on-chip EHCI controller driver.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > ---
> > V1-->V2
> >   * New patch
> > ---
> >  .../devicetree/bindings/usb/ehci-r8a77470.txt      | 35
> ++++++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/usb/ehci-r8a77470.txt
> >
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

RE: [PATCH 03/12] dt-bindings: usb: ehci-r8a77470 devicetree binding document

[Yoshihiro Shimoda]

Hi Biju-san,

> From: Biju Das, Sent: Tuesday, April 9, 2019 4:30 PM
> 
> Hi Rob,
> 
> Thanks for the review.  I guess we need to drop this patch, if the solution proposed by Shimoda-San is acceptable by everyone.
> The same result can be achieved without using this driver. I have posted V3 based on this. please see the link below.
> 
> https://patchwork.kernel.org/patch/10883263/
> 
> ehci-r8a77479 driver = generic ehci driver + phy initialization code of rcar-gen3-usb2 driver.

I accept v3 based patches (for now I checked patch 1 to 4 only though).

Best regards,
Yoshihiro Shimoda