From: Biju Das <biju.das@bp.renesas.com>
To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>
Cc: Biju Das <biju.das@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Simon Horman <horms@verge.net.au>,
Magnus Damm <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Subject: [PATCH 1/4] arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devices
Date: Mon, 23 Sep 2019 15:57:25 +0100 [thread overview]
Message-ID: <1569250648-33857-2-git-send-email-biju.das@bp.renesas.com> (raw)
In-Reply-To: <1569250648-33857-1-git-send-email-biju.das@bp.renesas.com>
This patch adds OPPs table for CA57{0,1} cpu devices.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index f42f646..398bf38 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -45,6 +45,28 @@
clock-frequency = <0>;
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <830000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -59,6 +81,7 @@
#cooling-cells = <2>;
dynamic-power-coefficient = <854>;
clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
a57_1: cpu@1 {
@@ -69,6 +92,7 @@
next-level-cache = <&L2_CA57>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>;
+ operating-points-v2 = <&cluster0_opp>;
};
L2_CA57: cache-controller-0 {
--
2.7.4
next prev parent reply other threads:[~2019-09-23 14:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-23 14:57 [PATCH 0/4] Add RZ/G2N OPP/Thermal/CMT/TMU support Biju Das
2019-09-23 14:57 ` Biju Das [this message]
2019-10-09 12:05 ` [PATCH 1/4] arm64: dts: renesas: r8a774b1: Add OPPs table for cpu devices Geert Uytterhoeven
2019-09-23 14:57 ` [PATCH 2/4] arm64: dts: renesas: r8a774b1: Add RZ/G2N thermal support Biju Das
2019-10-09 12:07 ` Geert Uytterhoeven
2019-09-23 14:57 ` [PATCH 3/4] arm64: dts: renesas: r8a774b1: Add CMT device nodes Biju Das
2019-10-09 12:08 ` Geert Uytterhoeven
2019-09-23 14:57 ` [PATCH 4/4] arm64: dts: renesas: r8a774b1: Add TMU " Biju Das
2019-10-09 12:09 ` Geert Uytterhoeven
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1569250648-33857-2-git-send-email-biju.das@bp.renesas.com \
--to=biju.das@bp.renesas.com \
--cc=Chris.Paterson2@renesas.com \
--cc=devicetree@vger.kernel.org \
--cc=fabrizio.castro@bp.renesas.com \
--cc=geert+renesas@glider.be \
--cc=horms@verge.net.au \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=magnus.damm@gmail.com \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).