* [PATCH RFC 1/3] arm64: dts: renesas: r8a779{7|8}0: add RPC-IF support
2019-01-12 17:41 [PATCH RFC 0/3] Add R8A779{7|8}0 RPC-IF support Sergei Shtylyov
@ 2019-01-12 17:43 ` Sergei Shtylyov
2019-01-12 17:44 ` [PATCH RFC 2/3] arm64: dts: renesas: r8a77970: eagle/v3msk: add QSPI flash support Sergei Shtylyov
2019-01-12 17:45 ` [PATCH RFC 3/3] arm64: dts: renesas: r8a77980: condor/v3hsk: " Sergei Shtylyov
2 siblings, 0 replies; 4+ messages in thread
From: Sergei Shtylyov @ 2019-01-12 17:43 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, devicetree, Rob Herring
Cc: Mark Rutland, Magnus Damm
Describe RPC-IF in the R8A779{7|8}0 device trees.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 15 +++++++++++++++
2 files changed, 30 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -1038,6 +1038,21 @@
status = "disabled";
};
+ rpc: rpc@ee200000 {
+ compatible = "renesas,r8a77970-rpc";
+ reg = <0 0xee200000 0 0x8100>,
+ <0 0x08000000 0 0x4000000>;
+ reg-names = "regs", "dirmap";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -1325,6 +1325,21 @@
status = "disabled";
};
+ rpc: rpc@ee200000 {
+ compatible = "renesas,r8a77980-rpc";
+ reg = <0 0xee200000 0 0x8100>,
+ <0 0x08000000 0 0x4000000>;
+ reg-names = "regs", "dirmap";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 917>;
+ clock-names = "rpc";
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 917>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1010000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH RFC 2/3] arm64: dts: renesas: r8a77970: eagle/v3msk: add QSPI flash support
2019-01-12 17:41 [PATCH RFC 0/3] Add R8A779{7|8}0 RPC-IF support Sergei Shtylyov
2019-01-12 17:43 ` [PATCH RFC 1/3] arm64: dts: renesas: r8a779{7|8}0: add " Sergei Shtylyov
@ 2019-01-12 17:44 ` Sergei Shtylyov
2019-01-12 17:45 ` [PATCH RFC 3/3] arm64: dts: renesas: r8a77980: condor/v3hsk: " Sergei Shtylyov
2 siblings, 0 replies; 4+ messages in thread
From: Sergei Shtylyov @ 2019-01-12 17:44 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, devicetree, Rob Herring
Cc: Mark Rutland, Magnus Damm
Define the Eagle/V3MSK board dependent parts of the RPC-IF device node.
Add device nodes for Spansion S25FS512S SPI flash and MTD partitions on it.
Based on the original patches by Dmitry Shifrin.
Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 68 +++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 68 +++++++++++++++++++++++++
2 files changed, 136 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
@@ -173,12 +173,80 @@
function = "i2c0";
};
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
};
+&rpc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+
+ renesas,rpc-mode = "spi";
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ cr7@40000 {
+ reg = <0x00040000 0x080000>;
+ read-only;
+ };
+ cert_header_sa3@c0000 {
+ reg = <0x000c0000 0x080000>;
+ read-only;
+ };
+ bl2@140000 {
+ reg = <0x00140000 0x040000>;
+ read-only;
+ };
+ cert_header_sa6@180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@1c0000 {
+ reg = <0x001c0000 0x460000>;
+ read-only;
+ };
+ uboot@640000 {
+ reg = <0x00640000 0x0c0000>;
+ read-only;
+ };
+ uboot-env@700000 {
+ reg = <0x00700000 0x040000>;
+ read-only;
+ };
+ dtb@740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@7c0000 {
+ reg = <0x007c0000 0x1400000>;
+ };
+ user@1bc0000 {
+ reg = <0x01bc0000 0x2440000>;
+ };
+ };
+ };
+};
+
&rwdt {
timeout-sec = <60>;
status = "okay";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
@@ -145,6 +145,11 @@
power-source = <3300>;
};
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@@ -220,6 +225,69 @@
status = "okay";
};
+&rpc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+
+ renesas,rpc-mode = "spi";
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ cr7@40000 {
+ reg = <0x00040000 0x080000>;
+ read-only;
+ };
+ cert_header_sa3@c0000 {
+ reg = <0x000c0000 0x080000>;
+ read-only;
+ };
+ bl2@140000 {
+ reg = <0x00140000 0x040000>;
+ read-only;
+ };
+ cert_header_sa6@180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@1c0000 {
+ reg = <0x001c0000 0x460000>;
+ read-only;
+ };
+ uboot@640000 {
+ reg = <0x00640000 0x0c0000>;
+ read-only;
+ };
+ uboot-env@700000 {
+ reg = <0x00700000 0x040000>;
+ read-only;
+ };
+ dtb@740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@7c0000 {
+ reg = <0x007c0000 0x1400000>;
+ };
+ user@1bc0000 {
+ reg = <0x01bc0000 0x2440000>;
+ };
+ };
+ };
+};
+
&scif0 {
pinctrl-0 = <&scif0_pins>;
pinctrl-names = "default";
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH RFC 3/3] arm64: dts: renesas: r8a77980: condor/v3hsk: add QSPI flash support
2019-01-12 17:41 [PATCH RFC 0/3] Add R8A779{7|8}0 RPC-IF support Sergei Shtylyov
2019-01-12 17:43 ` [PATCH RFC 1/3] arm64: dts: renesas: r8a779{7|8}0: add " Sergei Shtylyov
2019-01-12 17:44 ` [PATCH RFC 2/3] arm64: dts: renesas: r8a77970: eagle/v3msk: add QSPI flash support Sergei Shtylyov
@ 2019-01-12 17:45 ` Sergei Shtylyov
2 siblings, 0 replies; 4+ messages in thread
From: Sergei Shtylyov @ 2019-01-12 17:45 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, devicetree, Rob Herring
Cc: Mark Rutland, Magnus Damm
Define the Condor/V3HSK board dependent parts of the RPC-IF device node.
Add device nodes for Spansion S25FS512S SPI flash and MTD partitions on it.
Based on the original patches by Dmitry Shifrin.
Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 68 ++++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 68 ++++++++++++++++++++++++
2 files changed, 136 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -264,6 +264,11 @@
power-source = <1800>;
};
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@@ -275,6 +280,69 @@
};
};
+&rpc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+
+ renesas,rpc-mode = "spi";
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ cr7@40000 {
+ reg = <0x00040000 0x080000>;
+ read-only;
+ };
+ cert_header_sa3@c0000 {
+ reg = <0x000c0000 0x080000>;
+ read-only;
+ };
+ bl2@140000 {
+ reg = <0x00140000 0x040000>;
+ read-only;
+ };
+ cert_header_sa6@180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@1c0000 {
+ reg = <0x001c0000 0x460000>;
+ read-only;
+ };
+ uboot@640000 {
+ reg = <0x00640000 0x0c0000>;
+ read-only;
+ };
+ uboot-env@700000 {
+ reg = <0x00700000 0x040000>;
+ read-only;
+ };
+ dtb@740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@7c0000 {
+ reg = <0x007c0000 0x1400000>;
+ };
+ user@1bc0000 {
+ reg = <0x01bc0000 0x2440000>;
+ };
+ };
+ };
+};
+
&rwdt {
timeout-sec = <60>;
status = "okay";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -189,6 +189,11 @@
function = "i2c0";
};
+ qspi0_pins: qspi0 {
+ groups = "qspi0_ctrl", "qspi0_data4";
+ function = "qspi0";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
@@ -200,6 +205,69 @@
};
};
+&rpc {
+ pinctrl-0 = <&qspi0_pins>;
+ pinctrl-names = "default";
+
+ renesas,rpc-mode = "spi";
+ status = "okay";
+
+ flash@0 {
+ compatible = "spansion,s25fs512s", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootparam@0 {
+ reg = <0x00000000 0x040000>;
+ read-only;
+ };
+ cr7@00040000 {
+ reg = <0x00040000 0x080000>;
+ read-only;
+ };
+ cert_header_sa3@000C0000 {
+ reg = <0x000C0000 0x080000>;
+ read-only;
+ };
+ bl2@00140000 {
+ reg = <0x00140000 0x040000>;
+ read-only;
+ };
+ cert_header_sa6@00180000 {
+ reg = <0x00180000 0x040000>;
+ read-only;
+ };
+ bl31@001C0000 {
+ reg = <0x001C0000 0x460000>;
+ read-only;
+ };
+ uboot@00640000 {
+ reg = <0x00640000 0x0C0000>;
+ read-only;
+ };
+ uboot-env@00700000 {
+ reg = <0x00700000 0x040000>;
+ read-only;
+ };
+ dtb@00740000 {
+ reg = <0x00740000 0x080000>;
+ };
+ kernel@007C0000 {
+ reg = <0x007C0000 0x1400000>;
+ };
+ user@01BC0000 {
+ reg = <0x01BC0000 0x2440000>;
+ };
+ };
+ };
+};
+
&rwdt {
timeout-sec = <60>;
status = "okay";
^ permalink raw reply [flat|nested] 4+ messages in thread