* [PATCH] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()
@ 2019-03-01 12:38 Geert Uytterhoeven
2019-03-02 10:15 ` Niklas Söderlund
2019-03-04 10:03 ` Simon Horman
0 siblings, 2 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2019-03-01 12:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Simon Horman, linux-renesas-soc, linux-clk, Geert Uytterhoeven
Explicitly pass the clock's name and register offset to
cpg_sd_clk_register(), so the latter doesn't have to extract them from
the cpg_core_clk object.
This keeps all cpg_core_clk parsing and unmarshalling contained in a
single function (rcar_gen3_cpg_clk_register()).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in clk-renesas-for-v5.2.
drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 9a8071a8114daec9..dcd4ac389326b932 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -369,8 +369,8 @@ static u32 cpg_quirks __initdata;
#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
#define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
-static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
- void __iomem *base, const char *parent_name,
+static struct clk * __init cpg_sd_clk_register(const char *name,
+ void __iomem *base, unsigned int offset, const char *parent_name,
struct raw_notifier_head *notifiers)
{
struct clk_init_data init;
@@ -383,13 +383,13 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
if (!clock)
return ERR_PTR(-ENOMEM);
- init.name = core->name;
+ init.name = name;
init.ops = &cpg_sd_clock_ops;
init.flags = CLK_SET_RATE_PARENT;
init.parent_names = &parent_name;
init.num_parents = 1;
- clock->csn.reg = base + core->offset;
+ clock->csn.reg = base + offset;
clock->hw.init = &init;
clock->div_table = cpg_sd_div_table;
clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
@@ -606,8 +606,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
break;
case CLK_TYPE_GEN3_SD:
- return cpg_sd_clk_register(core, base, __clk_get_name(parent),
- notifiers);
+ return cpg_sd_clk_register(core->name, base, core->offset,
+ __clk_get_name(parent), notifiers);
case CLK_TYPE_GEN3_R:
if (cpg_quirks & RCKCR_CKSEL) {
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()
2019-03-01 12:38 [PATCH] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() Geert Uytterhoeven
@ 2019-03-02 10:15 ` Niklas Söderlund
2019-03-04 10:03 ` Simon Horman
1 sibling, 0 replies; 3+ messages in thread
From: Niklas Söderlund @ 2019-03-02 10:15 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Simon Horman, linux-renesas-soc,
linux-clk
Hi Geert,
Thanks for your patch.
On 2019-03-01 13:38:22 +0100, Geert Uytterhoeven wrote:
> Explicitly pass the clock's name and register offset to
> cpg_sd_clk_register(), so the latter doesn't have to extract them from
> the cpg_core_clk object.
>
> This keeps all cpg_core_clk parsing and unmarshalling contained in a
> single function (rcar_gen3_cpg_clk_register()).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> To be queued in clk-renesas-for-v5.2.
>
> drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
> index 9a8071a8114daec9..dcd4ac389326b932 100644
> --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -369,8 +369,8 @@ static u32 cpg_quirks __initdata;
> #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
> #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
>
> -static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
> - void __iomem *base, const char *parent_name,
> +static struct clk * __init cpg_sd_clk_register(const char *name,
> + void __iomem *base, unsigned int offset, const char *parent_name,
> struct raw_notifier_head *notifiers)
> {
> struct clk_init_data init;
> @@ -383,13 +383,13 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
> if (!clock)
> return ERR_PTR(-ENOMEM);
>
> - init.name = core->name;
> + init.name = name;
> init.ops = &cpg_sd_clock_ops;
> init.flags = CLK_SET_RATE_PARENT;
> init.parent_names = &parent_name;
> init.num_parents = 1;
>
> - clock->csn.reg = base + core->offset;
> + clock->csn.reg = base + offset;
> clock->hw.init = &init;
> clock->div_table = cpg_sd_div_table;
> clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
> @@ -606,8 +606,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
> break;
>
> case CLK_TYPE_GEN3_SD:
> - return cpg_sd_clk_register(core, base, __clk_get_name(parent),
> - notifiers);
> + return cpg_sd_clk_register(core->name, base, core->offset,
> + __clk_get_name(parent), notifiers);
>
> case CLK_TYPE_GEN3_R:
> if (cpg_quirks & RCKCR_CKSEL) {
> --
> 2.17.1
>
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()
2019-03-01 12:38 [PATCH] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() Geert Uytterhoeven
2019-03-02 10:15 ` Niklas Söderlund
@ 2019-03-04 10:03 ` Simon Horman
1 sibling, 0 replies; 3+ messages in thread
From: Simon Horman @ 2019-03-04 10:03 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-clk
On Fri, Mar 01, 2019 at 01:38:22PM +0100, Geert Uytterhoeven wrote:
> Explicitly pass the clock's name and register offset to
> cpg_sd_clk_register(), so the latter doesn't have to extract them from
> the cpg_core_clk object.
>
> This keeps all cpg_core_clk parsing and unmarshalling contained in a
> single function (rcar_gen3_cpg_clk_register()).
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> To be queued in clk-renesas-for-v5.2.
>
> drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
> index 9a8071a8114daec9..dcd4ac389326b932 100644
> --- a/drivers/clk/renesas/rcar-gen3-cpg.c
> +++ b/drivers/clk/renesas/rcar-gen3-cpg.c
> @@ -369,8 +369,8 @@ static u32 cpg_quirks __initdata;
> #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
> #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */
>
> -static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
> - void __iomem *base, const char *parent_name,
> +static struct clk * __init cpg_sd_clk_register(const char *name,
> + void __iomem *base, unsigned int offset, const char *parent_name,
> struct raw_notifier_head *notifiers)
> {
> struct clk_init_data init;
> @@ -383,13 +383,13 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
> if (!clock)
> return ERR_PTR(-ENOMEM);
>
> - init.name = core->name;
> + init.name = name;
> init.ops = &cpg_sd_clock_ops;
> init.flags = CLK_SET_RATE_PARENT;
> init.parent_names = &parent_name;
> init.num_parents = 1;
>
> - clock->csn.reg = base + core->offset;
> + clock->csn.reg = base + offset;
> clock->hw.init = &init;
> clock->div_table = cpg_sd_div_table;
> clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
> @@ -606,8 +606,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
> break;
>
> case CLK_TYPE_GEN3_SD:
> - return cpg_sd_clk_register(core, base, __clk_get_name(parent),
> - notifiers);
> + return cpg_sd_clk_register(core->name, base, core->offset,
> + __clk_get_name(parent), notifiers);
>
> case CLK_TYPE_GEN3_R:
> if (cpg_quirks & RCKCR_CKSEL) {
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-03-01 12:38 [PATCH] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() Geert Uytterhoeven
2019-03-02 10:15 ` Niklas Söderlund
2019-03-04 10:03 ` Simon Horman
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