[PATCH] ARM: dts: r8a7740: Add missing extal2 to CPG node

[PATCH] ARM: dts: r8a7740: Add missing extal2 to CPG node

[Geert Uytterhoeven]

The Clock Pulse Generator (CPG) device node lacks the extal2 clock.
This may lead to a failure registering the "r" clock, or to a wrong
parent for the "usb24s" clock, depending on MD_CK2 pin configuration and
boot loader CPG_USBCKCR register configuration.

This went unnoticed, as this does not affect the single upstream board
configuration, which relies on the first clock input only.

Fixes: d9ffd583bf345e2e ("ARM: shmobile: r8a7740: add SoC clocks to DTS")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in renesas-fixes for v5.7, to avoid the json-schema CPG DT
bindings conversion introducing a regression.
---
 arch/arm/boot/dts/r8a7740.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 014805894ea71f41..0588d4446f9ac2e0 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -479,7 +479,7 @@
 		cpg_clocks: cpg_clocks@e6150000 {
 			compatible = "renesas,r8a7740-cpg-clocks";
 			reg = <0xe6150000 0x10000>;
-			clocks = <&extal1_clk>, <&extalr_clk>;
+			clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
 			#clock-cells = <1>;
 			clock-output-names = "system", "pllc0", "pllc1",
 					     "pllc2", "r",
-- 
2.17.1

Re: [PATCH] ARM: dts: r8a7740: Add missing extal2 to CPG node

[Ulrich Hecht]

> On May 8, 2020 11:59 AM Geert Uytterhoeven <geert+renesas@glider.be> wrote:
> 
>  
> The Clock Pulse Generator (CPG) device node lacks the extal2 clock.
> This may lead to a failure registering the "r" clock, or to a wrong
> parent for the "usb24s" clock, depending on MD_CK2 pin configuration and
> boot loader CPG_USBCKCR register configuration.
> 
> This went unnoticed, as this does not affect the single upstream board
> configuration, which relies on the first clock input only.
> 
> Fixes: d9ffd583bf345e2e ("ARM: shmobile: r8a7740: add SoC clocks to DTS")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>

CU
Uli