* [PATCH] dt-bindings: clock: renesas: div6: Convert to json-schema
@ 2020-05-07 7:50 Geert Uytterhoeven
2020-05-12 15:16 ` Niklas Söderlund
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Geert Uytterhoeven @ 2020-05-07 7:50 UTC (permalink / raw)
To: Rob Herring, Michael Turquette, Stephen Boyd
Cc: devicetree, linux-clk, linux-renesas-soc, Geert Uytterhoeven
Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to
json-schema.
Drop R-Car Gen2 compatible values, which were obsoleted by the unified
"Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
bindings.
Update the example to match reality.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in clk-renesas-for-v5.8.
.../clock/renesas,cpg-div6-clock.yaml | 60 +++++++++++++++++++
.../clock/renesas,cpg-div6-clocks.txt | 40 -------------
2 files changed, 60 insertions(+), 40 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml
delete mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml
new file mode 100644
index 0000000000000000..c55a7c494e013da5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas CPG DIV6 Clock
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
+ Generator (CPG). Their clock input is divided by a configurable factor from 1
+ to 64.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a73a4-div6-clock # R-Mobile APE6
+ - renesas,r8a7740-div6-clock # R-Mobile A1
+ - renesas,sh73a0-div6-clock # SH-Mobile AG5
+ - const: renesas,cpg-div6-clock
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ oneOf:
+ - maxItems: 1
+ - maxItems: 4
+ - maxItems: 8
+ description:
+ For clocks with multiple parents, invalid settings must be specified as
+ "<0>".
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a73a4-clock.h>
+ sdhi2_clk: sdhi2_clk@e615007c {
+ compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+ reg = <0xe615007c 4>;
+ clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
+ <&extal2_clk>;
+ #clock-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
deleted file mode 100644
index ae36ab84291988b7..0000000000000000
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-* Renesas CPG DIV6 Clock
-
-The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
-Generator (CPG). Their clock input is divided by a configurable factor from 1
-to 64.
-
-Required Properties:
-
- - compatible: Must be one of the following
- - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
- - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
- - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
- - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
- - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
- - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
- - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
- and "renesas,cpg-div6-clock" as a fallback.
- - reg: Base address and length of the memory resource used by the DIV6 clock
- - clocks: Reference to the parent clock(s); either one, four, or eight
- clocks must be specified. For clocks with multiple parents, invalid
- settings must be specified as "<0>".
- - #clock-cells: Must be 0
-
-
-Optional Properties:
-
- - clock-output-names: The name of the clock as a free-form string
-
-
-Example
--------
-
- sdhi2_clk: sdhi2_clk@e615007c {
- compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
- reg = <0 0xe615007c 0 4>;
- clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
- <0>, <&extal2_clk>;
- #clock-cells = <0>;
- clock-output-names = "sdhi2ck";
- };
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] dt-bindings: clock: renesas: div6: Convert to json-schema
2020-05-07 7:50 [PATCH] dt-bindings: clock: renesas: div6: Convert to json-schema Geert Uytterhoeven
@ 2020-05-12 15:16 ` Niklas Söderlund
2020-05-12 23:27 ` Stephen Boyd
2020-05-15 2:43 ` Rob Herring
2 siblings, 0 replies; 4+ messages in thread
From: Niklas Söderlund @ 2020-05-12 15:16 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Michael Turquette, Stephen Boyd, devicetree,
linux-clk, linux-renesas-soc
Hi Geert,
Thanks for your work.
On 2020-05-07 09:50:26 +0200, Geert Uytterhoeven wrote:
> Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to
> json-schema.
>
> Drop R-Car Gen2 compatible values, which were obsoleted by the unified
> "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
> bindings.
> Update the example to match reality.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> To be queued in clk-renesas-for-v5.8.
>
> .../clock/renesas,cpg-div6-clock.yaml | 60 +++++++++++++++++++
> .../clock/renesas,cpg-div6-clocks.txt | 40 -------------
> 2 files changed, 60 insertions(+), 40 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml
> delete mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml
> new file mode 100644
> index 0000000000000000..c55a7c494e013da5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas CPG DIV6 Clock
> +
> +maintainers:
> + - Geert Uytterhoeven <geert+renesas@glider.be>
> +
> +description:
> + The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
> + Generator (CPG). Their clock input is divided by a configurable factor from 1
> + to 64.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r8a73a4-div6-clock # R-Mobile APE6
> + - renesas,r8a7740-div6-clock # R-Mobile A1
> + - renesas,sh73a0-div6-clock # SH-Mobile AG5
> + - const: renesas,cpg-div6-clock
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + oneOf:
> + - maxItems: 1
> + - maxItems: 4
> + - maxItems: 8
> + description:
> + For clocks with multiple parents, invalid settings must be specified as
> + "<0>".
> +
> + '#clock-cells':
> + const: 0
> +
> + clock-output-names: true
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r8a73a4-clock.h>
> + sdhi2_clk: sdhi2_clk@e615007c {
> + compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
> + reg = <0xe615007c 4>;
> + clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
> + <&extal2_clk>;
> + #clock-cells = <0>;
> + };
> diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
> deleted file mode 100644
> index ae36ab84291988b7..0000000000000000
> --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
> +++ /dev/null
> @@ -1,40 +0,0 @@
> -* Renesas CPG DIV6 Clock
> -
> -The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
> -Generator (CPG). Their clock input is divided by a configurable factor from 1
> -to 64.
> -
> -Required Properties:
> -
> - - compatible: Must be one of the following
> - - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
> - - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
> - - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
> - - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
> - - "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
> - - "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
> - - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
> - and "renesas,cpg-div6-clock" as a fallback.
> - - reg: Base address and length of the memory resource used by the DIV6 clock
> - - clocks: Reference to the parent clock(s); either one, four, or eight
> - clocks must be specified. For clocks with multiple parents, invalid
> - settings must be specified as "<0>".
> - - #clock-cells: Must be 0
> -
> -
> -Optional Properties:
> -
> - - clock-output-names: The name of the clock as a free-form string
> -
> -
> -Example
> --------
> -
> - sdhi2_clk: sdhi2_clk@e615007c {
> - compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
> - reg = <0 0xe615007c 0 4>;
> - clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
> - <0>, <&extal2_clk>;
> - #clock-cells = <0>;
> - clock-output-names = "sdhi2ck";
> - };
> --
> 2.17.1
>
--
Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] dt-bindings: clock: renesas: div6: Convert to json-schema
2020-05-07 7:50 [PATCH] dt-bindings: clock: renesas: div6: Convert to json-schema Geert Uytterhoeven
2020-05-12 15:16 ` Niklas Söderlund
@ 2020-05-12 23:27 ` Stephen Boyd
2020-05-15 2:43 ` Rob Herring
2 siblings, 0 replies; 4+ messages in thread
From: Stephen Boyd @ 2020-05-12 23:27 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Rob Herring
Cc: devicetree, linux-clk, linux-renesas-soc, Geert Uytterhoeven
Quoting Geert Uytterhoeven (2020-05-07 00:50:26)
> Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to
> json-schema.
>
> Drop R-Car Gen2 compatible values, which were obsoleted by the unified
> "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
> bindings.
> Update the example to match reality.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] dt-bindings: clock: renesas: div6: Convert to json-schema
2020-05-07 7:50 [PATCH] dt-bindings: clock: renesas: div6: Convert to json-schema Geert Uytterhoeven
2020-05-12 15:16 ` Niklas Söderlund
2020-05-12 23:27 ` Stephen Boyd
@ 2020-05-15 2:43 ` Rob Herring
2 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2020-05-15 2:43 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Stephen Boyd, Rob Herring, linux-clk, linux-renesas-soc,
Michael Turquette, devicetree
On Thu, 7 May 2020 09:50:26 +0200, Geert Uytterhoeven wrote:
> Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to
> json-schema.
>
> Drop R-Car Gen2 compatible values, which were obsoleted by the unified
> "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
> bindings.
> Update the example to match reality.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> To be queued in clk-renesas-for-v5.8.
>
> .../clock/renesas,cpg-div6-clock.yaml | 60 +++++++++++++++++++
> .../clock/renesas,cpg-div6-clocks.txt | 40 -------------
> 2 files changed, 60 insertions(+), 40 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml
> delete mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2020-05-07 7:50 [PATCH] dt-bindings: clock: renesas: div6: Convert to json-schema Geert Uytterhoeven
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2020-05-12 23:27 ` Stephen Boyd
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