[PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document RZ/G2L MTU3 counter

[Biju Das <biju.das.jz@bp.renesas.com>]

Document 16-bit and 32-bit phase counting mode support on
RZ/G2L MTU3 IP.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 * Updated commit header.
---
 .../bindings/mfd/renesas,rzg2l-mtu3.yaml      | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
index c1fae8e8d9f9..c4bcf28623d6 100644
--- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
+++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml
@@ -192,6 +192,37 @@ properties:
   "#size-cells":
     const: 0
 
+patternProperties:
+  "^counter@[1-2]+$":
+    type: object
+
+    properties:
+      compatible:
+        const: renesas,rzg2l-mtu3-counter
+
+      reg:
+        description: Identify counter channels.
+        items:
+          enum: [ 1, 2 ]
+
+      renesas,32bit-phase-counting:
+        type: boolean
+        description: Enable 32-bit phase counting mode.
+
+      renesas,ext-input-phase-clock-select:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [ 0, 1 ]
+        default: 1
+        description: |
+          Selects the external clock pin for phase counting mode.
+            <0> : MTCLKA and MTCLKB are selected for the external phase clock.
+            <1> : MTCLKC and MTCLKD are selected for the external phase clock
+                  (default)
+
+    required:
+      - compatible
+      - reg
+
 required:
   - compatible
   - reg
@@ -270,6 +301,10 @@ examples:
       clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
       power-domains = <&cpg>;
       resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
+      counter@1 {
+        compatible = "renesas,rzg2l-mtu3-counter";
+        reg = <1>;
+      };
     };
 
 ...
-- 
2.25.1