* [PATCH 0/4] r8a779f0: update SCIF parent clocks
@ 2022-11-03 14:34 Wolfram Sang
2022-11-03 14:34 ` [PATCH 1/4] clk: renesas: r8a779f0: Fix HSCIF " Wolfram Sang
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Wolfram Sang @ 2022-11-03 14:34 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Geert Uytterhoeven, Wolfram Sang
Similar to what Geert found out for V4H, adapt the (H)SCIF clock parents
and baud rate generators to the parents mentioned in the updated
documentation. Slightly tested with SCIF on the Spider board in Kieran's
lab. But the HW engineers already confirmed Geert findings.
Wolfram Sang (4):
clk: renesas: r8a779f0: Fix HSCIF parent clocks
clk: renesas: r8a779f0: Fix SCIF parent clocks
arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock
arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 16 ++++++++--------
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 16 ++++++++--------
2 files changed, 16 insertions(+), 16 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/4] clk: renesas: r8a779f0: Fix HSCIF parent clocks
2022-11-03 14:34 [PATCH 0/4] r8a779f0: update SCIF parent clocks Wolfram Sang
@ 2022-11-03 14:34 ` Wolfram Sang
2022-11-07 16:08 ` Geert Uytterhoeven
2022-11-03 14:34 ` [PATCH 2/4] clk: renesas: r8a779f0: Fix SCIF " Wolfram Sang
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Wolfram Sang @ 2022-11-03 14:34 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Geert Uytterhoeven, Wolfram Sang
As serial communication requires a clean clock signal, the High Speed
Serial Communication Interfaces with FIFO (HSCIF) is clocked by a clock
that is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the parent clocks for the HSCIF modules from the S0D3_PER
clock to the SASYNCPERD1 clock (which has the same clock rate), cfr.
R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: 080bcd8d5997 ("clk: renesas: r8a779f0: Add HSCIF clocks")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index e4f2bbbfeb2d..fd1462425316 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -128,10 +128,10 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
- DEF_MOD("hscif0", 514, R8A779F0_CLK_S0D3),
- DEF_MOD("hscif1", 515, R8A779F0_CLK_S0D3),
- DEF_MOD("hscif2", 516, R8A779F0_CLK_S0D3),
- DEF_MOD("hscif3", 517, R8A779F0_CLK_S0D3),
+ DEF_MOD("hscif0", 514, R8A779F0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif1", 515, R8A779F0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif2", 516, R8A779F0_CLK_SASYNCPERD1),
+ DEF_MOD("hscif3", 517, R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
--
2.35.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 2/4] clk: renesas: r8a779f0: Fix SCIF parent clocks
2022-11-03 14:34 [PATCH 0/4] r8a779f0: update SCIF parent clocks Wolfram Sang
2022-11-03 14:34 ` [PATCH 1/4] clk: renesas: r8a779f0: Fix HSCIF " Wolfram Sang
@ 2022-11-03 14:34 ` Wolfram Sang
2022-11-07 16:11 ` Geert Uytterhoeven
2022-11-03 14:34 ` [PATCH 3/4] arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock Wolfram Sang
2022-11-03 14:34 ` [PATCH 4/4] arm64: dts: renesas: r8a779f0: Fix SCIF " Wolfram Sang
3 siblings, 1 reply; 10+ messages in thread
From: Wolfram Sang @ 2022-11-03 14:34 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Geert Uytterhoeven, Wolfram Sang
As serial communication requires a clean clock signal, the Serial
Communication Interfaces with FIFO (SCIF) is clocked by a clock that is
not affected by Spread Spectrum or Fractional Multiplication.
Hence change the parent clocks for the SCIF modules from the S0D12_PER
clock to the SASYNCPERD4 clock (which has the same clock rate), cfr.
R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index fd1462425316..800fdc104edd 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -144,10 +144,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
DEF_MOD("msiof3", 621, R8A779F0_CLK_MSO),
DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2),
DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2),
- DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER),
- DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER),
- DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER),
- DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER),
+ DEF_MOD("scif0", 702, R8A779F0_CLK_SASYNCPERD4),
+ DEF_MOD("scif1", 703, R8A779F0_CLK_SASYNCPERD4),
+ DEF_MOD("scif3", 704, R8A779F0_CLK_SASYNCPERD4),
+ DEF_MOD("scif4", 705, R8A779F0_CLK_SASYNCPERD4),
DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0),
DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
--
2.35.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/4] arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock
2022-11-03 14:34 [PATCH 0/4] r8a779f0: update SCIF parent clocks Wolfram Sang
2022-11-03 14:34 ` [PATCH 1/4] clk: renesas: r8a779f0: Fix HSCIF " Wolfram Sang
2022-11-03 14:34 ` [PATCH 2/4] clk: renesas: r8a779f0: Fix SCIF " Wolfram Sang
@ 2022-11-03 14:34 ` Wolfram Sang
2022-11-07 16:13 ` Geert Uytterhoeven
2022-11-03 14:34 ` [PATCH 4/4] arm64: dts: renesas: r8a779f0: Fix SCIF " Wolfram Sang
3 siblings, 1 reply; 10+ messages in thread
From: Wolfram Sang @ 2022-11-03 14:34 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Geert Uytterhoeven, Wolfram Sang
As serial communication requires a clock signal, the High Speed Serial
Communication Interfaces with FIFO (HSCIF) are clocked by a clock that
is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the clock input for the HSCIF Baud Rate Generator internal
clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: 01a787f78bfd ("arm64: dts: renesas: r8a779f0: Add HSCIF nodes")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index c2f152bcf10e..3be577dc9a93 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -577,7 +577,7 @@ hscif0: serial@e6540000 {
reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x31>, <&dmac0 0x30>,
@@ -594,7 +594,7 @@ hscif1: serial@e6550000 {
reg = <0 0xe6550000 0 0x60>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x33>, <&dmac0 0x32>,
@@ -611,7 +611,7 @@ hscif2: serial@e6560000 {
reg = <0 0xe6560000 0 0x60>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 516>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x35>, <&dmac0 0x34>,
@@ -628,7 +628,7 @@ hscif3: serial@e66a0000 {
reg = <0 0xe66a0000 0 0x60>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x37>, <&dmac0 0x36>,
--
2.35.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 4/4] arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock
2022-11-03 14:34 [PATCH 0/4] r8a779f0: update SCIF parent clocks Wolfram Sang
` (2 preceding siblings ...)
2022-11-03 14:34 ` [PATCH 3/4] arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock Wolfram Sang
@ 2022-11-03 14:34 ` Wolfram Sang
2022-11-07 16:13 ` Geert Uytterhoeven
3 siblings, 1 reply; 10+ messages in thread
From: Wolfram Sang @ 2022-11-03 14:34 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Geert Uytterhoeven, Wolfram Sang
As serial communication requires a clock signal, the Serial
Communication Interfaces with FIFO (SCIF) are clocked by a clock that
is not affected by Spread Spectrum or Fractional Multiplication.
Hence change the clock input for the SCIF Baud Rate Generator internal
clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.
Fixes: c62331e8222f ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support")
Fixes: 40753144256b ("arm64: dts: renesas: r8a779f0: Add SCIF nodes")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 3be577dc9a93..4092c0016035 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -657,7 +657,7 @@ scif0: serial@e6e60000 {
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x51>, <&dmac0 0x50>,
@@ -674,7 +674,7 @@ scif1: serial@e6e68000 {
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x53>, <&dmac0 0x52>,
@@ -691,7 +691,7 @@ scif3: serial@e6c50000 {
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x57>, <&dmac0 0x56>,
@@ -708,7 +708,7 @@ scif4: serial@e6c40000 {
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>,
- <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+ <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x59>, <&dmac0 0x58>,
--
2.35.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/4] clk: renesas: r8a779f0: Fix HSCIF parent clocks
2022-11-03 14:34 ` [PATCH 1/4] clk: renesas: r8a779f0: Fix HSCIF " Wolfram Sang
@ 2022-11-07 16:08 ` Geert Uytterhoeven
0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2022-11-07 16:08 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-renesas-soc
On Thu, Nov 3, 2022 at 3:34 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> As serial communication requires a clean clock signal, the High Speed
> Serial Communication Interfaces with FIFO (HSCIF) is clocked by a clock
> that is not affected by Spread Spectrum or Fractional Multiplication.
>
> Hence change the parent clocks for the HSCIF modules from the S0D3_PER
> clock to the SASYNCPERD1 clock (which has the same clock rate), cfr.
> R-Car S4-8 Hardware User's Manual rev. 0.81.
>
> Fixes: 080bcd8d5997 ("clk: renesas: r8a779f0: Add HSCIF clocks")
> Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.2.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/4] clk: renesas: r8a779f0: Fix SCIF parent clocks
2022-11-03 14:34 ` [PATCH 2/4] clk: renesas: r8a779f0: Fix SCIF " Wolfram Sang
@ 2022-11-07 16:11 ` Geert Uytterhoeven
0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2022-11-07 16:11 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-renesas-soc
On Thu, Nov 3, 2022 at 3:34 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> As serial communication requires a clean clock signal, the Serial
> Communication Interfaces with FIFO (SCIF) is clocked by a clock that is
> not affected by Spread Spectrum or Fractional Multiplication.
>
> Hence change the parent clocks for the SCIF modules from the S0D12_PER
> clock to the SASYNCPERD4 clock (which has the same clock rate), cfr.
> R-Car S4-8 Hardware User's Manual rev. 0.81.
>
> Fixes: 24aaff6a6ce4 ("clk: renesas: cpg-mssr: Add support for R-Car S4-8")
> Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.2.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/4] arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock
2022-11-03 14:34 ` [PATCH 3/4] arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock Wolfram Sang
@ 2022-11-07 16:13 ` Geert Uytterhoeven
2022-11-07 19:18 ` Wolfram Sang
0 siblings, 1 reply; 10+ messages in thread
From: Geert Uytterhoeven @ 2022-11-07 16:13 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-renesas-soc
On Thu, Nov 3, 2022 at 3:34 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> As serial communication requires a clock signal, the High Speed Serial
I see the missing "clean" introduced by me is propagating ;-)
> Communication Interfaces with FIFO (HSCIF) are clocked by a clock that
> is not affected by Spread Spectrum or Fractional Multiplication.
>
> Hence change the clock input for the HSCIF Baud Rate Generator internal
> clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
> same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.
>
> Fixes: 01a787f78bfd ("arm64: dts: renesas: r8a779f0: Add HSCIF nodes")
> Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.2, with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/4] arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock
2022-11-03 14:34 ` [PATCH 4/4] arm64: dts: renesas: r8a779f0: Fix SCIF " Wolfram Sang
@ 2022-11-07 16:13 ` Geert Uytterhoeven
0 siblings, 0 replies; 10+ messages in thread
From: Geert Uytterhoeven @ 2022-11-07 16:13 UTC (permalink / raw)
To: Wolfram Sang; +Cc: linux-renesas-soc
On Thu, Nov 3, 2022 at 3:34 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> As serial communication requires a clock signal, the Serial
clean clock
> Communication Interfaces with FIFO (SCIF) are clocked by a clock that
> is not affected by Spread Spectrum or Fractional Multiplication.
>
> Hence change the clock input for the SCIF Baud Rate Generator internal
> clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
> same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.
>
> Fixes: c62331e8222f ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support")
> Fixes: 40753144256b ("arm64: dts: renesas: r8a779f0: Add SCIF nodes")
> Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.2, with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/4] arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock
2022-11-07 16:13 ` Geert Uytterhoeven
@ 2022-11-07 19:18 ` Wolfram Sang
0 siblings, 0 replies; 10+ messages in thread
From: Wolfram Sang @ 2022-11-07 19:18 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: linux-renesas-soc
[-- Attachment #1: Type: text/plain, Size: 416 bytes --]
On Mon, Nov 07, 2022 at 05:13:15PM +0100, Geert Uytterhoeven wrote:
> On Thu, Nov 3, 2022 at 3:34 PM Wolfram Sang
> <wsa+renesas@sang-engineering.com> wrote:
> > As serial communication requires a clock signal, the High Speed Serial
>
> I see the missing "clean" introduced by me is propagating ;-)
:D Except for the missing word, this is an awesome description, so it
should spread. Thanks for fixing!
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^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-11-07 19:18 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
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2022-11-03 14:34 [PATCH 0/4] r8a779f0: update SCIF parent clocks Wolfram Sang
2022-11-03 14:34 ` [PATCH 1/4] clk: renesas: r8a779f0: Fix HSCIF " Wolfram Sang
2022-11-07 16:08 ` Geert Uytterhoeven
2022-11-03 14:34 ` [PATCH 2/4] clk: renesas: r8a779f0: Fix SCIF " Wolfram Sang
2022-11-07 16:11 ` Geert Uytterhoeven
2022-11-03 14:34 ` [PATCH 3/4] arm64: dts: renesas: r8a779f0: Fix HSCIF "brg_int" clock Wolfram Sang
2022-11-07 16:13 ` Geert Uytterhoeven
2022-11-07 19:18 ` Wolfram Sang
2022-11-03 14:34 ` [PATCH 4/4] arm64: dts: renesas: r8a779f0: Fix SCIF " Wolfram Sang
2022-11-07 16:13 ` Geert Uytterhoeven
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