* [RFC PATCH 0/4] Add missing pins for RZ/Five SoC
@ 2023-06-30 12:04 Prabhakar
2023-06-30 12:04 ` [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar
` (4 more replies)
0 siblings, 5 replies; 18+ messages in thread
From: Prabhakar @ 2023-06-30 12:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Biju Das, Prabhakar, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Geert,
This patch series intends to incorporate the absent port pins P19 to P28,
which are exclusively available on the RZ/Five SoC.
I am submitting this series as an RFC (Request for Comments) as the port
pins P19 to P28 cannot be utilized as GPIO but can be utilized as
multiplexed pins. Additionally, certain attributes such as setting the
ISEL would necessitate a device tree property to indicate ISEL. Therefore,
before proceeding with the addition of comprehensive support, I would
appreciate some input on whether an alternative approach could be considered.
Cheers,
Prabhakar
Lad Prabhakar (4):
pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK()
macro
pinctrl: renesas: pinctrl-rzg2l: Add validation of GPIO pin in
rzg2l_gpio_request()
pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28
riscv: dts: renesas: r9a07g043f: Update gpio-ranges property
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 263 +++++++++++++-------
2 files changed, 176 insertions(+), 91 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-06-30 12:04 [RFC PATCH 0/4] Add missing pins for RZ/Five SoC Prabhakar
@ 2023-06-30 12:04 ` Prabhakar
2023-07-03 11:42 ` Biju Das
` (2 more replies)
2023-06-30 12:04 ` [RFC PATCH 2/4] pinctrl: renesas: pinctrl-rzg2l: Add validation of GPIO pin in rzg2l_gpio_request() Prabhakar
` (3 subsequent siblings)
4 siblings, 3 replies; 18+ messages in thread
From: Prabhakar @ 2023-06-30 12:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Biju Das, Prabhakar, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Currently we assume all the port pins are sequential ie always PX_0 to
PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to
P28_5 which have holes in them, for example only one pin on port19 is
available and that is P19_1 and not P19_0.
So to handle such cases include pinmap for each port which would indicate
the pin availability on each port. With this we also get additional pin
validation, for example on the RZ/G2L SOC P0 has two pins P0_1 and P0_0
but with DT/SYSFS could use the P0_2-P0_7.
While at it, update rzg2l_validate_gpio_pin() to use the port pinmap to
validate the gpio pin.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167 ++++++++++++------------
1 file changed, 86 insertions(+), 81 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 9511d920565e..a0c2e585e765 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -67,10 +67,12 @@
PIN_CFG_FILCLKSEL)
/*
- * n indicates number of pins in the port, a is the register index
- * and f is pin configuration capabilities supported.
+ * m indicates the bitmap of supported pins, n indicates number
+ * of pins in the port, a is the register index and f is pin
+ * configuration capabilities supported.
*/
-#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f))
+#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) | (UL(n) << 28) | ((a) << 20) | (f))
+#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK(39, 32)) >> 32)
#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
#define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20)
#define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0))
@@ -129,7 +131,7 @@ struct rzg2l_dedicated_configs {
struct rzg2l_pinctrl_data {
const char * const *port_pins;
- const u32 *port_pin_configs;
+ const u64 *port_pin_configs;
unsigned int n_ports;
struct rzg2l_dedicated_configs *dedicated_pins;
unsigned int n_port_pins;
@@ -445,13 +447,16 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
}
static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
- u32 cfg, u32 port, u8 bit)
+ u64 cfg, u32 port, u8 bit)
{
- u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
- u32 data;
+ u8 pinmap = RZG2L_GPIO_PORT_GET_PINMAP(cfg);
+ u64 data;
- if (bit >= pincount || port >= pctrl->data->n_port_pins)
+ if (port >= pctrl->data->n_port_pins)
+ return -EINVAL;
+
+ if (!(pinmap & BIT(bit)))
return -EINVAL;
data = pctrl->data->port_pin_configs[port];
@@ -501,7 +506,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
- unsigned int *pin_data = pin->drv_data;
+ u64 *pin_data = pin->drv_data;
unsigned int arg = 0;
unsigned long flags;
void __iomem *addr;
@@ -591,7 +596,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
{
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
- unsigned int *pin_data = pin->drv_data;
+ u64 *pin_data = pin->drv_data;
enum pin_config_param param;
unsigned long flags;
void __iomem *addr;
@@ -965,78 +970,78 @@ static const char * const rzg2l_gpio_names[] = {
"P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7",
};
-static const u32 rzg2l_gpio_configs[] = {
- RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
+static const u64 rzg2l_gpio_configs[] = {
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x10, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x11, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x12, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x13, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x14, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x15, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x16, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x17, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x18, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x19, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x21, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x22, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x23, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x36, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x37, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x38, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x39, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x40, RZG2L_MPXED_PIN_FUNCS),
};
-static const u32 r9a07g043_gpio_configs[] = {
- RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
- RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
- RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
- RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
+static const u64 r9a07g043_gpio_configs[] = {
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x10, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x15, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x16, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x21, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS),
};
static struct {
@@ -1396,7 +1401,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)
{
struct pinctrl_pin_desc *pins;
unsigned int i, j;
- u32 *pin_data;
+ u64 *pin_data;
int ret;
pctrl->desc.name = DRV_NAME;
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH 2/4] pinctrl: renesas: pinctrl-rzg2l: Add validation of GPIO pin in rzg2l_gpio_request()
2023-06-30 12:04 [RFC PATCH 0/4] Add missing pins for RZ/Five SoC Prabhakar
2023-06-30 12:04 ` [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar
@ 2023-06-30 12:04 ` Prabhakar
2023-06-30 12:04 ` [RFC PATCH 3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Prabhakar
` (2 subsequent siblings)
4 siblings, 0 replies; 18+ messages in thread
From: Prabhakar @ 2023-06-30 12:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Biju Das, Prabhakar, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Validate the GPIO pin request in rzg2l_gpio_request() callback using
rzg2l_validate_gpio_pin() function.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index a0c2e585e765..2fc1b880db0c 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -780,12 +780,18 @@ static const struct pinconf_ops rzg2l_pinctrl_confops = {
static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
{
struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);
+ const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[offset];
+ u64 *pin_data = pin->drv_data;
u32 port = RZG2L_PIN_ID_TO_PORT(offset);
u8 bit = RZG2L_PIN_ID_TO_PIN(offset);
unsigned long flags;
u8 reg8;
int ret;
+ ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
+ if (ret)
+ return ret;
+
ret = pinctrl_gpio_request(chip->base + offset);
if (ret)
return ret;
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH 3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28
2023-06-30 12:04 [RFC PATCH 0/4] Add missing pins for RZ/Five SoC Prabhakar
2023-06-30 12:04 ` [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar
2023-06-30 12:04 ` [RFC PATCH 2/4] pinctrl: renesas: pinctrl-rzg2l: Add validation of GPIO pin in rzg2l_gpio_request() Prabhakar
@ 2023-06-30 12:04 ` Prabhakar
2023-07-10 14:18 ` Geert Uytterhoeven
2023-06-30 12:04 ` [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property Prabhakar
2023-07-10 14:05 ` [RFC PATCH 0/4] Add missing pins for RZ/Five SoC Geert Uytterhoeven
4 siblings, 1 reply; 18+ messages in thread
From: Prabhakar @ 2023-06-30 12:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Biju Das, Prabhakar, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins
provide expanded capabilities and are exclusive to the RZ/Five SoC.
Furthermore, a new variant called r9a07g043_data has been introduced
specifically for the RZ/Five SoC. When CONFIG_RISCV is enabled, this
variant replaces the previous data configuration. Additionally, a new macro
named PIN_CFG_NOGPIO has been implemented. This macro serves as an
indicator to determine whether the port pins can be utilized as GPIO pins.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Please note that I have only included the necessary changes for PFC
settings in this paragraph. However, further work is required to set
the attributes of the pin. While we already have generic properties in
place for most of the attributes, setting the ISEL attribute for those
pins may require a specific property unique to Renesas. Alternatively,
is there a possibility of addressing this requirement in a different manner?
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 94 +++++++++++++++++++++----
1 file changed, 82 insertions(+), 12 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 2fc1b880db0c..61004733c2eb 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -15,6 +15,7 @@
#include <linux/of_irq.h>
#include <linux/seq_file.h>
#include <linux/spinlock.h>
+#include <linux/sys_soc.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
@@ -53,6 +54,7 @@
#define PIN_CFG_FILONOFF BIT(10)
#define PIN_CFG_FILNUM BIT(11)
#define PIN_CFG_FILCLKSEL BIT(12)
+#define PIN_CFG_NOGPIO BIT(13)
#define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
PIN_CFG_SR | \
@@ -101,6 +103,12 @@
#define SD_CH(n) (0x3000 + (n) * 4)
#define QSPI (0x3008)
+#define RZFIVE_P_EX(n) (0x0000 + 0x06 + ((n) - 19))
+#define RZFIVE_PM_EX(n) (0x0100 + 0x0c + ((n) - 19) * 2)
+#define RZFIVE_PMC_EX(n) (0x0200 + 0x06 + ((n) - 19))
+#define RZFIVE_PFC_EX(n) (0x0400 + 0x18 + ((n) - 19) * 4)
+#define RZFIVE_PIN_EX(n) (0x0800 + 0x06 + ((n) - 19))
+
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
#define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
@@ -160,39 +168,53 @@ struct rzg2l_pinctrl {
static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };
static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
+static const struct soc_device_attribute rzfive_match[] = {
+ { .family = "RZ/Five" },
+ { /* sentinel */}
+};
+
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
u8 port, u8 pin, u8 func)
{
+ u32 pm_offset = PM(port);
+ u32 pmc_offset = PMC(port);
+ u32 pfc_offset = PFC(port);
unsigned long flags;
u32 reg;
+ if (soc_device_match(rzfive_match) && port > 18) {
+ pm_offset = RZFIVE_PM_EX(port);
+ pmc_offset = RZFIVE_PMC_EX(port);
+ pfc_offset = RZFIVE_PFC_EX(port);
+ }
+
spin_lock_irqsave(&pctrl->lock, flags);
/* Set pin to 'Non-use (Hi-Z input protection)' */
- reg = readw(pctrl->base + PM(port));
+ reg = readw(pctrl->base + pm_offset);
reg &= ~(PM_MASK << (pin * 2));
- writew(reg, pctrl->base + PM(port));
+ writew(reg, pctrl->base + pm_offset);
/* Temporarily switch to GPIO mode with PMC register */
- reg = readb(pctrl->base + PMC(port));
- writeb(reg & ~BIT(pin), pctrl->base + PMC(port));
+ reg = readb(pctrl->base + pmc_offset);
+ writeb(reg & ~BIT(pin), pctrl->base + pmc_offset);
/* Set the PWPR register to allow PFC register to write */
writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */
/* Select Pin function mode with PFC register */
- reg = readl(pctrl->base + PFC(port));
+ reg = readl(pctrl->base + pfc_offset);
reg &= ~(PFC_MASK << (pin * 4));
- writel(reg | (func << (pin * 4)), pctrl->base + PFC(port));
+ writel(reg | (func << (pin * 4)), pctrl->base + pfc_offset);
/* Set the PWPR register to be write-protected */
writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */
/* Switch to Peripheral pin function with PMC register */
- reg = readb(pctrl->base + PMC(port));
- writeb(reg | BIT(pin), pctrl->base + PMC(port));
+ reg = readb(pctrl->base + pmc_offset);
+ writeb(reg | BIT(pin), pctrl->base + pmc_offset);
spin_unlock_irqrestore(&pctrl->lock, flags);
};
@@ -447,12 +469,15 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,
}
static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
- u64 cfg, u32 port, u8 bit)
+ u64 cfg, u32 port, u8 bit, bool pfc)
{
u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
u8 pinmap = RZG2L_GPIO_PORT_GET_PINMAP(cfg);
u64 data;
+ if (!pfc && (cfg & PIN_CFG_NOGPIO))
+ return -EINVAL;
+
if (port >= pctrl->data->n_port_pins)
return -EINVAL;
@@ -526,7 +551,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
bit = RZG2L_PIN_ID_TO_PIN(_pin);
- if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
+ if (rzg2l_validate_gpio_pin(pctrl, *pin_data,
+ RZG2L_PIN_ID_TO_PORT(_pin), bit, true))
return -EINVAL;
}
@@ -617,7 +643,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin);
bit = RZG2L_PIN_ID_TO_PIN(_pin);
- if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))
+ if (rzg2l_validate_gpio_pin(pctrl, *pin_data,
+ RZG2L_PIN_ID_TO_PORT(_pin), bit, true))
return -EINVAL;
}
@@ -788,7 +815,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)
u8 reg8;
int ret;
- ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
+ ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit, false);
if (ret)
return ret;
@@ -1050,6 +1077,38 @@ static const u64 r9a07g043_gpio_configs[] = {
RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS),
};
+static const u64 r9a07g043f_gpio_configs[] = {
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x10, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x15, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x16, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x21, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS),
+ RZG2L_GPIO_PORT_PACK(0x02, 1, 0x06, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
+ RZG2L_GPIO_PORT_PACK(0xff, 8, 0x07, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
+ RZG2L_GPIO_PORT_PACK(0x02, 1, 0x08, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO)),
+ RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x09, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO)),
+ RZG2L_GPIO_PORT_PACK(0x3e, 5, 0x0a, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO)),
+ RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x0b, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
+ RZG2L_GPIO_PORT_PACK(0x02, 1, 0x0c, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
+ RZG2L_GPIO_PORT_PACK(0x00, 0, 0x0d, 0x0),
+ RZG2L_GPIO_PORT_PACK(0x00, 0, 0x0e, 0x0),
+ RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
+};
+
static struct {
struct rzg2l_dedicated_configs common[35];
struct rzg2l_dedicated_configs rzg2l_pins[7];
@@ -1534,6 +1593,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
return 0;
}
+#ifdef CONFIG_RISCV
+static struct rzg2l_pinctrl_data r9a07g043_data = {
+ .port_pins = rzg2l_gpio_names,
+ .port_pin_configs = r9a07g043f_gpio_configs,
+ .n_ports = ARRAY_SIZE(r9a07g043f_gpio_configs),
+ .dedicated_pins = rzg2l_dedicated_pins.common,
+ .n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT,
+ .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
+};
+#else
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
@@ -1542,6 +1611,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
};
+#endif
static struct rzg2l_pinctrl_data r9a07g044_data = {
.port_pins = rzg2l_gpio_names,
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property
2023-06-30 12:04 [RFC PATCH 0/4] Add missing pins for RZ/Five SoC Prabhakar
` (2 preceding siblings ...)
2023-06-30 12:04 ` [RFC PATCH 3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Prabhakar
@ 2023-06-30 12:04 ` Prabhakar
2023-07-10 14:21 ` Geert Uytterhoeven
2023-07-10 14:05 ` [RFC PATCH 0/4] Add missing pins for RZ/Five SoC Geert Uytterhoeven
4 siblings, 1 reply; 18+ messages in thread
From: Prabhakar @ 2023-06-30 12:04 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Biju Das, Prabhakar, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update
the gpio-ranges property in RZ/Five SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index b0796015e36b..e68a91c9fe77 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -42,6 +42,10 @@ cpu0_intc: interrupt-controller {
};
};
+&pinctrl {
+ gpio-ranges = <&pinctrl 0 0 232>;
+};
+
&soc {
dma-noncoherent;
interrupt-parent = <&plic>;
--
2.34.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* RE: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-06-30 12:04 ` [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar
@ 2023-07-03 11:42 ` Biju Das
2023-07-03 12:43 ` Lad, Prabhakar
2023-07-04 8:30 ` Biju Das
2023-07-10 14:12 ` Geert Uytterhoeven
2 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2023-07-03 11:42 UTC (permalink / raw)
To: Prabhakar, Geert Uytterhoeven, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Prabhakar Mahadev Lad
Hi Prabhakar,
Thanks for the patch.
> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Friday, June 30, 2023 1:05 PM
> To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> <magnus.damm@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> <biju.das.jz@bp.renesas.com>; Prabhakar <prabhakar.csengg@gmail.com>;
> Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> RZG2L_GPIO_PORT_PACK() macro
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Currently we assume all the port pins are sequential ie always PX_0 to
> PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to
> P28_5 which have holes in them, for example only one pin on port19 is
> available and that is P19_1 and not P19_0.
>
> So to handle such cases include pinmap for each port which would
> indicate the pin availability on each port. With this we also get
> additional pin validation, for example on the RZ/G2L SOC P0 has two pins
> P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
>
> While at it, update rzg2l_validate_gpio_pin() to use the port pinmap to
> validate the gpio pin.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167 ++++++++++++------------
> 1 file changed, 86 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 9511d920565e..a0c2e585e765 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -67,10 +67,12 @@
> PIN_CFG_FILCLKSEL)
>
> /*
> - * n indicates number of pins in the port, a is the register index
> - * and f is pin configuration capabilities supported.
> + * m indicates the bitmap of supported pins, n indicates number
> + * of pins in the port, a is the register index and f is pin
> + * configuration capabilities supported.
> */
> -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) |
> (f))
> +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) | (UL(n) << 28)
> | ((a) << 20) | (f))
I guess, you can still achieve RZG2L_GPIO_PORT_PACK(n, a, f) with
((UL(PINMAP(n)) << 32) | (UL(n) << 28) | ((a) << 20) | (f))
#define PINMAP(n) GENMASK(n,0) ?? Then you don't need to modify rzg2l_gpio_configs.
Cheers,
Biju
> +#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK(39, 32)) >> 32)
> #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
> #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20)
> #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0))
> @@ -129,7 +131,7 @@ struct rzg2l_dedicated_configs {
>
> struct rzg2l_pinctrl_data {
> const char * const *port_pins;
> - const u32 *port_pin_configs;
> + const u64 *port_pin_configs;
> unsigned int n_ports;
> struct rzg2l_dedicated_configs *dedicated_pins;
> unsigned int n_port_pins;
> @@ -445,13 +447,16 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev
> *pctldev, }
>
> static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
> - u32 cfg, u32 port, u8 bit)
> + u64 cfg, u32 port, u8 bit)
> {
> - u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
> u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
> - u32 data;
> + u8 pinmap = RZG2L_GPIO_PORT_GET_PINMAP(cfg);
> + u64 data;
>
> - if (bit >= pincount || port >= pctrl->data->n_port_pins)
> + if (port >= pctrl->data->n_port_pins)
> + return -EINVAL;
> +
> + if (!(pinmap & BIT(bit)))
> return -EINVAL;
>
> data = pctrl->data->port_pin_configs[port];
> @@ -501,7 +506,7 @@ static int rzg2l_pinctrl_pinconf_get(struct
> pinctrl_dev *pctldev,
> struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> enum pin_config_param param = pinconf_to_config_param(*config);
> const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
> - unsigned int *pin_data = pin->drv_data;
> + u64 *pin_data = pin->drv_data;
> unsigned int arg = 0;
> unsigned long flags;
> void __iomem *addr;
> @@ -591,7 +596,7 @@ static int rzg2l_pinctrl_pinconf_set(struct
> pinctrl_dev *pctldev, {
> struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
> - unsigned int *pin_data = pin->drv_data;
> + u64 *pin_data = pin->drv_data;
> enum pin_config_param param;
> unsigned long flags;
> void __iomem *addr;
> @@ -965,78 +970,78 @@ static const char * const rzg2l_gpio_names[] = {
> "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6",
> "P48_7", };
>
> -static const u32 rzg2l_gpio_configs[] = {
> - RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x24,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x25,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x26,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x27,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x28,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x29,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2a,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2b,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2c,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2d,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2e,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2f,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x30,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x31,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x32,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x33,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x34,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(3, 0x35,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
> +static const u64 rzg2l_gpio_configs[] = {
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x10, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x11, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x12, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x13, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x14, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x15, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x16, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x17, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x18, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x19, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x21, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x22, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x23, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x24,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x25,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x26,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x27,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x28,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x29,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2a,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2b,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2c,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2d,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2e,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2f,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x30,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x31,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x32,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x33,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x34,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x35,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x36, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x37, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x38, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x39, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x40, RZG2L_MPXED_PIN_FUNCS),
> };
>
> -static const u32 r9a07g043_gpio_configs[] = {
> - RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x11,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(4, 0x12,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(4, 0x13,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(6, 0x14,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x17,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(5, 0x18,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(4, 0x19,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(5, 0x1a,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
> +static const u64 r9a07g043_gpio_configs[] = {
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x10, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x11,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x12,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x13,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x14,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x15, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x16, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x17,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x18,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x19,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1a,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x21, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS),
> };
>
> static struct {
> @@ -1396,7 +1401,7 @@ static int rzg2l_pinctrl_register(struct
> rzg2l_pinctrl *pctrl) {
> struct pinctrl_pin_desc *pins;
> unsigned int i, j;
> - u32 *pin_data;
> + u64 *pin_data;
> int ret;
>
> pctrl->desc.name = DRV_NAME;
> --
> 2.34.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-07-03 11:42 ` Biju Das
@ 2023-07-03 12:43 ` Lad, Prabhakar
2023-07-03 14:13 ` Biju Das
0 siblings, 1 reply; 18+ messages in thread
From: Lad, Prabhakar @ 2023-07-03 12:43 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Linus Walleij, linux-renesas-soc,
devicetree, linux-riscv, linux-kernel, linux-gpio,
Prabhakar Mahadev Lad
Hi Biju,
Thank you for the review.
On Mon, Jul 3, 2023 at 12:42 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Friday, June 30, 2023 1:05 PM
> > To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > <magnus.damm@gmail.com>
> > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> > <biju.das.jz@bp.renesas.com>; Prabhakar <prabhakar.csengg@gmail.com>;
> > Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > RZG2L_GPIO_PORT_PACK() macro
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Currently we assume all the port pins are sequential ie always PX_0 to
> > PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to
> > P28_5 which have holes in them, for example only one pin on port19 is
> > available and that is P19_1 and not P19_0.
> >
> > So to handle such cases include pinmap for each port which would
> > indicate the pin availability on each port. With this we also get
> > additional pin validation, for example on the RZ/G2L SOC P0 has two pins
> > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
> >
> > While at it, update rzg2l_validate_gpio_pin() to use the port pinmap to
> > validate the gpio pin.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167 ++++++++++++------------
> > 1 file changed, 86 insertions(+), 81 deletions(-)
> >
> > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > index 9511d920565e..a0c2e585e765 100644
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > @@ -67,10 +67,12 @@
> > PIN_CFG_FILCLKSEL)
> >
> > /*
> > - * n indicates number of pins in the port, a is the register index
> > - * and f is pin configuration capabilities supported.
> > + * m indicates the bitmap of supported pins, n indicates number
> > + * of pins in the port, a is the register index and f is pin
> > + * configuration capabilities supported.
> > */
> > -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) |
> > (f))
> > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) | (UL(n) << 28)
> > | ((a) << 20) | (f))
>
> I guess, you can still achieve RZG2L_GPIO_PORT_PACK(n, a, f) with
> ((UL(PINMAP(n)) << 32) | (UL(n) << 28) | ((a) << 20) | (f))
>
> #define PINMAP(n) GENMASK(n,0) ?? Then you don't need to modify rzg2l_gpio_configs.
>
Good point, but this would work if port pins didn't have any holes.
For example on RZ/Five port P19 we have P19_1 pin only and P19_0 is
not available (and similarly for port P25 we have P25_1).
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-07-03 12:43 ` Lad, Prabhakar
@ 2023-07-03 14:13 ` Biju Das
2023-07-03 21:10 ` Lad, Prabhakar
2023-07-10 14:14 ` Geert Uytterhoeven
0 siblings, 2 replies; 18+ messages in thread
From: Biju Das @ 2023-07-03 14:13 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Linus Walleij, linux-renesas-soc,
devicetree, linux-riscv, linux-kernel, linux-gpio,
Prabhakar Mahadev Lad
Hi Prabhakar,
> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Monday, July 3, 2023 1:43 PM
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Prabhakar Mahadev
> Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> RZG2L_GPIO_PORT_PACK() macro
>
> Hi Biju,
>
> Thank you for the review.
>
> On Mon, Jul 3, 2023 at 12:42 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Friday, June 30, 2023 1:05 PM
> > > To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > > <magnus.damm@gmail.com>
> > > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > > <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> > > <biju.das.jz@bp.renesas.com>; Prabhakar
> > > <prabhakar.csengg@gmail.com>; Prabhakar Mahadev Lad
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > > RZG2L_GPIO_PORT_PACK() macro
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Currently we assume all the port pins are sequential ie always PX_0
> > > to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins
> > > P19_1 to
> > > P28_5 which have holes in them, for example only one pin on port19
> > > is available and that is P19_1 and not P19_0.
> > >
> > > So to handle such cases include pinmap for each port which would
> > > indicate the pin availability on each port. With this we also get
> > > additional pin validation, for example on the RZ/G2L SOC P0 has two
> > > pins
> > > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
> > >
> > > While at it, update rzg2l_validate_gpio_pin() to use the port pinmap
> > > to validate the gpio pin.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167
> > > ++++++++++++------------
> > > 1 file changed, 86 insertions(+), 81 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > index 9511d920565e..a0c2e585e765 100644
> > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > @@ -67,10 +67,12 @@
> > > PIN_CFG_FILCLKSEL)
> > >
> > > /*
> > > - * n indicates number of pins in the port, a is the register index
> > > - * and f is pin configuration capabilities supported.
> > > + * m indicates the bitmap of supported pins, n indicates number
> > > + * of pins in the port, a is the register index and f is pin
> > > + * configuration capabilities supported.
> > > */
> > > -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) <<
> 20) |
> > > (f))
> > > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) |
> (UL(n) << 28)
> > > | ((a) << 20) | (f))
> >
> > I guess, you can still achieve RZG2L_GPIO_PORT_PACK(n, a, f) with
> > ((UL(PINMAP(n)) << 32) | (UL(n) << 28) | ((a) << 20) | (f))
> >
> > #define PINMAP(n) GENMASK(n,0) ?? Then you don't need to modify
> rzg2l_gpio_configs.
> >
> Good point, but this would work if port pins didn't have any holes.
> For example on RZ/Five port P19 we have P19_1 pin only and P19_0 is not
> available (and similarly for port P25 we have P25_1).
Maybe introduce a helper macro to address this case.
#define RZG2L_GPIO_PORT_PACK_WITH_HOLES(m, n, a, f) for these 2 cases
and use RZG2L_GPIO_PORT_PACK(n, a, f) for the one without holes.
Cheers,
Biju
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-07-03 14:13 ` Biju Das
@ 2023-07-03 21:10 ` Lad, Prabhakar
2023-07-10 14:14 ` Geert Uytterhoeven
1 sibling, 0 replies; 18+ messages in thread
From: Lad, Prabhakar @ 2023-07-03 21:10 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Linus Walleij, linux-renesas-soc,
devicetree, linux-riscv, linux-kernel, linux-gpio,
Prabhakar Mahadev Lad
Hi Biju,
On Mon, Jul 3, 2023 at 3:13 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Monday, July 3, 2023 1:43 PM
> > To: Biju Das <biju.das.jz@bp.renesas.com>
> > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> > Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Prabhakar Mahadev
> > Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > RZG2L_GPIO_PORT_PACK() macro
> >
> > Hi Biju,
> >
> > Thank you for the review.
> >
> > On Mon, Jul 3, 2023 at 12:42 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > Thanks for the patch.
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Friday, June 30, 2023 1:05 PM
> > > > To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > > > <magnus.damm@gmail.com>
> > > > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > > > <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > > > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > > > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > > > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> > > > <biju.das.jz@bp.renesas.com>; Prabhakar
> > > > <prabhakar.csengg@gmail.com>; Prabhakar Mahadev Lad
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > > > RZG2L_GPIO_PORT_PACK() macro
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Currently we assume all the port pins are sequential ie always PX_0
> > > > to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins
> > > > P19_1 to
> > > > P28_5 which have holes in them, for example only one pin on port19
> > > > is available and that is P19_1 and not P19_0.
> > > >
> > > > So to handle such cases include pinmap for each port which would
> > > > indicate the pin availability on each port. With this we also get
> > > > additional pin validation, for example on the RZ/G2L SOC P0 has two
> > > > pins
> > > > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
> > > >
> > > > While at it, update rzg2l_validate_gpio_pin() to use the port pinmap
> > > > to validate the gpio pin.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167
> > > > ++++++++++++------------
> > > > 1 file changed, 86 insertions(+), 81 deletions(-)
> > > >
> > > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > index 9511d920565e..a0c2e585e765 100644
> > > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > @@ -67,10 +67,12 @@
> > > > PIN_CFG_FILCLKSEL)
> > > >
> > > > /*
> > > > - * n indicates number of pins in the port, a is the register index
> > > > - * and f is pin configuration capabilities supported.
> > > > + * m indicates the bitmap of supported pins, n indicates number
> > > > + * of pins in the port, a is the register index and f is pin
> > > > + * configuration capabilities supported.
> > > > */
> > > > -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) <<
> > 20) |
> > > > (f))
> > > > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) |
> > (UL(n) << 28)
> > > > | ((a) << 20) | (f))
> > >
> > > I guess, you can still achieve RZG2L_GPIO_PORT_PACK(n, a, f) with
> > > ((UL(PINMAP(n)) << 32) | (UL(n) << 28) | ((a) << 20) | (f))
> > >
> > > #define PINMAP(n) GENMASK(n,0) ?? Then you don't need to modify
> > rzg2l_gpio_configs.
> > >
> > Good point, but this would work if port pins didn't have any holes.
> > For example on RZ/Five port P19 we have P19_1 pin only and P19_0 is not
> > available (and similarly for port P25 we have P25_1).
>
> Maybe introduce a helper macro to address this case.
>
> #define RZG2L_GPIO_PORT_PACK_WITH_HOLES(m, n, a, f) for these 2 cases
>
> and use RZG2L_GPIO_PORT_PACK(n, a, f) for the one without holes.
>
Agreed will do.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-06-30 12:04 ` [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar
2023-07-03 11:42 ` Biju Das
@ 2023-07-04 8:30 ` Biju Das
2023-07-04 8:35 ` Lad, Prabhakar
2023-07-10 14:12 ` Geert Uytterhoeven
2 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2023-07-04 8:30 UTC (permalink / raw)
To: Prabhakar, Geert Uytterhoeven, Magnus Damm
Cc: Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Prabhakar Mahadev Lad
Hi Prabhakar,
> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Friday, June 30, 2023 1:05 PM
> To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> <magnus.damm@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> <biju.das.jz@bp.renesas.com>; Prabhakar <prabhakar.csengg@gmail.com>;
> Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> RZG2L_GPIO_PORT_PACK() macro
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Currently we assume all the port pins are sequential ie always PX_0 to
> PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to
> P28_5 which have holes in them, for example only one pin on port19 is
> available and that is P19_1 and not P19_0.
>
> So to handle such cases include pinmap for each port which would
> indicate the pin availability on each port. With this we also get
> additional pin validation, for example on the RZ/G2L SOC P0 has two pins
> P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
>
> While at it, update rzg2l_validate_gpio_pin() to use the port pinmap to
> validate the gpio pin.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167 ++++++++++++------------
> 1 file changed, 86 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 9511d920565e..a0c2e585e765 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -67,10 +67,12 @@
> PIN_CFG_FILCLKSEL)
>
> /*
> - * n indicates number of pins in the port, a is the register index
> - * and f is pin configuration capabilities supported.
> + * m indicates the bitmap of supported pins, n indicates number
> + * of pins in the port, a is the register index and f is pin
> + * configuration capabilities supported.
> */
> -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) |
> (f))
> +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) | (UL(n) << 28)
> | ((a) << 20) | (f))
> +#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK(39, 32)) >> 32)
> #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
> #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20)
> #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0))
> @@ -129,7 +131,7 @@ struct rzg2l_dedicated_configs {
>
> struct rzg2l_pinctrl_data {
> const char * const *port_pins;
> - const u32 *port_pin_configs;
> + const u64 *port_pin_configs;
Can this be SoC specific? Only for RZ/Five you need this changes.
Others SoCs like RZ/{G2L,G2LC,V2L and G2UL) still work with u32* as there
is no holes. With this change memory usage is doubled as we change from
u32->u64.
Cheers,
Biju
> unsigned int n_ports;
> struct rzg2l_dedicated_configs *dedicated_pins;
> unsigned int n_port_pins;
> @@ -445,13 +447,16 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev
> *pctldev, }
>
> static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
> - u32 cfg, u32 port, u8 bit)
> + u64 cfg, u32 port, u8 bit)
> {
> - u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
> u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg);
> - u32 data;
> + u8 pinmap = RZG2L_GPIO_PORT_GET_PINMAP(cfg);
> + u64 data;
>
> - if (bit >= pincount || port >= pctrl->data->n_port_pins)
> + if (port >= pctrl->data->n_port_pins)
> + return -EINVAL;
> +
> + if (!(pinmap & BIT(bit)))
> return -EINVAL;
>
> data = pctrl->data->port_pin_configs[port];
> @@ -501,7 +506,7 @@ static int rzg2l_pinctrl_pinconf_get(struct
> pinctrl_dev *pctldev,
> struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> enum pin_config_param param = pinconf_to_config_param(*config);
> const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
> - unsigned int *pin_data = pin->drv_data;
> + u64 *pin_data = pin->drv_data;
> unsigned int arg = 0;
> unsigned long flags;
> void __iomem *addr;
> @@ -591,7 +596,7 @@ static int rzg2l_pinctrl_pinconf_set(struct
> pinctrl_dev *pctldev, {
> struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
> - unsigned int *pin_data = pin->drv_data;
> + u64 *pin_data = pin->drv_data;
> enum pin_config_param param;
> unsigned long flags;
> void __iomem *addr;
> @@ -965,78 +970,78 @@ static const char * const rzg2l_gpio_names[] = {
> "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6",
> "P48_7", };
>
> -static const u32 rzg2l_gpio_configs[] = {
> - RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x24,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x25,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x26,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x27,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x28,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x29,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2a,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2b,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2c,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2d,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2e,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x2f,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x30,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x31,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x32,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x33,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x34,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(3, 0x35,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS),
> +static const u64 rzg2l_gpio_configs[] = {
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x10, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x11, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x12, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x13, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x14, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x15, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x16, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x17, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x18, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x19, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1a, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1b, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1d, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1e, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1f, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x21, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x22, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x23, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x24,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x25,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x26,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x27,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x28,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x29,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2a,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2b,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2c,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2d,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2e,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x2f,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x30,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x31,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x32,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x33,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x34,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x35,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x36, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x37, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x38, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x39, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x3a, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3b, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3c, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3d, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3e, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x3f, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x40, RZG2L_MPXED_PIN_FUNCS),
> };
>
> -static const u32 r9a07g043_gpio_configs[] = {
> - RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x11,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(4, 0x12,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(4, 0x13,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(6, 0x14,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> - RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x17,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(5, 0x18,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(4, 0x19,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(5, 0x1a,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> - RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),
> - RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),
> +static const u64 r9a07g043_gpio_configs[] = {
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x10, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x11,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x12,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x13,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x14,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x15, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x16, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x17,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x18,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x19,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1a,
> RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x21, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS),
> };
>
> static struct {
> @@ -1396,7 +1401,7 @@ static int rzg2l_pinctrl_register(struct
> rzg2l_pinctrl *pctrl) {
> struct pinctrl_pin_desc *pins;
> unsigned int i, j;
> - u32 *pin_data;
> + u64 *pin_data;
> int ret;
>
> pctrl->desc.name = DRV_NAME;
> --
> 2.34.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-07-04 8:30 ` Biju Das
@ 2023-07-04 8:35 ` Lad, Prabhakar
2023-07-04 8:42 ` Biju Das
0 siblings, 1 reply; 18+ messages in thread
From: Lad, Prabhakar @ 2023-07-04 8:35 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Linus Walleij, linux-renesas-soc,
devicetree, linux-riscv, linux-kernel, linux-gpio,
Prabhakar Mahadev Lad
Hi Biju,
On Tue, Jul 4, 2023 at 9:30 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Friday, June 30, 2023 1:05 PM
> > To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > <magnus.damm@gmail.com>
> > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> > <biju.das.jz@bp.renesas.com>; Prabhakar <prabhakar.csengg@gmail.com>;
> > Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > RZG2L_GPIO_PORT_PACK() macro
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Currently we assume all the port pins are sequential ie always PX_0 to
> > PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to
> > P28_5 which have holes in them, for example only one pin on port19 is
> > available and that is P19_1 and not P19_0.
> >
> > So to handle such cases include pinmap for each port which would
> > indicate the pin availability on each port. With this we also get
> > additional pin validation, for example on the RZ/G2L SOC P0 has two pins
> > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
> >
> > While at it, update rzg2l_validate_gpio_pin() to use the port pinmap to
> > validate the gpio pin.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167 ++++++++++++------------
> > 1 file changed, 86 insertions(+), 81 deletions(-)
> >
> > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > index 9511d920565e..a0c2e585e765 100644
> > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > @@ -67,10 +67,12 @@
> > PIN_CFG_FILCLKSEL)
> >
> > /*
> > - * n indicates number of pins in the port, a is the register index
> > - * and f is pin configuration capabilities supported.
> > + * m indicates the bitmap of supported pins, n indicates number
> > + * of pins in the port, a is the register index and f is pin
> > + * configuration capabilities supported.
> > */
> > -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) |
> > (f))
> > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) | (UL(n) << 28)
> > | ((a) << 20) | (f))
> > +#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK(39, 32)) >> 32)
> > #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
> > #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20)
> > #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0))
> > @@ -129,7 +131,7 @@ struct rzg2l_dedicated_configs {
> >
> > struct rzg2l_pinctrl_data {
> > const char * const *port_pins;
> > - const u32 *port_pin_configs;
> > + const u64 *port_pin_configs;
>
> Can this be SoC specific? Only for RZ/Five you need this changes.
> Others SoCs like RZ/{G2L,G2LC,V2L and G2UL) still work with u32* as there
> is no holes. With this change memory usage is doubled as we change from
> u32->u64.
>
This is to avoid writing to undocumented registers so I have added for
all the SoCs. For example on the RZ/G2L SOC P0 has two pins P0_1 and
P0_0 but DT/SYSFS could use the P0_2-P0_7. This patch restricts users
to use only available GPIO pins.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-07-04 8:35 ` Lad, Prabhakar
@ 2023-07-04 8:42 ` Biju Das
2023-07-04 8:47 ` Lad, Prabhakar
0 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2023-07-04 8:42 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Linus Walleij, linux-renesas-soc,
devicetree, linux-riscv, linux-kernel, linux-gpio,
Prabhakar Mahadev Lad
Hi Prabhakar,
> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Tuesday, July 4, 2023 9:36 AM
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Prabhakar Mahadev
> Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> RZG2L_GPIO_PORT_PACK() macro
>
> Hi Biju,
>
> On Tue, Jul 4, 2023 at 9:30 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Friday, June 30, 2023 1:05 PM
> > > To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > > <magnus.damm@gmail.com>
> > > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > > <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> > > <biju.das.jz@bp.renesas.com>; Prabhakar
> > > <prabhakar.csengg@gmail.com>; Prabhakar Mahadev Lad
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > > RZG2L_GPIO_PORT_PACK() macro
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Currently we assume all the port pins are sequential ie always PX_0
> > > to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins
> > > P19_1 to
> > > P28_5 which have holes in them, for example only one pin on port19
> > > is available and that is P19_1 and not P19_0.
> > >
> > > So to handle such cases include pinmap for each port which would
> > > indicate the pin availability on each port. With this we also get
> > > additional pin validation, for example on the RZ/G2L SOC P0 has two
> > > pins
> > > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
> > >
> > > While at it, update rzg2l_validate_gpio_pin() to use the port pinmap
> > > to validate the gpio pin.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167
> > > ++++++++++++------------
> > > 1 file changed, 86 insertions(+), 81 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > index 9511d920565e..a0c2e585e765 100644
> > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > @@ -67,10 +67,12 @@
> > > PIN_CFG_FILCLKSEL)
> > >
> > > /*
> > > - * n indicates number of pins in the port, a is the register index
> > > - * and f is pin configuration capabilities supported.
> > > + * m indicates the bitmap of supported pins, n indicates number
> > > + * of pins in the port, a is the register index and f is pin
> > > + * configuration capabilities supported.
> > > */
> > > -#define RZG2L_GPIO_PORT_PACK(
, a, f) (((n) << 28) | ((a) <<
> 20) |
> > > (f))
> > > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) |
> (UL(n) << 28)
> > > | ((a) << 20) | (f))
> > > +#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK(39,
> 32)) >> 32)
> > > #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30,
> 28)) >> 28)
> > > #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >>
> > > 20) #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) @@
> > > -129,7 +131,7 @@ struct rzg2l_dedicated_configs {
> > >
> > > struct rzg2l_pinctrl_data {
> > > const char * const *port_pins;
> > > - const u32 *port_pin_configs;
> > > + const u64 *port_pin_configs;
> >
> > Can this be SoC specific? Only for RZ/Five you need this changes.
> > Others SoCs like RZ/{G2L,G2LC,V2L and G2UL) still work with u32* as
> > there is no holes. With this change memory usage is doubled as we
> > change from
> > u32->u64.
> >
> This is to avoid writing to undocumented registers so I have added for
> all the SoCs. For example on the RZ/G2L SOC P0 has two pins P0_1 and
> P0_0 but DT/SYSFS could use the P0_2-P0_7. This patch restricts users to
> use only available GPIO pins.
I guess that still can be achieved, as the below macro has valid
pins info??
#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
if (!(BIT(bit) & GENMASK(RZG2L_GPIO_PORT_GET_PINCNT(x), 0))
return -EINVAL;
Cheers,
Biju
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-07-04 8:42 ` Biju Das
@ 2023-07-04 8:47 ` Lad, Prabhakar
0 siblings, 0 replies; 18+ messages in thread
From: Lad, Prabhakar @ 2023-07-04 8:47 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Linus Walleij, linux-renesas-soc,
devicetree, linux-riscv, linux-kernel, linux-gpio,
Prabhakar Mahadev Lad
On Tue, Jul 4, 2023 at 9:42 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Tuesday, July 4, 2023 9:36 AM
> > To: Biju Das <biju.das.jz@bp.renesas.com>
> > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> > Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Prabhakar Mahadev
> > Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > RZG2L_GPIO_PORT_PACK() macro
> >
> > Hi Biju,
> >
> > On Tue, Jul 4, 2023 at 9:30 AM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Friday, June 30, 2023 1:05 PM
> > > > To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > > > <magnus.damm@gmail.com>
> > > > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > > > <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > > > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > > > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > > > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> > > > <biju.das.jz@bp.renesas.com>; Prabhakar
> > > > <prabhakar.csengg@gmail.com>; Prabhakar Mahadev Lad
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > > > RZG2L_GPIO_PORT_PACK() macro
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Currently we assume all the port pins are sequential ie always PX_0
> > > > to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins
> > > > P19_1 to
> > > > P28_5 which have holes in them, for example only one pin on port19
> > > > is available and that is P19_1 and not P19_0.
> > > >
> > > > So to handle such cases include pinmap for each port which would
> > > > indicate the pin availability on each port. With this we also get
> > > > additional pin validation, for example on the RZ/G2L SOC P0 has two
> > > > pins
> > > > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
> > > >
> > > > While at it, update rzg2l_validate_gpio_pin() to use the port pinmap
> > > > to validate the gpio pin.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167
> > > > ++++++++++++------------
> > > > 1 file changed, 86 insertions(+), 81 deletions(-)
> > > >
> > > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > index 9511d920565e..a0c2e585e765 100644
> > > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > @@ -67,10 +67,12 @@
> > > > PIN_CFG_FILCLKSEL)
> > > >
> > > > /*
> > > > - * n indicates number of pins in the port, a is the register index
> > > > - * and f is pin configuration capabilities supported.
> > > > + * m indicates the bitmap of supported pins, n indicates number
> > > > + * of pins in the port, a is the register index and f is pin
> > > > + * configuration capabilities supported.
> > > > */
> > > > -#define RZG2L_GPIO_PORT_PACK(
>
> , a, f) (((n) << 28) | ((a) <<
> > 20) |
> > > > (f))
> > > > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) |
> > (UL(n) << 28)
> > > > | ((a) << 20) | (f))
> > > > +#define RZG2L_GPIO_PORT_GET_PINMAP(x) (((x) & GENMASK(39,
> > 32)) >> 32)
> > > > #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30,
> > 28)) >> 28)
> > > > #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >>
> > > > 20) #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) @@
> > > > -129,7 +131,7 @@ struct rzg2l_dedicated_configs {
> > > >
> > > > struct rzg2l_pinctrl_data {
> > > > const char * const *port_pins;
> > > > - const u32 *port_pin_configs;
> > > > + const u64 *port_pin_configs;
> > >
> > > Can this be SoC specific? Only for RZ/Five you need this changes.
> > > Others SoCs like RZ/{G2L,G2LC,V2L and G2UL) still work with u32* as
> > > there is no holes. With this change memory usage is doubled as we
> > > change from
> > > u32->u64.
> > >
> > This is to avoid writing to undocumented registers so I have added for
> > all the SoCs. For example on the RZ/G2L SOC P0 has two pins P0_1 and
> > P0_0 but DT/SYSFS could use the P0_2-P0_7. This patch restricts users to
> > use only available GPIO pins.
>
> I guess that still can be achieved, as the below macro has valid
> pins info??
>
> #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28)
>
> if (!(BIT(bit) & GENMASK(RZG2L_GPIO_PORT_GET_PINCNT(x), 0))
> return -EINVAL;
>
Agreed, If Geert is OK to have SoC specific checks around I'll do the above.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH 0/4] Add missing pins for RZ/Five SoC
2023-06-30 12:04 [RFC PATCH 0/4] Add missing pins for RZ/Five SoC Prabhakar
` (3 preceding siblings ...)
2023-06-30 12:04 ` [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property Prabhakar
@ 2023-07-10 14:05 ` Geert Uytterhoeven
4 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2023-07-10 14:05 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Biju Das, Lad Prabhakar
Hi Prabhakar,
On Fri, Jun 30, 2023 at 2:04 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> This patch series intends to incorporate the absent port pins P19 to P28,
> which are exclusively available on the RZ/Five SoC.
Are you sure these are not available on RZ/G2UL?
I thought RZ/Five and RZ/G2UL were identical, except for the ARM
vs. RISC-V CPU core (+ support)?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-06-30 12:04 ` [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar
2023-07-03 11:42 ` Biju Das
2023-07-04 8:30 ` Biju Das
@ 2023-07-10 14:12 ` Geert Uytterhoeven
2 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2023-07-10 14:12 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Biju Das, Lad Prabhakar
Hi Prabhakar,
On Fri, Jun 30, 2023 at 2:05 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Currently we assume all the port pins are sequential ie always PX_0 to
> PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to
> P28_5 which have holes in them, for example only one pin on port19 is
> available and that is P19_1 and not P19_0.
>
> So to handle such cases include pinmap for each port which would indicate
> the pin availability on each port. With this we also get additional pin
> validation, for example on the RZ/G2L SOC P0 has two pins P0_1 and P0_0
> but with DT/SYSFS could use the P0_2-P0_7.
>
> While at it, update rzg2l_validate_gpio_pin() to use the port pinmap to
> validate the gpio pin.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167 ++++++++++++------------
> 1 file changed, 86 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 9511d920565e..a0c2e585e765 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -67,10 +67,12 @@
> PIN_CFG_FILCLKSEL)
>
> /*
> - * n indicates number of pins in the port, a is the register index
> - * and f is pin configuration capabilities supported.
> + * m indicates the bitmap of supported pins, n indicates number
> + * of pins in the port, a is the register index and f is pin
> + * configuration capabilities supported.
> */
> -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f))
> +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) | (UL(n) << 28) | ((a) << 20) | (f))
Do we actually need 20 bits for the "f" field?
As Biju already commented, "n" can be derived from "m".
If "f" can be shrunk, we might fit everything in 32 bits.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro
2023-07-03 14:13 ` Biju Das
2023-07-03 21:10 ` Lad, Prabhakar
@ 2023-07-10 14:14 ` Geert Uytterhoeven
1 sibling, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2023-07-10 14:14 UTC (permalink / raw)
To: Biju Das
Cc: Lad, Prabhakar, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Linus Walleij, linux-renesas-soc, devicetree, linux-riscv,
linux-kernel, linux-gpio, Prabhakar Mahadev Lad
Hi Biju,
On Mon, Jul 3, 2023 at 4:13 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Monday, July 3, 2023 1:43 PM
> > To: Biju Das <biju.das.jz@bp.renesas.com>
> > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > <magnus.damm@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof
> > Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Prabhakar Mahadev
> > Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Subject: Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > RZG2L_GPIO_PORT_PACK() macro
> >
> > On Mon, Jul 3, 2023 at 12:42 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Friday, June 30, 2023 1:05 PM
> > > > To: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > > > <magnus.damm@gmail.com>
> > > > Cc: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski
> > > > <krzysztof.kozlowski+dt@linaro.org>; Linus Walleij
> > > > <linus.walleij@linaro.org>; linux-renesas-soc@vger.kernel.org;
> > > > devicetree@vger.kernel.org; linux-riscv@lists.infradead.org; linux-
> > > > kernel@vger.kernel.org; linux-gpio@vger.kernel.org; Biju Das
> > > > <biju.das.jz@bp.renesas.com>; Prabhakar
> > > > <prabhakar.csengg@gmail.com>; Prabhakar Mahadev Lad
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > > > RZG2L_GPIO_PORT_PACK() macro
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Currently we assume all the port pins are sequential ie always PX_0
> > > > to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins
> > > > P19_1 to
> > > > P28_5 which have holes in them, for example only one pin on port19
> > > > is available and that is P19_1 and not P19_0.
> > > >
> > > > So to handle such cases include pinmap for each port which would
> > > > indicate the pin availability on each port. With this we also get
> > > > additional pin validation, for example on the RZ/G2L SOC P0 has two
> > > > pins
> > > > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
> > > >
> > > > While at it, update rzg2l_validate_gpio_pin() to use the port pinmap
> > > > to validate the gpio pin.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167
> > > > ++++++++++++------------
> > > > 1 file changed, 86 insertions(+), 81 deletions(-)
> > > >
> > > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > index 9511d920565e..a0c2e585e765 100644
> > > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > > @@ -67,10 +67,12 @@
> > > > PIN_CFG_FILCLKSEL)
> > > >
> > > > /*
> > > > - * n indicates number of pins in the port, a is the register index
> > > > - * and f is pin configuration capabilities supported.
> > > > + * m indicates the bitmap of supported pins, n indicates number
> > > > + * of pins in the port, a is the register index and f is pin
> > > > + * configuration capabilities supported.
> > > > */
> > > > -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) <<
> > 20) |
> > > > (f))
> > > > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f) ((UL(m) << 32) |
> > (UL(n) << 28)
> > > > | ((a) << 20) | (f))
> > >
> > > I guess, you can still achieve RZG2L_GPIO_PORT_PACK(n, a, f) with
> > > ((UL(PINMAP(n)) << 32) | (UL(n) << 28) | ((a) << 20) | (f))
> > >
> > > #define PINMAP(n) GENMASK(n,0) ?? Then you don't need to modify
> > rzg2l_gpio_configs.
> > >
> > Good point, but this would work if port pins didn't have any holes.
> > For example on RZ/Five port P19 we have P19_1 pin only and P19_0 is not
> > available (and similarly for port P25 we have P25_1).
>
> Maybe introduce a helper macro to address this case.
>
> #define RZG2L_GPIO_PORT_PACK_WITH_HOLES(m, n, a, f) for these 2 cases
"sparse" is the terse term.
#define RZG2L_GPIO_PORT_PACK_SPARSE(m, a, f)
as "n" can be derived from "m"
> and use RZG2L_GPIO_PORT_PACK(n, a, f) for the one without holes.
Exactly.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH 3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28
2023-06-30 12:04 ` [RFC PATCH 3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Prabhakar
@ 2023-07-10 14:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2023-07-10 14:18 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Biju Das, Lad Prabhakar
Hi Prabhakar,
On Fri, Jun 30, 2023 at 2:05 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins
> provide expanded capabilities and are exclusive to the RZ/Five SoC.
> Furthermore, a new variant called r9a07g043_data has been introduced
> specifically for the RZ/Five SoC. When CONFIG_RISCV is enabled, this
> variant replaces the previous data configuration. Additionally, a new macro
> named PIN_CFG_NOGPIO has been implemented. This macro serves as an
> indicator to determine whether the port pins can be utilized as GPIO pins.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -15,6 +15,7 @@
> #include <linux/of_irq.h>
> #include <linux/seq_file.h>
> #include <linux/spinlock.h>
> +#include <linux/sys_soc.h>
>
> #include <linux/pinctrl/consumer.h>
> #include <linux/pinctrl/pinconf-generic.h>
> @@ -53,6 +54,7 @@
> #define PIN_CFG_FILONOFF BIT(10)
> #define PIN_CFG_FILNUM BIT(11)
> #define PIN_CFG_FILCLKSEL BIT(12)
> +#define PIN_CFG_NOGPIO BIT(13)
>
> #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \
> PIN_CFG_SR | \
> @@ -101,6 +103,12 @@
> #define SD_CH(n) (0x3000 + (n) * 4)
> #define QSPI (0x3008)
>
> +#define RZFIVE_P_EX(n) (0x0000 + 0x06 + ((n) - 19))
> +#define RZFIVE_PM_EX(n) (0x0100 + 0x0c + ((n) - 19) * 2)
> +#define RZFIVE_PMC_EX(n) (0x0200 + 0x06 + ((n) - 19))
> +#define RZFIVE_PFC_EX(n) (0x0400 + 0x18 + ((n) - 19) * 4)
> +#define RZFIVE_PIN_EX(n) (0x0800 + 0x06 + ((n) - 19))
> +
> #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
> #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
>
> @@ -160,39 +168,53 @@ struct rzg2l_pinctrl {
> static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 };
> static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
>
> +static const struct soc_device_attribute rzfive_match[] = {
> + { .family = "RZ/Five" },
> + { /* sentinel */}
> +};
> +
> static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> u8 port, u8 pin, u8 func)
> {
> + u32 pm_offset = PM(port);
> + u32 pmc_offset = PMC(port);
> + u32 pfc_offset = PFC(port);
> unsigned long flags;
> u32 reg;
>
> + if (soc_device_match(rzfive_match) && port > 18) {
Please no soc_device_match() outside .probe() callbacks.
> + pm_offset = RZFIVE_PM_EX(port);
> + pmc_offset = RZFIVE_PMC_EX(port);
> + pfc_offset = RZFIVE_PFC_EX(port);
> + }
> +
> spin_lock_irqsave(&pctrl->lock, flags);
> @@ -1050,6 +1077,38 @@ static const u64 r9a07g043_gpio_configs[] = {
> RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS),
> };
>
> +static const u64 r9a07g043f_gpio_configs[] = {
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x10, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x15, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x16, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1b, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x1c, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x1f, 5, 0x1d, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x07, 3, 0x1e, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x1f, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x03, 2, 0x20, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x21, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x22, RZG2L_MPXED_PIN_FUNCS),
> + RZG2L_GPIO_PORT_PACK(0x02, 1, 0x06, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
Aha, so that's where P19-P28 are hiding: in the P06-P0F registers :-(
> + RZG2L_GPIO_PORT_PACK(0xff, 8, 0x07, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
> + RZG2L_GPIO_PORT_PACK(0x02, 1, 0x08, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO)),
> + RZG2L_GPIO_PORT_PACK(0x0f, 4, 0x09, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO)),
> + RZG2L_GPIO_PORT_PACK(0x3e, 5, 0x0a, (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOGPIO)),
> + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x0b, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
> + RZG2L_GPIO_PORT_PACK(0x02, 1, 0x0c, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
> + RZG2L_GPIO_PORT_PACK(0x00, 0, 0x0d, 0x0),
> + RZG2L_GPIO_PORT_PACK(0x00, 0, 0x0e, 0x0),
> + RZG2L_GPIO_PORT_PACK(0x3f, 6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO),
> +};
> +
> static struct {
> struct rzg2l_dedicated_configs common[35];
> struct rzg2l_dedicated_configs rzg2l_pins[7];
> @@ -1534,6 +1593,16 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
> return 0;
> }
>
> +#ifdef CONFIG_RISCV
> +static struct rzg2l_pinctrl_data r9a07g043_data = {
> + .port_pins = rzg2l_gpio_names,
> + .port_pin_configs = r9a07g043f_gpio_configs,
> + .n_ports = ARRAY_SIZE(r9a07g043f_gpio_configs),
> + .dedicated_pins = rzg2l_dedicated_pins.common,
> + .n_port_pins = ARRAY_SIZE(r9a07g043f_gpio_configs) * RZG2L_PINS_PER_PORT,
> + .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
> +};
I can't really say I'm excited about this...
> +#else
> static struct rzg2l_pinctrl_data r9a07g043_data = {
> .port_pins = rzg2l_gpio_names,
> .port_pin_configs = r9a07g043_gpio_configs,
> @@ -1542,6 +1611,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
> .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
> .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
> };
> +#endif
>
> static struct rzg2l_pinctrl_data r9a07g044_data = {
> .port_pins = rzg2l_gpio_names,
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property
2023-06-30 12:04 ` [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property Prabhakar
@ 2023-07-10 14:21 ` Geert Uytterhoeven
0 siblings, 0 replies; 18+ messages in thread
From: Geert Uytterhoeven @ 2023-07-10 14:21 UTC (permalink / raw)
To: Prabhakar
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Linus Walleij,
linux-renesas-soc, devicetree, linux-riscv, linux-kernel,
linux-gpio, Biju Das, Lad Prabhakar
Hi Prabhakar,
On Fri, Jun 30, 2023 at 2:05 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update
> the gpio-ranges property in RZ/Five SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -42,6 +42,10 @@ cpu0_intc: interrupt-controller {
> };
> };
>
> +&pinctrl {
> + gpio-ranges = <&pinctrl 0 0 232>;
Is that correct? You only have 32 more pins than on r9a07g043u,
which uses:
gpio-ranges = <&pinctrl 0 0 152>;
> +};
> +
> &soc {
> dma-noncoherent;
> interrupt-parent = <&plic>;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2023-07-10 14:21 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-30 12:04 [RFC PATCH 0/4] Add missing pins for RZ/Five SoC Prabhakar
2023-06-30 12:04 ` [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Prabhakar
2023-07-03 11:42 ` Biju Das
2023-07-03 12:43 ` Lad, Prabhakar
2023-07-03 14:13 ` Biju Das
2023-07-03 21:10 ` Lad, Prabhakar
2023-07-10 14:14 ` Geert Uytterhoeven
2023-07-04 8:30 ` Biju Das
2023-07-04 8:35 ` Lad, Prabhakar
2023-07-04 8:42 ` Biju Das
2023-07-04 8:47 ` Lad, Prabhakar
2023-07-10 14:12 ` Geert Uytterhoeven
2023-06-30 12:04 ` [RFC PATCH 2/4] pinctrl: renesas: pinctrl-rzg2l: Add validation of GPIO pin in rzg2l_gpio_request() Prabhakar
2023-06-30 12:04 ` [RFC PATCH 3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Prabhakar
2023-07-10 14:18 ` Geert Uytterhoeven
2023-06-30 12:04 ` [RFC PATCH 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property Prabhakar
2023-07-10 14:21 ` Geert Uytterhoeven
2023-07-10 14:05 ` [RFC PATCH 0/4] Add missing pins for RZ/Five SoC Geert Uytterhoeven
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