* [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions
@ 2022-06-14 5:57 Kuninori Morimoto
2022-06-14 5:58 ` [PATCH v3 01/21] dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support Kuninori Morimoto
` (20 more replies)
0 siblings, 21 replies; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:57 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
Hi Geert
These are v3 of V4H (r8a779g0) pinctrl patches.
These are based on renesas-pinctrl/renesas-pinctrl-for-v5.20.
As I have mentioned before, I want to keep original code as much as
possible to avoid unexpected bug at [03/21][04/21].
v3 patch uses incremental patch to add missing pin settings, etc.
Basically, [03/21][04/21] of v3 is cleaup comment, alphabetical order, etc,
no code was changed. [05/21] or later change the code.
Please let me know if something was missing.
I'm happy to add it as incremental patch.
This patch didn't care about GP1_23 - GP1_28 voltage control,
because the code is same as document.
This patch didn't care about RMII pins, because I'm not sure.
This patch didn't care about I2C-capable pins, because I'm not sure.
v2 -> v2
- for [03/21]
- remove "core.h"
- drop DRV1 from CANFD7 comment
- rename pinmux_ops to r8a779g0_pfc_ops
- fixup comment XR_TXENA_N -> FXR_TXENA_N
- fixup comment RPC_RESET -> RPC_RESET_N
- fixup TPU0TO1/TPU0TO0 order at PUEN2
- for [04/21]
- Missing blank line.
- sort modules alphabetically
- fixup comment RX,TX -> RX1, TX1
- fixup comment MSIOF1_xxx -> MSIOF2_xxx
- fixup comment RTS3#/CTS3# -> RTS3_N/CTS3_N
- fixup comment RTS1#/CTS1# -> RTS1_N/CTS1_N
- add missing pin settings.
v1 -> v2
- add r8a779g0 on renesas,pfc Document at [1/4]
- use CFG_13 on CFG_14 [2/4]
- tidyup WARNINGs [3/4]
- tidyup tab and/or white space
- care reserve bit/fields
- fixup settings miss
- tidyup tab and/or white space [4/4]
[01/21] dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support
[02/21] pinctrl: renesas: Add PORT_GP_CFG_13 macros
[03/21] pinctrl: renesas: Initial R8A779G0 (V4H) PFC support
[04/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions
[05/21] pinctrl: renesas: r8a779g0: remove not used NOGP definitions
[06/21] pinctrl: renesas: r8a779g0: remove not used IPxSRx definitions
[07/21] pinctrl: renesas: r8a779g0: remove not used MOD_SELx definitions
[08/21] pinctrl: renesas: r8a779g0: tidyup ioctrl_regs
[09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X
[10/21] pinctrl: renesas: r8a779g0: add missing IRQx_A/IRQx_B
[11/21] pinctrl: renesas: r8a779g0: add missing HSCIF3_A
[12/21] pinctrl: renesas: r8a779g0: add missing HSCIF1_X
[13/21] pinctrl: renesas: r8a779g0: add missing SCIF3
[14/21] pinctrl: renesas: r8a779g0: add missing SCIF1_X
[15/21] pinctrl: renesas: r8a779g0: add missing CANFD5_B
[16/21] pinctrl: renesas: r8a779g0: add missing TPU0TOx_A
[17/21] pinctrl: renesas: r8a779g0: add missing FlaxRay
[18/21] pinctrl: renesas: r8a779g0: add missing PWM
[19/21] pinctrl: renesas: r8a779g0: add missing ERROROUTC_A
[20/21] pinctrl: renesas: r8a779g0: add missing MODSELx for TSN0
[21/21] pinctrl: renesas: r8a779g0: add missing MODSELx for AVBx
.../bindings/pinctrl/renesas,pfc.yaml | 1 +
drivers/pinctrl/renesas/Kconfig | 5 +
drivers/pinctrl/renesas/Makefile | 1 +
drivers/pinctrl/renesas/core.c | 6 +
drivers/pinctrl/renesas/pfc-r8a779g0.c | 4316 +++++++++++++++++
drivers/pinctrl/renesas/sh_pfc.h | 9 +-
6 files changed, 4336 insertions(+), 2 deletions(-)
create mode 100644 drivers/pinctrl/renesas/pfc-r8a779g0.c
--
2.25.1
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v3 01/21] dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
@ 2022-06-14 5:58 ` Kuninori Morimoto
2022-06-17 12:30 ` Geert Uytterhoeven
2022-06-14 5:58 ` [PATCH v3 02/21] pinctrl: renesas: Add PORT_GP_CFG_13 macros Kuninori Morimoto
` (19 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:58 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Document Pin Function Controller (PFC) support for the Renesas
R-Car V4H (R8A779G0) SoC.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
index 2a57df75d832..4fc758fea7e6 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
@@ -45,6 +45,7 @@ properties:
- renesas,pfc-r8a77995 # R-Car D3
- renesas,pfc-r8a779a0 # R-Car V3U
- renesas,pfc-r8a779f0 # R-Car S4-8
+ - renesas,pfc-r8a779g0 # R-Car V4H
- renesas,pfc-sh73a0 # SH-Mobile AG5
reg:
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 02/21] pinctrl: renesas: Add PORT_GP_CFG_13 macros
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
2022-06-14 5:58 ` [PATCH v3 01/21] dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support Kuninori Morimoto
@ 2022-06-14 5:58 ` Kuninori Morimoto
2022-06-17 12:30 ` Geert Uytterhoeven
2022-06-14 5:58 ` [PATCH v3 04/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (18 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:58 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Add PORT_GP_CFG_13() and PORT_GP_13() helper macros,
to be used by the r8a779g0 subdriver.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/sh_pfc.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index 12bc279f5733..bd0ae9d7005a 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -492,9 +492,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
-#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
+#define PORT_GP_CFG_13(bank, fn, sfx, cfg) \
PORT_GP_CFG_12(bank, fn, sfx, cfg), \
- PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
+ PORT_GP_CFG_1(bank, 12, fn, sfx, cfg)
+#define PORT_GP_13(bank, fn, sfx) PORT_GP_CFG_13(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
+ PORT_GP_CFG_13(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 04/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
2022-06-14 5:58 ` [PATCH v3 01/21] dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support Kuninori Morimoto
2022-06-14 5:58 ` [PATCH v3 02/21] pinctrl: renesas: Add PORT_GP_CFG_13 macros Kuninori Morimoto
@ 2022-06-14 5:58 ` Kuninori Morimoto
2022-06-17 15:15 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 05/21] pinctrl: renesas: r8a779g0: remove not used NOGP definitions Kuninori Morimoto
` (17 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:58 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Phong Hoang <phong.hoang.wz@renesas.com>
This patch adds SCIF, I2C, EthernetAVB, HSCIF, MMC, QSPI,
MSIOF, PWM, CAN-FD, Ethernet-TSN, PCIe pins, groups, and functions
[Morimoto merged above patches into one, cleanup white space,
sort modules alphabetically, fixup comments]
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: CongDang <cong.dang.xn@renesas.com>
Signed-off-by: Kazuya Mizuguch <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 1620 +++++++++++++++++++++++-
1 file changed, 1619 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 5035d45c4202..d42470b54d50 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -1211,12 +1211,1630 @@ static const struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
+/* - AVB0 ------------------------------------------------ */
+static const unsigned int avb0_link_pins[] = {
+ /* AVB0_LINK */
+ RCAR_GP_PIN(7, 4),
+};
+static const unsigned int avb0_link_mux[] = {
+ AVB0_LINK_MARK,
+};
+static const unsigned int avb0_magic_pins[] = {
+ /* AVB0_MAGIC */
+ RCAR_GP_PIN(7, 10),
+};
+static const unsigned int avb0_magic_mux[] = {
+ AVB0_MAGIC_MARK,
+};
+static const unsigned int avb0_phy_int_pins[] = {
+ /* AVB0_PHY_INT */
+ RCAR_GP_PIN(7, 5),
+};
+static const unsigned int avb0_phy_int_mux[] = {
+ AVB0_PHY_INT_MARK,
+};
+static const unsigned int avb0_mdio_pins[] = {
+ /* AVB0_MDC, AVB0_MDIO */
+ RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
+};
+static const unsigned int avb0_mdio_mux[] = {
+ AVB0_MDC_MARK, AVB0_MDIO_MARK,
+};
+static const unsigned int avb0_rgmii_pins[] = {
+ /*
+ * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
+ * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3,
+ */
+ RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
+ RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
+ RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
+ RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
+ RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
+ RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
+};
+static const unsigned int avb0_rgmii_mux[] = {
+ AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
+ AVB0_TD0_MARK, AVB0_TD1_MARK,
+ AVB0_TD2_MARK, AVB0_TD3_MARK,
+ AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
+ AVB0_RD0_MARK, AVB0_RD1_MARK,
+ AVB0_RD2_MARK, AVB0_RD3_MARK,
+};
+static const unsigned int avb0_txcrefclk_pins[] = {
+ /* AVB0_TXCREFCLK */
+ RCAR_GP_PIN(7, 9),
+};
+static const unsigned int avb0_txcrefclk_mux[] = {
+ AVB0_TXCREFCLK_MARK,
+};
+static const unsigned int avb0_avtp_pps_pins[] = {
+ /* AVB0_AVTP_PPS */
+ RCAR_GP_PIN(7, 0),
+};
+static const unsigned int avb0_avtp_pps_mux[] = {
+ AVB0_AVTP_PPS_MARK,
+};
+static const unsigned int avb0_avtp_capture_pins[] = {
+ /* AVB0_AVTP_CAPTURE */
+ RCAR_GP_PIN(7, 1),
+};
+static const unsigned int avb0_avtp_capture_mux[] = {
+ AVB0_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb0_avtp_match_pins[] = {
+ /* AVB0_AVTP_MATCH */
+ RCAR_GP_PIN(7, 2),
+};
+static const unsigned int avb0_avtp_match_mux[] = {
+ AVB0_AVTP_MATCH_MARK,
+};
+
+/* - AVB1 ------------------------------------------------ */
+static const unsigned int avb1_link_pins[] = {
+ /* AVB1_LINK */
+ RCAR_GP_PIN(6, 4),
+};
+static const unsigned int avb1_link_mux[] = {
+ AVB1_LINK_MARK,
+};
+static const unsigned int avb1_magic_pins[] = {
+ /* AVB1_MAGIC */
+ RCAR_GP_PIN(6, 1),
+};
+static const unsigned int avb1_magic_mux[] = {
+ AVB1_MAGIC_MARK,
+};
+static const unsigned int avb1_phy_int_pins[] = {
+ /* AVB1_PHY_INT */
+ RCAR_GP_PIN(6, 3),
+};
+static const unsigned int avb1_phy_int_mux[] = {
+ AVB1_PHY_INT_MARK,
+};
+static const unsigned int avb1_mdio_pins[] = {
+ /* AVB1_MDC, AVB1_MDIO */
+ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
+};
+static const unsigned int avb1_mdio_mux[] = {
+ AVB1_MDC_MARK, AVB1_MDIO_MARK,
+};
+static const unsigned int avb1_rgmii_pins[] = {
+ /*
+ * AVB1_TX_CTL, AVB1_TXC, AVB1_TD0, AVB1_TD1, AVB1_TD2, AVB1_TD3,
+ * AVB1_RX_CTL, AVB1_RXC, AVB1_RD0, AVB1_RD1, AVB1_RD2, AVB1_RD3,
+ */
+ RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
+ RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
+ RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
+ RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
+ RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
+ RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
+};
+static const unsigned int avb1_rgmii_mux[] = {
+ AVB1_TX_CTL_MARK, AVB1_TXC_MARK,
+ AVB1_TD0_MARK, AVB1_TD1_MARK,
+ AVB1_TD2_MARK, AVB1_TD3_MARK,
+ AVB1_RX_CTL_MARK, AVB1_RXC_MARK,
+ AVB1_RD0_MARK, AVB1_RD1_MARK,
+ AVB1_RD2_MARK, AVB1_RD3_MARK,
+};
+static const unsigned int avb1_txcrefclk_pins[] = {
+ /* AVB1_TXCREFCLK */
+ RCAR_GP_PIN(6, 20),
+};
+static const unsigned int avb1_txcrefclk_mux[] = {
+ AVB1_TXCREFCLK_MARK,
+};
+static const unsigned int avb1_avtp_pps_pins[] = {
+ /* AVB1_AVTP_PPS */
+ RCAR_GP_PIN(6, 10),
+};
+static const unsigned int avb1_avtp_pps_mux[] = {
+ AVB1_AVTP_PPS_MARK,
+};
+static const unsigned int avb1_avtp_capture_pins[] = {
+ /* AVB1_AVTP_CAPTURE */
+ RCAR_GP_PIN(6, 11),
+};
+static const unsigned int avb1_avtp_capture_mux[] = {
+ AVB1_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb1_avtp_match_pins[] = {
+ /* AVB1_AVTP_MATCH */
+ RCAR_GP_PIN(6, 5),
+};
+static const unsigned int avb1_avtp_match_mux[] = {
+ AVB1_AVTP_MATCH_MARK,
+};
+
+/* - AVB2 ------------------------------------------------ */
+static const unsigned int avb2_link_pins[] = {
+ /* AVB2_LINK */
+ RCAR_GP_PIN(5, 3),
+};
+static const unsigned int avb2_link_mux[] = {
+ AVB2_LINK_MARK,
+};
+static const unsigned int avb2_magic_pins[] = {
+ /* AVB2_MAGIC */
+ RCAR_GP_PIN(5, 5),
+};
+static const unsigned int avb2_magic_mux[] = {
+ AVB2_MAGIC_MARK,
+};
+static const unsigned int avb2_phy_int_pins[] = {
+ /* AVB2_PHY_INT */
+ RCAR_GP_PIN(5, 4),
+};
+static const unsigned int avb2_phy_int_mux[] = {
+ AVB2_PHY_INT_MARK,
+};
+static const unsigned int avb2_mdio_pins[] = {
+ /* AVB2_MDC, AVB2_MDIO */
+ RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
+};
+static const unsigned int avb2_mdio_mux[] = {
+ AVB2_MDC_MARK, AVB2_MDIO_MARK,
+};
+static const unsigned int avb2_rgmii_pins[] = {
+ /*
+ * AVB2_TX_CTL, AVB2_TXC, AVB2_TD0, AVB2_TD1, AVB2_TD2, AVB2_TD3,
+ * AVB2_RX_CTL, AVB2_RXC, AVB2_RD0, AVB2_RD1, AVB2_RD2, AVB2_RD3,
+ */
+ RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
+ RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
+ RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
+ RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
+ RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
+ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
+};
+static const unsigned int avb2_rgmii_mux[] = {
+ AVB2_TX_CTL_MARK, AVB2_TXC_MARK,
+ AVB2_TD0_MARK, AVB2_TD1_MARK,
+ AVB2_TD2_MARK, AVB2_TD3_MARK,
+ AVB2_RX_CTL_MARK, AVB2_RXC_MARK,
+ AVB2_RD0_MARK, AVB2_RD1_MARK,
+ AVB2_RD2_MARK, AVB2_RD3_MARK,
+};
+static const unsigned int avb2_txcrefclk_pins[] = {
+ /* AVB2_TXCREFCLK */
+ RCAR_GP_PIN(5, 7),
+};
+static const unsigned int avb2_txcrefclk_mux[] = {
+ AVB2_TXCREFCLK_MARK,
+};
+static const unsigned int avb2_avtp_pps_pins[] = {
+ /* AVB2_AVTP_PPS */
+ RCAR_GP_PIN(5, 0),
+};
+static const unsigned int avb2_avtp_pps_mux[] = {
+ AVB2_AVTP_PPS_MARK,
+};
+static const unsigned int avb2_avtp_capture_pins[] = {
+ /* AVB2_AVTP_CAPTURE */
+ RCAR_GP_PIN(5, 1),
+};
+static const unsigned int avb2_avtp_capture_mux[] = {
+ AVB2_AVTP_CAPTURE_MARK,
+};
+static const unsigned int avb2_avtp_match_pins[] = {
+ /* AVB2_AVTP_MATCH */
+ RCAR_GP_PIN(5, 2),
+};
+static const unsigned int avb2_avtp_match_mux[] = {
+ AVB2_AVTP_MATCH_MARK,
+};
+
+/* - CANFD0 ----------------------------------------------------------------- */
+static const unsigned int canfd0_data_pins[] = {
+ /* CANFD0_TX, CANFD0_RX */
+ RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+};
+static const unsigned int canfd0_data_mux[] = {
+ CANFD0_TX_MARK, CANFD0_RX_MARK,
+};
+
+/* - CANFD1 ----------------------------------------------------------------- */
+static const unsigned int canfd1_data_pins[] = {
+ /* CANFD1_TX, CANFD1_RX */
+ RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
+};
+static const unsigned int canfd1_data_mux[] = {
+ CANFD1_TX_MARK, CANFD1_RX_MARK,
+};
+
+/* - CANFD2 ----------------------------------------------------------------- */
+static const unsigned int canfd2_data_pins[] = {
+ /* CANFD2_TX, CANFD2_RX */
+ RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int canfd2_data_mux[] = {
+ CANFD2_TX_MARK, CANFD2_RX_MARK,
+};
+
+/* - CANFD3 ----------------------------------------------------------------- */
+static const unsigned int canfd3_data_pins[] = {
+ /* CANFD3_TX, CANFD3_RX */
+ RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
+};
+static const unsigned int canfd3_data_mux[] = {
+ CANFD3_TX_MARK, CANFD3_RX_MARK,
+};
+
+/* - CANFD4 ----------------------------------------------------------------- */
+static const unsigned int canfd4_data_pins[] = {
+ /* CANFD4_TX, CANFD4_RX */
+ RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
+};
+static const unsigned int canfd4_data_mux[] = {
+ CANFD4_TX_MARK, CANFD4_RX_MARK,
+};
+
+/* - CANFD5 ----------------------------------------------------------------- */
+static const unsigned int canfd5_data_pins[] = {
+ /* CANFD5_TX, CANFD5_RX */
+ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int canfd5_data_mux[] = {
+ CANFD5_TX_MARK, CANFD5_RX_MARK,
+};
+
+/* - CANFD6 ----------------------------------------------------------------- */
+static const unsigned int canfd6_data_pins[] = {
+ /* CANFD6_TX, CANFD6_RX */
+ RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
+};
+static const unsigned int canfd6_data_mux[] = {
+ CANFD6_TX_MARK, CANFD6_RX_MARK,
+};
+
+/* - CANFD7 ----------------------------------------------------------------- */
+static const unsigned int canfd7_data_pins[] = {
+ /* CANFD7_TX, CANFD7_RX */
+ RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
+};
+static const unsigned int canfd7_data_mux[] = {
+ CANFD7_TX_MARK, CANFD7_RX_MARK,
+};
+
+/* - CANFD Clock ------------------------------------------------------------ */
+static const unsigned int can_clk_pins[] = {
+ /* CAN_CLK */
+ RCAR_GP_PIN(2, 9),
+};
+static const unsigned int can_clk_mux[] = {
+ CAN_CLK_MARK,
+};
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+ /* HRX0, HTX0 */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
+};
+static const unsigned int hscif0_data_mux[] = {
+ HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+ /* HSCK0 */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int hscif0_clk_mux[] = {
+ HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+ /* HRTS0#, HCTS0# */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+ HRTS0_N_MARK, HCTS0_N_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+ /* HRX1, HTX1 */
+ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
+};
+static const unsigned int hscif1_data_mux[] = {
+ HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+ /* HSCK1 */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int hscif1_clk_mux[] = {
+ HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+ /* HRTS1#, HCTS1# */
+ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+ HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+ /* HRX2, HTX2 */
+ RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
+};
+static const unsigned int hscif2_data_mux[] = {
+ HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+ /* HSCK2 */
+ RCAR_GP_PIN(8, 13),
+};
+static const unsigned int hscif2_clk_mux[] = {
+ HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+ /* HRTS2#, HCTS2# */
+ RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+ HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+ /* HRX3, HTX3 */
+ RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
+};
+static const unsigned int hscif3_data_mux[] = {
+ HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+ /* HSCK3 */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int hscif3_clk_mux[] = {
+ HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+ /* HRTS3#, HCTS3# */
+ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+ HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+ /* SDA0, SCL0 */
+ RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
+};
+static const unsigned int i2c0_mux[] = {
+ SDA0_MARK, SCL0_MARK,
+};
+
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+ /* SDA1, SCL1 */
+ RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
+};
+static const unsigned int i2c1_mux[] = {
+ SDA1_MARK, SCL1_MARK,
+};
+
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+ /* SDA2, SCL2 */
+ RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
+};
+static const unsigned int i2c2_mux[] = {
+ SDA2_MARK, SCL2_MARK,
+};
+
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+ /* SDA3, SCL3 */
+ RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
+};
+static const unsigned int i2c3_mux[] = {
+ SDA3_MARK, SCL3_MARK,
+};
+
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+ /* SDA4, SCL4 */
+ RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
+};
+static const unsigned int i2c4_mux[] = {
+ SDA4_MARK, SCL4_MARK,
+};
+
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+ /* SDA5, SCL5 */
+ RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
+};
+static const unsigned int i2c5_mux[] = {
+ SDA5_MARK, SCL5_MARK,
+};
+
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data_pins[] = {
+ /* MMC_SD_D[0:3], MMC_D[4:7] */
+ RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
+ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
+ RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
+ RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int mmc_data_mux[] = {
+ MMC_SD_D0_MARK, MMC_SD_D1_MARK,
+ MMC_SD_D2_MARK, MMC_SD_D3_MARK,
+ MMC_D4_MARK, MMC_D5_MARK,
+ MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+ /* MMC_SD_CLK, MMC_SD_CMD */
+ RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+ MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+ /* SD_CD */
+ RCAR_GP_PIN(3, 11),
+};
+static const unsigned int mmc_cd_mux[] = {
+ SD_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+ /* SD_WP */
+ RCAR_GP_PIN(3, 12),
+};
+static const unsigned int mmc_wp_mux[] = {
+ SD_WP_MARK,
+};
+static const unsigned int mmc_ds_pins[] = {
+ /* MMC_DS */
+ RCAR_GP_PIN(3, 4),
+};
+static const unsigned int mmc_ds_mux[] = {
+ MMC_DS_MARK,
+};
+
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+ /* MSIOF0_SCK */
+ RCAR_GP_PIN(1, 10),
+};
+static const unsigned int msiof0_clk_mux[] = {
+ MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+ /* MSIOF0_SYNC */
+ RCAR_GP_PIN(1, 8),
+};
+static const unsigned int msiof0_sync_mux[] = {
+ MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+ /* MSIOF0_SS1 */
+ RCAR_GP_PIN(1, 7),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+ MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+ /* MSIOF0_SS2 */
+ RCAR_GP_PIN(1, 6),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+ MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+ /* MSIOF0_TXD */
+ RCAR_GP_PIN(1, 9),
+};
+static const unsigned int msiof0_txd_mux[] = {
+ MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+ /* MSIOF0_RXD */
+ RCAR_GP_PIN(1, 11),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+ MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+ /* MSIOF1_SCK */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int msiof1_clk_mux[] = {
+ MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+ /* MSIOF1_SYNC */
+ RCAR_GP_PIN(1, 2),
+};
+static const unsigned int msiof1_sync_mux[] = {
+ MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+ /* MSIOF1_SS1 */
+ RCAR_GP_PIN(1, 1),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+ MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+ /* MSIOF1_SS2 */
+ RCAR_GP_PIN(1, 0),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+ MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+ /* MSIOF1_TXD */
+ RCAR_GP_PIN(1, 4),
+};
+static const unsigned int msiof1_txd_mux[] = {
+ MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+ /* MSIOF1_RXD */
+ RCAR_GP_PIN(1, 5),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+ MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+ /* MSIOF2_SCK */
+ RCAR_GP_PIN(0, 17),
+};
+static const unsigned int msiof2_clk_mux[] = {
+ MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+ /* MSIOF2_SYNC */
+ RCAR_GP_PIN(0, 15),
+};
+static const unsigned int msiof2_sync_mux[] = {
+ MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+ /* MSIOF2_SS1 */
+ RCAR_GP_PIN(0, 14),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+ MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+ /* MSIOF2_SS2 */
+ RCAR_GP_PIN(0, 13),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+ MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+ /* MSIOF2_TXD */
+ RCAR_GP_PIN(0, 16),
+};
+static const unsigned int msiof2_txd_mux[] = {
+ MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+ /* MSIOF2_RXD */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+ MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+ /* MSIOF3_SCK */
+ RCAR_GP_PIN(0, 3),
+};
+static const unsigned int msiof3_clk_mux[] = {
+ MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+ /* MSIOF3_SYNC */
+ RCAR_GP_PIN(0, 6),
+};
+static const unsigned int msiof3_sync_mux[] = {
+ MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+ /* MSIOF3_SS1 */
+ RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+ MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+ /* MSIOF3_SS2 */
+ RCAR_GP_PIN(0, 2),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+ MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+ /* MSIOF3_TXD */
+ RCAR_GP_PIN(0, 4),
+};
+static const unsigned int msiof3_txd_mux[] = {
+ MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+ /* MSIOF3_RXD */
+ RCAR_GP_PIN(0, 5),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+ MSIOF3_RXD_MARK,
+};
+
+/* - MSIOF4 ----------------------------------------------------------------- */
+static const unsigned int msiof4_clk_pins[] = {
+ /* MSIOF4_SCK */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int msiof4_clk_mux[] = {
+ MSIOF4_SCK_MARK,
+};
+static const unsigned int msiof4_sync_pins[] = {
+ /* MSIOF4_SYNC */
+ RCAR_GP_PIN(1, 28),
+};
+static const unsigned int msiof4_sync_mux[] = {
+ MSIOF4_SYNC_MARK,
+};
+static const unsigned int msiof4_ss1_pins[] = {
+ /* MSIOF4_SS1 */
+ RCAR_GP_PIN(1, 23),
+};
+static const unsigned int msiof4_ss1_mux[] = {
+ MSIOF4_SS1_MARK,
+};
+static const unsigned int msiof4_ss2_pins[] = {
+ /* MSIOF4_SS2 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int msiof4_ss2_mux[] = {
+ MSIOF4_SS2_MARK,
+};
+static const unsigned int msiof4_txd_pins[] = {
+ /* MSIOF4_TXD */
+ RCAR_GP_PIN(1, 26),
+};
+static const unsigned int msiof4_txd_mux[] = {
+ MSIOF4_TXD_MARK,
+};
+static const unsigned int msiof4_rxd_pins[] = {
+ /* MSIOF4_RXD */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int msiof4_rxd_mux[] = {
+ MSIOF4_RXD_MARK,
+};
+
+/* - MSIOF5 ----------------------------------------------------------------- */
+static const unsigned int msiof5_clk_pins[] = {
+ /* MSIOF5_SCK */
+ RCAR_GP_PIN(0, 11),
+};
+static const unsigned int msiof5_clk_mux[] = {
+ MSIOF5_SCK_MARK,
+};
+static const unsigned int msiof5_sync_pins[] = {
+ /* MSIOF5_SYNC */
+ RCAR_GP_PIN(0, 9),
+};
+static const unsigned int msiof5_sync_mux[] = {
+ MSIOF5_SYNC_MARK,
+};
+static const unsigned int msiof5_ss1_pins[] = {
+ /* MSIOF5_SS1 */
+ RCAR_GP_PIN(0, 8),
+};
+static const unsigned int msiof5_ss1_mux[] = {
+ MSIOF5_SS1_MARK,
+};
+static const unsigned int msiof5_ss2_pins[] = {
+ /* MSIOF5_SS2 */
+ RCAR_GP_PIN(0, 7),
+};
+static const unsigned int msiof5_ss2_mux[] = {
+ MSIOF5_SS2_MARK,
+};
+static const unsigned int msiof5_txd_pins[] = {
+ /* MSIOF5_TXD */
+ RCAR_GP_PIN(0, 10),
+};
+static const unsigned int msiof5_txd_mux[] = {
+ MSIOF5_TXD_MARK,
+};
+static const unsigned int msiof5_rxd_pins[] = {
+ /* MSIOF5_RXD */
+ RCAR_GP_PIN(0, 12),
+};
+static const unsigned int msiof5_rxd_mux[] = {
+ MSIOF5_RXD_MARK,
+};
+
+/* - PCIE ------------------------------------------------------------------- */
+static const unsigned int pcie0_clkreq_n_pins[] = {
+ /* PCIE0_CLKREQ# */
+ RCAR_GP_PIN(4, 21),
+};
+
+static const unsigned int pcie0_clkreq_n_mux[] = {
+ PCIE0_CLKREQ_N_MARK,
+};
+
+static const unsigned int pcie1_clkreq_n_pins[] = {
+ /* PCIE1_CLKREQ# */
+ RCAR_GP_PIN(4, 22),
+};
+
+static const unsigned int pcie1_clkreq_n_mux[] = {
+ PCIE1_CLKREQ_N_MARK,
+};
+
+/* - PWM0 ------------------------------------------------------------------- */
+static const unsigned int pwm0_pins[] = {
+ /* PWM0 */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int pwm0_mux[] = {
+ PWM0_MARK,
+};
+
+/* - PWM1 ------------------------------------------------------------------- */
+static const unsigned int pwm1_pins[] = {
+ /* PWM1 */
+ RCAR_GP_PIN(2, 13),
+};
+static const unsigned int pwm1_mux[] = {
+ PWM1_MARK,
+};
+
+/* - PWM2 ------------------------------------------------------------------- */
+static const unsigned int pwm2_pins[] = {
+ /* PWM2 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int pwm2_mux[] = {
+ PWM2_MARK,
+};
+
+/* - PWM3 ------------------------------------------------------------------- */
+static const unsigned int pwm3_pins[] = {
+ /* PWM3 */
+ RCAR_GP_PIN(1, 22),
+};
+static const unsigned int pwm3_mux[] = {
+ PWM3_MARK,
+};
+
+/* - PWM4 ------------------------------------------------------------------- */
+static const unsigned int pwm4_pins[] = {
+ /* PWM4 */
+ RCAR_GP_PIN(2, 16),
+};
+static const unsigned int pwm4_mux[] = {
+ PWM4_MARK,
+};
+
+/* - PWM5 ------------------------------------------------------------------- */
+static const unsigned int pwm5_pins[] = {
+ /* PWM5 */
+ RCAR_GP_PIN(2, 17),
+};
+static const unsigned int pwm5_mux[] = {
+ PWM5_MARK,
+};
+
+/* - PWM6 ------------------------------------------------------------------- */
+static const unsigned int pwm6_pins[] = {
+ /* PWM6 */
+ RCAR_GP_PIN(2, 18),
+};
+static const unsigned int pwm6_mux[] = {
+ PWM6_MARK,
+};
+
+/* - PWM7 ------------------------------------------------------------------- */
+static const unsigned int pwm7_pins[] = {
+ /* PWM7 */
+ RCAR_GP_PIN(2, 19),
+};
+static const unsigned int pwm7_mux[] = {
+ PWM7_MARK,
+};
+
+/* - PWM8 ------------------------------------------------------------------- */
+static const unsigned int pwm8_pins[] = {
+ /* PWM8 */
+ RCAR_GP_PIN(1, 13),
+};
+static const unsigned int pwm8_mux[] = {
+ PWM8_MARK,
+};
+
+/* - PWM9 ------------------------------------------------------------------- */
+static const unsigned int pwm9_pins[] = {
+ /* PWM9 */
+ RCAR_GP_PIN(1, 14),
+};
+static const unsigned int pwm9_mux[] = {
+ PWM9_MARK,
+};
+
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+ QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
+ RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int qspi0_data_mux[] = {
+ QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+ QSPI0_IO2_MARK, QSPI0_IO3_MARK
+};
+
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+ /* SPCLK, SSL */
+ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+ QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data_pins[] = {
+ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
+ RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
+ RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
+};
+static const unsigned int qspi1_data_mux[] = {
+ QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+ QSPI1_IO2_MARK, QSPI1_IO3_MARK
+};
+
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RX0, TX0 */
+ RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK0 */
+ RCAR_GP_PIN(1, 15),
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS0#, CTS0# */
+ RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_N_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+ /* RX1, TX1 */
+ RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
+};
+static const unsigned int scif1_data_mux[] = {
+ RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK1 */
+ RCAR_GP_PIN(0, 18),
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS1_N, CTS1_N */
+ RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_N_MARK, CTS1_N_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RX3, TX3 */
+ RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK3 */
+ RCAR_GP_PIN(1, 4),
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+ /* RTS3_N, CTS3_N */
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+ RTS3_N_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RX4, TX4 */
+ RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+ /* SCK4 */
+ RCAR_GP_PIN(8, 8),
+};
+static const unsigned int scif4_clk_mux[] = {
+ SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+ /* RTS4#, CTS4# */
+ RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+ RTS4_N_MARK, CTS4_N_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+ /* SCIF_CLK */
+ RCAR_GP_PIN(1, 17),
+};
+static const unsigned int scif_clk_mux[] = {
+ SCIF_CLK_MARK,
+};
+
+/* - TPU ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_pins[] = {
+ /* TPU0TO0 */
+ RCAR_GP_PIN(2, 8),
+};
+static const unsigned int tpu_to0_mux[] = {
+ TPU0TO0_MARK,
+};
+static const unsigned int tpu_to1_pins[] = {
+ /* TPU0TO1 */
+ RCAR_GP_PIN(2, 7),
+};
+static const unsigned int tpu_to1_mux[] = {
+ TPU0TO1_MARK,
+};
+static const unsigned int tpu_to2_pins[] = {
+ /* TPU0TO2 */
+ RCAR_GP_PIN(2, 12),
+};
+static const unsigned int tpu_to2_mux[] = {
+ TPU0TO2_MARK,
+};
+static const unsigned int tpu_to3_pins[] = {
+ /* TPU0TO3 */
+ RCAR_GP_PIN(2, 13),
+};
+static const unsigned int tpu_to3_mux[] = {
+ TPU0TO3_MARK,
+};
+
+/* - TSN0 ------------------------------------------------ */
+static const unsigned int tsn0_link_pins[] = {
+ /* TSN0_LINK */
+ RCAR_GP_PIN(4, 4),
+};
+static const unsigned int tsn0_link_mux[] = {
+ TSN0_LINK_MARK,
+};
+static const unsigned int tsn0_phy_int_pins[] = {
+ /* TSN0_PHY_INT */
+ RCAR_GP_PIN(4, 3),
+};
+static const unsigned int tsn0_phy_int_mux[] = {
+ TSN0_PHY_INT_MARK,
+};
+static const unsigned int tsn0_mdio_pins[] = {
+ /* TSN0_MDC, TSN0_MDIO */
+ RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
+};
+static const unsigned int tsn0_mdio_mux[] = {
+ TSN0_MDC_MARK, TSN0_MDIO_MARK,
+};
+static const unsigned int tsn0_rgmii_pins[] = {
+ /*
+ * TSN0_TX_CTL, TSN0_TXC, TSN0_TD0, TSN0_TD1, TSN0_TD2, TSN0_TD3,
+ * TSN0_RX_CTL, TSN0_RXC, TSN0_RD0, TSN0_RD1, TSN0_RD2, TSN0_RD3,
+ */
+ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
+ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
+ RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
+ RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
+ RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
+ RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int tsn0_rgmii_mux[] = {
+ TSN0_TX_CTL_MARK, TSN0_TXC_MARK,
+ TSN0_TD0_MARK, TSN0_TD1_MARK,
+ TSN0_TD2_MARK, TSN0_TD3_MARK,
+ TSN0_RX_CTL_MARK, TSN0_RXC_MARK,
+ TSN0_RD0_MARK, TSN0_RD1_MARK,
+ TSN0_RD2_MARK, TSN0_RD3_MARK,
+};
+static const unsigned int tsn0_txcrefclk_pins[] = {
+ /* TSN0_TXCREFCLK */
+ RCAR_GP_PIN(4, 20),
+};
+static const unsigned int tsn0_txcrefclk_mux[] = {
+ TSN0_TXCREFCLK_MARK,
+};
+static const unsigned int tsn0_avtp_pps_pins[] = {
+ /* TSN0_AVTP_PPS0, TSN0_AVTP_PPS1 */
+ RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int tsn0_avtp_pps_mux[] = {
+ TSN0_AVTP_PPS0_MARK, TSN0_AVTP_PPS1_MARK,
+};
+static const unsigned int tsn0_avtp_capture_pins[] = {
+ /* TSN0_AVTP_CAPTURE */
+ RCAR_GP_PIN(4, 6),
+};
+static const unsigned int tsn0_avtp_capture_mux[] = {
+ TSN0_AVTP_CAPTURE_MARK,
+};
+static const unsigned int tsn0_avtp_match_pins[] = {
+ /* TSN0_AVTP_MATCH */
+ RCAR_GP_PIN(4, 5),
+};
+static const unsigned int tsn0_avtp_match_mux[] = {
+ TSN0_AVTP_MATCH_MARK,
+};
+
static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(avb0_link),
+ SH_PFC_PIN_GROUP(avb0_magic),
+ SH_PFC_PIN_GROUP(avb0_phy_int),
+ SH_PFC_PIN_GROUP(avb0_mdio),
+ SH_PFC_PIN_GROUP(avb0_rgmii),
+ SH_PFC_PIN_GROUP(avb0_txcrefclk),
+ SH_PFC_PIN_GROUP(avb0_avtp_pps),
+ SH_PFC_PIN_GROUP(avb0_avtp_capture),
+ SH_PFC_PIN_GROUP(avb0_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb1_link),
+ SH_PFC_PIN_GROUP(avb1_magic),
+ SH_PFC_PIN_GROUP(avb1_phy_int),
+ SH_PFC_PIN_GROUP(avb1_mdio),
+ SH_PFC_PIN_GROUP(avb1_rgmii),
+ SH_PFC_PIN_GROUP(avb1_txcrefclk),
+ SH_PFC_PIN_GROUP(avb1_avtp_pps),
+ SH_PFC_PIN_GROUP(avb1_avtp_capture),
+ SH_PFC_PIN_GROUP(avb1_avtp_match),
+
+ SH_PFC_PIN_GROUP(avb2_link),
+ SH_PFC_PIN_GROUP(avb2_magic),
+ SH_PFC_PIN_GROUP(avb2_phy_int),
+ SH_PFC_PIN_GROUP(avb2_mdio),
+ SH_PFC_PIN_GROUP(avb2_rgmii),
+ SH_PFC_PIN_GROUP(avb2_txcrefclk),
+ SH_PFC_PIN_GROUP(avb2_avtp_pps),
+ SH_PFC_PIN_GROUP(avb2_avtp_capture),
+ SH_PFC_PIN_GROUP(avb2_avtp_match),
+
+ SH_PFC_PIN_GROUP(canfd0_data),
+ SH_PFC_PIN_GROUP(canfd1_data),
+ SH_PFC_PIN_GROUP(canfd2_data),
+ SH_PFC_PIN_GROUP(canfd3_data),
+ SH_PFC_PIN_GROUP(canfd4_data),
+ SH_PFC_PIN_GROUP(canfd5_data),
+ SH_PFC_PIN_GROUP(canfd6_data),
+ SH_PFC_PIN_GROUP(canfd7_data),
+ SH_PFC_PIN_GROUP(can_clk),
+
+ SH_PFC_PIN_GROUP(hscif0_data),
+ SH_PFC_PIN_GROUP(hscif0_clk),
+ SH_PFC_PIN_GROUP(hscif0_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_data),
+ SH_PFC_PIN_GROUP(hscif1_clk),
+ SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif2_data),
+ SH_PFC_PIN_GROUP(hscif2_clk),
+ SH_PFC_PIN_GROUP(hscif2_ctrl),
+ SH_PFC_PIN_GROUP(hscif3_data),
+ SH_PFC_PIN_GROUP(hscif3_clk),
+ SH_PFC_PIN_GROUP(hscif3_ctrl),
+
+ SH_PFC_PIN_GROUP(i2c0),
+ SH_PFC_PIN_GROUP(i2c1),
+ SH_PFC_PIN_GROUP(i2c2),
+ SH_PFC_PIN_GROUP(i2c3),
+ SH_PFC_PIN_GROUP(i2c4),
+ SH_PFC_PIN_GROUP(i2c5),
+
+ BUS_DATA_PIN_GROUP(mmc_data, 1),
+ BUS_DATA_PIN_GROUP(mmc_data, 4),
+ BUS_DATA_PIN_GROUP(mmc_data, 8),
+ SH_PFC_PIN_GROUP(mmc_ctrl),
+ SH_PFC_PIN_GROUP(mmc_cd),
+ SH_PFC_PIN_GROUP(mmc_wp),
+ SH_PFC_PIN_GROUP(mmc_ds),
+
+ SH_PFC_PIN_GROUP(msiof0_clk),
+ SH_PFC_PIN_GROUP(msiof0_sync),
+ SH_PFC_PIN_GROUP(msiof0_ss1),
+ SH_PFC_PIN_GROUP(msiof0_ss2),
+ SH_PFC_PIN_GROUP(msiof0_txd),
+ SH_PFC_PIN_GROUP(msiof0_rxd),
+
+ SH_PFC_PIN_GROUP(msiof1_clk),
+ SH_PFC_PIN_GROUP(msiof1_sync),
+ SH_PFC_PIN_GROUP(msiof1_ss1),
+ SH_PFC_PIN_GROUP(msiof1_ss2),
+ SH_PFC_PIN_GROUP(msiof1_txd),
+ SH_PFC_PIN_GROUP(msiof1_rxd),
+
+ SH_PFC_PIN_GROUP(msiof2_clk),
+ SH_PFC_PIN_GROUP(msiof2_sync),
+ SH_PFC_PIN_GROUP(msiof2_ss1),
+ SH_PFC_PIN_GROUP(msiof2_ss2),
+ SH_PFC_PIN_GROUP(msiof2_txd),
+ SH_PFC_PIN_GROUP(msiof2_rxd),
+
+ SH_PFC_PIN_GROUP(msiof3_clk),
+ SH_PFC_PIN_GROUP(msiof3_sync),
+ SH_PFC_PIN_GROUP(msiof3_ss1),
+ SH_PFC_PIN_GROUP(msiof3_ss2),
+ SH_PFC_PIN_GROUP(msiof3_txd),
+ SH_PFC_PIN_GROUP(msiof3_rxd),
+
+ SH_PFC_PIN_GROUP(msiof4_clk),
+ SH_PFC_PIN_GROUP(msiof4_sync),
+ SH_PFC_PIN_GROUP(msiof4_ss1),
+ SH_PFC_PIN_GROUP(msiof4_ss2),
+ SH_PFC_PIN_GROUP(msiof4_txd),
+ SH_PFC_PIN_GROUP(msiof4_rxd),
+
+ SH_PFC_PIN_GROUP(msiof5_clk),
+ SH_PFC_PIN_GROUP(msiof5_sync),
+ SH_PFC_PIN_GROUP(msiof5_ss1),
+ SH_PFC_PIN_GROUP(msiof5_ss2),
+ SH_PFC_PIN_GROUP(msiof5_txd),
+ SH_PFC_PIN_GROUP(msiof5_rxd),
+
+ SH_PFC_PIN_GROUP(pcie0_clkreq_n),
+ SH_PFC_PIN_GROUP(pcie1_clkreq_n),
+
+ SH_PFC_PIN_GROUP(pwm0),
+ SH_PFC_PIN_GROUP(pwm1),
+ SH_PFC_PIN_GROUP(pwm2),
+ SH_PFC_PIN_GROUP(pwm3),
+ SH_PFC_PIN_GROUP(pwm4),
+ SH_PFC_PIN_GROUP(pwm5),
+ SH_PFC_PIN_GROUP(pwm6),
+ SH_PFC_PIN_GROUP(pwm7),
+ SH_PFC_PIN_GROUP(pwm8),
+ SH_PFC_PIN_GROUP(pwm9),
+
+ SH_PFC_PIN_GROUP(qspi0_ctrl),
+ BUS_DATA_PIN_GROUP(qspi0_data, 2),
+ BUS_DATA_PIN_GROUP(qspi0_data, 4),
+ SH_PFC_PIN_GROUP(qspi1_ctrl),
+ BUS_DATA_PIN_GROUP(qspi1_data, 2),
+ BUS_DATA_PIN_GROUP(qspi1_data, 4),
+
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_clk),
+ SH_PFC_PIN_GROUP(scif4_ctrl),
+ SH_PFC_PIN_GROUP(scif_clk),
+
+ SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to3),
+
+ SH_PFC_PIN_GROUP(tsn0_link),
+ SH_PFC_PIN_GROUP(tsn0_phy_int),
+ SH_PFC_PIN_GROUP(tsn0_mdio),
+ SH_PFC_PIN_GROUP(tsn0_rgmii),
+ SH_PFC_PIN_GROUP(tsn0_txcrefclk),
+ SH_PFC_PIN_GROUP(tsn0_avtp_pps),
+ SH_PFC_PIN_GROUP(tsn0_avtp_capture),
+ SH_PFC_PIN_GROUP(tsn0_avtp_match),
+};
+static const char * const avb0_groups[] = {
+ "avb0_link",
+ "avb0_magic",
+ "avb0_phy_int",
+ "avb0_mdio",
+ "avb0_rgmii",
+ "avb0_txcrefclk",
+ "avb0_avtp_pps",
+ "avb0_avtp_capture",
+ "avb0_avtp_match",
};
-static const struct sh_pfc_function pinmux_functions[] = {
+static const char * const avb1_groups[] = {
+ "avb1_link",
+ "avb1_magic",
+ "avb1_phy_int",
+ "avb1_mdio",
+ "avb1_rgmii",
+ "avb1_txcrefclk",
+ "avb1_avtp_pps",
+ "avb1_avtp_capture",
+ "avb1_avtp_match",
+};
+
+static const char * const avb2_groups[] = {
+ "avb2_link",
+ "avb2_magic",
+ "avb2_phy_int",
+ "avb2_mdio",
+ "avb2_rgmii",
+ "avb2_txcrefclk",
+ "avb2_avtp_pps",
+ "avb2_avtp_capture",
+ "avb2_avtp_match",
+};
+
+static const char * const canfd0_groups[] = {
+ "canfd0_data",
+};
+static const char * const canfd1_groups[] = {
+ "canfd1_data",
+};
+
+static const char * const canfd2_groups[] = {
+ "canfd2_data",
+};
+
+static const char * const canfd3_groups[] = {
+ "canfd3_data",
+};
+
+static const char * const canfd4_groups[] = {
+ "canfd4_data",
+};
+
+static const char * const canfd5_groups[] = {
+ "canfd5_data",
+};
+
+static const char * const canfd6_groups[] = {
+ "canfd6_data",
+};
+
+static const char * const canfd7_groups[] = {
+ "canfd7_data",
+};
+
+static const char * const can_clk_groups[] = {
+ "can_clk",
+};
+
+static const char * const hscif0_groups[] = {
+ "hscif0_data",
+ "hscif0_clk",
+ "hscif0_ctrl",
+};
+
+static const char * const hscif1_groups[] = {
+ "hscif1_data",
+ "hscif1_clk",
+ "hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+ "hscif2_data",
+ "hscif2_clk",
+ "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+ "hscif3_data",
+ "hscif3_clk",
+ "hscif3_ctrl",
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5",
+};
+
+static const char * const mmc_groups[] = {
+ "mmc_data1",
+ "mmc_data4",
+ "mmc_data8",
+ "mmc_ctrl",
+ "mmc_cd",
+ "mmc_wp",
+ "mmc_ds",
+};
+
+static const char * const msiof0_groups[] = {
+ "msiof0_clk",
+ "msiof0_sync",
+ "msiof0_ss1",
+ "msiof0_ss2",
+ "msiof0_txd",
+ "msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+ "msiof1_clk",
+ "msiof1_sync",
+ "msiof1_ss1",
+ "msiof1_ss2",
+ "msiof1_txd",
+ "msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+ "msiof2_clk",
+ "msiof2_sync",
+ "msiof2_ss1",
+ "msiof2_ss2",
+ "msiof2_txd",
+ "msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+ "msiof3_clk",
+ "msiof3_sync",
+ "msiof3_ss1",
+ "msiof3_ss2",
+ "msiof3_txd",
+ "msiof3_rxd",
+};
+
+static const char * const msiof4_groups[] = {
+ "msiof4_clk",
+ "msiof4_sync",
+ "msiof4_ss1",
+ "msiof4_ss2",
+ "msiof4_txd",
+ "msiof4_rxd",
+};
+
+static const char * const msiof5_groups[] = {
+ "msiof5_clk",
+ "msiof5_sync",
+ "msiof5_ss1",
+ "msiof5_ss2",
+ "msiof5_txd",
+ "msiof5_rxd",
+};
+
+static const char * const pcie_groups[] = {
+ "pcie0_clkreq_n",
+ "pcie1_clkreq_n",
+};
+
+static const char * const pwm0_groups[] = {
+ "pwm0",
+};
+
+static const char * const pwm1_groups[] = {
+ "pwm1",
+};
+
+static const char * const pwm2_groups[] = {
+ "pwm2",
+};
+
+static const char * const pwm3_groups[] = {
+ "pwm3",
+};
+
+static const char * const pwm4_groups[] = {
+ "pwm4",
+};
+
+static const char * const pwm5_groups[] = {
+ "pwm5",
+};
+
+static const char * const pwm6_groups[] = {
+ "pwm6",
+};
+
+static const char * const pwm7_groups[] = {
+ "pwm7",
+};
+
+static const char * const pwm8_groups[] = {
+ "pwm8",
+};
+
+static const char * const pwm9_groups[] = {
+ "pwm9",
+};
+
+static const char * const qspi0_groups[] = {
+ "qspi0_ctrl",
+ "qspi0_data2",
+ "qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+ "qspi1_ctrl",
+ "qspi1_data2",
+ "qspi1_data4",
+};
+
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_clk",
+ "scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data",
+ "scif1_clk",
+ "scif1_ctrl",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_ctrl",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_clk",
+ "scif4_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+ "scif_clk",
+};
+
+static const char * const tpu_groups[] = {
+ "tpu_to0",
+ "tpu_to1",
+ "tpu_to2",
+ "tpu_to3",
+};
+
+static const char * const tsn0_groups[] = {
+ "tsn0_link",
+ "tsn0_phy_int",
+ "tsn0_mdio",
+ "tsn0_rgmii",
+ "tsn0_txcrefclk",
+ "tsn0_avtp_pps",
+ "tsn0_avtp_capture",
+ "tsn0_avtp_match",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(avb0),
+ SH_PFC_FUNCTION(avb1),
+ SH_PFC_FUNCTION(avb2),
+
+ SH_PFC_FUNCTION(canfd0),
+ SH_PFC_FUNCTION(canfd1),
+ SH_PFC_FUNCTION(canfd2),
+ SH_PFC_FUNCTION(canfd3),
+ SH_PFC_FUNCTION(canfd4),
+ SH_PFC_FUNCTION(canfd5),
+ SH_PFC_FUNCTION(canfd6),
+ SH_PFC_FUNCTION(canfd7),
+ SH_PFC_FUNCTION(can_clk),
+
+ SH_PFC_FUNCTION(hscif0),
+ SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif2),
+ SH_PFC_FUNCTION(hscif3),
+
+ SH_PFC_FUNCTION(i2c0),
+ SH_PFC_FUNCTION(i2c1),
+ SH_PFC_FUNCTION(i2c2),
+ SH_PFC_FUNCTION(i2c3),
+ SH_PFC_FUNCTION(i2c4),
+ SH_PFC_FUNCTION(i2c5),
+
+ SH_PFC_FUNCTION(mmc),
+
+ SH_PFC_FUNCTION(msiof0),
+ SH_PFC_FUNCTION(msiof1),
+ SH_PFC_FUNCTION(msiof2),
+ SH_PFC_FUNCTION(msiof3),
+ SH_PFC_FUNCTION(msiof4),
+ SH_PFC_FUNCTION(msiof5),
+
+ SH_PFC_FUNCTION(pcie),
+
+ SH_PFC_FUNCTION(pwm0),
+ SH_PFC_FUNCTION(pwm1),
+ SH_PFC_FUNCTION(pwm2),
+ SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm4),
+ SH_PFC_FUNCTION(pwm5),
+ SH_PFC_FUNCTION(pwm6),
+ SH_PFC_FUNCTION(pwm7),
+ SH_PFC_FUNCTION(pwm8),
+ SH_PFC_FUNCTION(pwm9),
+
+ SH_PFC_FUNCTION(qspi0),
+ SH_PFC_FUNCTION(qspi1),
+
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif_clk),
+
+ SH_PFC_FUNCTION(tpu),
+
+ SH_PFC_FUNCTION(tsn0),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 05/21] pinctrl: renesas: r8a779g0: remove not used NOGP definitions
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (2 preceding siblings ...)
2022-06-14 5:58 ` [PATCH v3 04/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
@ 2022-06-14 5:59 ` Kuninori Morimoto
2022-06-17 15:16 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 06/21] pinctrl: renesas: r8a779g0: remove not used IPxSRx definitions Kuninori Morimoto
` (16 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:59 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Current V4H PFC code has many NOGP definitions. But these are not used,
and it is different from original usage. This patch removes these.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index d42470b54d50..1716399350dc 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -43,22 +43,6 @@
PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
-#define CPU_ALL_NOGP(fn) \
- PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
- PIN_NOGP_CFG(PRESETOUT1_N, "PRESETOUT1#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
- PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
- PIN_NOGP_CFG(DCUTRST0_N, "DCUTRST0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
- PIN_NOGP_CFG(DCUTCK0, "DCUTCK0", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(DCUTMS0, "DCUTMS0", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(DCUTDI0, "DCUTDI0", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(DCUTRST1_N, "DCUTRST1#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
- PIN_NOGP_CFG(DCUTCK1, "DCUTCK1", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(DCUTMS1, "DCUTMS1", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(DCUTDI1, "DCUTDI1", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(EVTI_N, "EVTI#", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(MSYN_N, "MSYN#", fn, SH_PFC_PIN_CFG_PULL_UP)
-
/* GPSR0 */
#define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
#define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
@@ -1204,7 +1188,6 @@ static const u16 pinmux_data[] = {
*/
enum {
GP_ASSIGN_LAST(),
- NOGP_ALL(),
};
static const struct sh_pfc_pin pinmux_pins[] = {
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 06/21] pinctrl: renesas: r8a779g0: remove not used IPxSRx definitions
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (3 preceding siblings ...)
2022-06-14 5:59 ` [PATCH v3 05/21] pinctrl: renesas: r8a779g0: remove not used NOGP definitions Kuninori Morimoto
@ 2022-06-14 5:59 ` Kuninori Morimoto
2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 07/21] pinctrl: renesas: r8a779g0: remove not used MOD_SELx definitions Kuninori Morimoto
` (15 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:59 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Current V4H PFC code has many IPxSRx definitions with all 0.
But these have no meaning. This patch removes these.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 67 +++++++++-----------------
1 file changed, 22 insertions(+), 45 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 1716399350dc..d049bb71dfe8 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -286,11 +286,6 @@
#define IP2SR0_3_0 FM(MSIOF2_TXD) FM(HCTS1_N) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_7_4 FM(MSIOF2_SCK) FM(HRTS1_N) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR0_11_8 FM(MSIOF2_RXD) FM(HSCK1) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR0_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR1 */
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -329,9 +324,6 @@
#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_19_16 FM(HTX3) FM(TX3) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR2 */
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -359,10 +351,6 @@
#define IP2SR2_7_4 FM(CANFD4_RX) F_(0, 0) FM(PWM5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_11_8 FM(CANFD7_TX) F_(0, 0) FM(PWM6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR2_15_12 FM(CANFD7_RX) F_(0, 0) FM(PWM7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR2_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR3 */
/* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -402,8 +390,6 @@
#define IP3SR3_15_12 FM(RPC_RESET_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR3_19_16 FM(RPC_WP_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR3_23_20 FM(RPC_INT_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR6 */
/* IP0SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -432,9 +418,6 @@
#define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR6_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR7 */
/* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -463,9 +446,6 @@
#define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR7_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR8 */
/* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -485,9 +465,6 @@
#define IP1SR8_15_12 FM(SDA5) FM(SCIF_CLK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR8_19_16 F_(0, 0) FM(HCTS2_N) FM(TX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR8_23_20 F_(0, 0) FM(HSCK2) FM(RX4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-
#define PINMUX_GPSR \
GPSR3_29 \
@@ -526,29 +503,29 @@ GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0 GPSR8_0
FM(IP0SR0_3_0) IP0SR0_3_0 FM(IP1SR0_3_0) IP1SR0_3_0 FM(IP2SR0_3_0) IP2SR0_3_0 \
FM(IP0SR0_7_4) IP0SR0_7_4 FM(IP1SR0_7_4) IP1SR0_7_4 FM(IP2SR0_7_4) IP2SR0_7_4 \
FM(IP0SR0_11_8) IP0SR0_11_8 FM(IP1SR0_11_8) IP1SR0_11_8 FM(IP2SR0_11_8) IP2SR0_11_8 \
-FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 FM(IP2SR0_15_12) IP2SR0_15_12 \
-FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 FM(IP2SR0_19_16) IP2SR0_19_16 \
-FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 FM(IP2SR0_23_20) IP2SR0_23_20 \
-FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 FM(IP2SR0_27_24) IP2SR0_27_24 \
-FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 FM(IP2SR0_31_28) IP2SR0_31_28 \
+FM(IP0SR0_15_12) IP0SR0_15_12 FM(IP1SR0_15_12) IP1SR0_15_12 \
+FM(IP0SR0_19_16) IP0SR0_19_16 FM(IP1SR0_19_16) IP1SR0_19_16 \
+FM(IP0SR0_23_20) IP0SR0_23_20 FM(IP1SR0_23_20) IP1SR0_23_20 \
+FM(IP0SR0_27_24) IP0SR0_27_24 FM(IP1SR0_27_24) IP1SR0_27_24 \
+FM(IP0SR0_31_28) IP0SR0_31_28 FM(IP1SR0_31_28) IP1SR0_31_28 \
\
FM(IP0SR1_3_0) IP0SR1_3_0 FM(IP1SR1_3_0) IP1SR1_3_0 FM(IP2SR1_3_0) IP2SR1_3_0 FM(IP3SR1_3_0) IP3SR1_3_0 \
FM(IP0SR1_7_4) IP0SR1_7_4 FM(IP1SR1_7_4) IP1SR1_7_4 FM(IP2SR1_7_4) IP2SR1_7_4 FM(IP3SR1_7_4) IP3SR1_7_4 \
FM(IP0SR1_11_8) IP0SR1_11_8 FM(IP1SR1_11_8) IP1SR1_11_8 FM(IP2SR1_11_8) IP2SR1_11_8 FM(IP3SR1_11_8) IP3SR1_11_8 \
FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2SR1_15_12 FM(IP3SR1_15_12) IP3SR1_15_12 \
FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \
-FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \
-FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \
-FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \
+FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 \
+FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 \
+FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \
\
FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \
FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \
FM(IP0SR2_11_8) IP0SR2_11_8 FM(IP1SR2_11_8) IP1SR2_11_8 FM(IP2SR2_11_8) IP2SR2_11_8 \
FM(IP0SR2_15_12) IP0SR2_15_12 FM(IP1SR2_15_12) IP1SR2_15_12 FM(IP2SR2_15_12) IP2SR2_15_12 \
-FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 FM(IP2SR2_19_16) IP2SR2_19_16 \
-FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2SR2_23_20 \
-FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \
-FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \
+FM(IP0SR2_19_16) IP0SR2_19_16 FM(IP1SR2_19_16) IP1SR2_19_16 \
+FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 \
+FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 \
+FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 \
\
FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 FM(IP2SR3_3_0) IP2SR3_3_0 FM(IP3SR3_3_0) IP3SR3_3_0 \
FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 FM(IP2SR3_7_4) IP2SR3_7_4 FM(IP3SR3_7_4) IP3SR3_7_4 \
@@ -556,26 +533,26 @@ FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 FM(IP2SR3_11_8) IP2SR
FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 FM(IP2SR3_15_12) IP2SR3_15_12 FM(IP3SR3_15_12) IP3SR3_15_12 \
FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 FM(IP2SR3_19_16) IP2SR3_19_16 FM(IP3SR3_19_16) IP3SR3_19_16 \
FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 FM(IP2SR3_23_20) IP2SR3_23_20 FM(IP3SR3_23_20) IP3SR3_23_20 \
-FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 FM(IP3SR3_27_24) IP3SR3_27_24 \
-FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 FM(IP3SR3_31_28) IP3SR3_31_28 \
+FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 FM(IP2SR3_27_24) IP2SR3_27_24 \
+FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 FM(IP2SR3_31_28) IP2SR3_31_28 \
\
FM(IP0SR6_3_0) IP0SR6_3_0 FM(IP1SR6_3_0) IP1SR6_3_0 FM(IP2SR6_3_0) IP2SR6_3_0 \
FM(IP0SR6_7_4) IP0SR6_7_4 FM(IP1SR6_7_4) IP1SR6_7_4 FM(IP2SR6_7_4) IP2SR6_7_4 \
FM(IP0SR6_11_8) IP0SR6_11_8 FM(IP1SR6_11_8) IP1SR6_11_8 FM(IP2SR6_11_8) IP2SR6_11_8 \
FM(IP0SR6_15_12) IP0SR6_15_12 FM(IP1SR6_15_12) IP1SR6_15_12 FM(IP2SR6_15_12) IP2SR6_15_12 \
FM(IP0SR6_19_16) IP0SR6_19_16 FM(IP1SR6_19_16) IP1SR6_19_16 FM(IP2SR6_19_16) IP2SR6_19_16 \
-FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 FM(IP2SR6_23_20) IP2SR6_23_20 \
-FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 FM(IP2SR6_27_24) IP2SR6_27_24 \
-FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 FM(IP2SR6_31_28) IP2SR6_31_28 \
+FM(IP0SR6_23_20) IP0SR6_23_20 FM(IP1SR6_23_20) IP1SR6_23_20 \
+FM(IP0SR6_27_24) IP0SR6_27_24 FM(IP1SR6_27_24) IP1SR6_27_24 \
+FM(IP0SR6_31_28) IP0SR6_31_28 FM(IP1SR6_31_28) IP1SR6_31_28 \
\
FM(IP0SR7_3_0) IP0SR7_3_0 FM(IP1SR7_3_0) IP1SR7_3_0 FM(IP2SR7_3_0) IP2SR7_3_0 \
FM(IP0SR7_7_4) IP0SR7_7_4 FM(IP1SR7_7_4) IP1SR7_7_4 FM(IP2SR7_7_4) IP2SR7_7_4 \
FM(IP0SR7_11_8) IP0SR7_11_8 FM(IP1SR7_11_8) IP1SR7_11_8 FM(IP2SR7_11_8) IP2SR7_11_8 \
FM(IP0SR7_15_12) IP0SR7_15_12 FM(IP1SR7_15_12) IP1SR7_15_12 FM(IP2SR7_15_12) IP2SR7_15_12 \
FM(IP0SR7_19_16) IP0SR7_19_16 FM(IP1SR7_19_16) IP1SR7_19_16 FM(IP2SR7_19_16) IP2SR7_19_16 \
-FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 FM(IP2SR7_23_20) IP2SR7_23_20 \
-FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 FM(IP2SR7_27_24) IP2SR7_27_24 \
-FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 FM(IP2SR7_31_28) IP2SR7_31_28 \
+FM(IP0SR7_23_20) IP0SR7_23_20 FM(IP1SR7_23_20) IP1SR7_23_20 \
+FM(IP0SR7_27_24) IP0SR7_27_24 FM(IP1SR7_27_24) IP1SR7_27_24 \
+FM(IP0SR7_31_28) IP0SR7_31_28 FM(IP1SR7_31_28) IP1SR7_31_28 \
\
FM(IP0SR8_3_0) IP0SR8_3_0 FM(IP1SR8_3_0) IP1SR8_3_0 \
FM(IP0SR8_7_4) IP0SR8_7_4 FM(IP1SR8_7_4) IP1SR8_7_4 \
@@ -583,8 +560,8 @@ FM(IP0SR8_11_8) IP0SR8_11_8 FM(IP1SR8_11_8) IP1SR8_11_8 \
FM(IP0SR8_15_12) IP0SR8_15_12 FM(IP1SR8_15_12) IP1SR8_15_12 \
FM(IP0SR8_19_16) IP0SR8_19_16 FM(IP1SR8_19_16) IP1SR8_19_16 \
FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \
-FM(IP0SR8_27_24) IP0SR8_27_24 FM(IP1SR8_27_24) IP1SR8_27_24 \
-FM(IP0SR8_31_28) IP0SR8_31_28 FM(IP1SR8_31_28) IP1SR8_31_28
+FM(IP0SR8_27_24) IP0SR8_27_24 \
+FM(IP0SR8_31_28) IP0SR8_31_28
/* MOD_SEL4 */ /* 0 */ /* 1 */
#define MOD_SEL4_19 FM(SEL_TSN0_TD2_0) FM(SEL_TSN0_TD2_1)
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 07/21] pinctrl: renesas: r8a779g0: remove not used MOD_SELx definitions
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (4 preceding siblings ...)
2022-06-14 5:59 ` [PATCH v3 06/21] pinctrl: renesas: r8a779g0: remove not used IPxSRx definitions Kuninori Morimoto
@ 2022-06-14 5:59 ` Kuninori Morimoto
2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 08/21] pinctrl: renesas: r8a779g0: tidyup ioctrl_regs Kuninori Morimoto
` (14 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:59 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Current V4H PFC code has many MOD_SELx definitions with all 0.
But these have no meaning. This patch removes these, but keep
its definition to avoid unreadable PINMUX_MOD_SELS.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 72 +++++++++++++-------------
1 file changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index d049bb71dfe8..76d2cdddebe2 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -566,85 +566,85 @@ FM(IP0SR8_31_28) IP0SR8_31_28
/* MOD_SEL4 */ /* 0 */ /* 1 */
#define MOD_SEL4_19 FM(SEL_TSN0_TD2_0) FM(SEL_TSN0_TD2_1)
#define MOD_SEL4_18 FM(SEL_TSN0_TD3_0) FM(SEL_TSN0_TD3_1)
-#define MOD_SEL4_17 F_(0, 0) F_(0, 0)
-#define MOD_SEL4_16 F_(0, 0) F_(0, 0)
+#define MOD_SEL4_17
+#define MOD_SEL4_16
#define MOD_SEL4_15 FM(SEL_TSN0_TD0_0) FM(SEL_TSN0_TD0_1)
#define MOD_SEL4_14 FM(SEL_TSN0_TD1_0) FM(SEL_TSN0_TD1_1)
-#define MOD_SEL4_13 F_(0, 0) F_(0, 0)
+#define MOD_SEL4_13
#define MOD_SEL4_12 FM(SEL_TSN0_TXC_0) FM(SEL_TSN0_TXC_1)
-#define MOD_SEL4_11 F_(0, 0) F_(0, 0)
-#define MOD_SEL4_10 F_(0, 0) F_(0, 0)
+#define MOD_SEL4_11
+#define MOD_SEL4_10
#define MOD_SEL4_9 FM(SEL_TSN0_TX_CTL_0) FM(SEL_TSN0_TX_CTL_1)
#define MOD_SEL4_8 FM(SEL_TSN0_AVTP_PPS0_0) FM(SEL_TSN0_AVTP_PPS0_1)
-#define MOD_SEL4_7 F_(0, 0) F_(0, 0)
-#define MOD_SEL4_6 F_(0, 0) F_(0, 0)
+#define MOD_SEL4_7
+#define MOD_SEL4_6
#define MOD_SEL4_5 FM(SEL_TSN0_AVTP_MATCH_0) FM(SEL_TSN0_AVTP_MATCH_1)
-#define MOD_SEL4_4 F_(0, 0) F_(0, 0)
-#define MOD_SEL4_3 F_(0, 0) F_(0, 0)
+#define MOD_SEL4_4
+#define MOD_SEL4_3
#define MOD_SEL4_2 FM(SEL_TSN0_AVTP_PPS1_0) FM(SEL_TSN0_AVTP_PPS1_1)
#define MOD_SEL4_1 FM(SEL_TSN0_MDC_0) FM(SEL_TSN0_MDC_1)
-#define MOD_SEL4_0 F_(0, 0) F_(0, 0)
+#define MOD_SEL4_0
/* MOD_SEL5 */ /* 0 */ /* 1 */
#define MOD_SEL5_19 FM(SEL_AVB2_TX_CTL_0) FM(SEL_AVB2_TX_CTL_1)
-#define MOD_SEL5_18 F_(0, 0) F_(0, 0)
-#define MOD_SEL5_17 F_(0, 0) F_(0, 0)
+#define MOD_SEL5_18
+#define MOD_SEL5_17
#define MOD_SEL5_16 FM(SEL_AVB2_TXC_0) FM(SEL_AVB2_TXC_1)
#define MOD_SEL5_15 FM(SEL_AVB2_TD0_0) FM(SEL_AVB2_TD0_1)
-#define MOD_SEL5_14 F_(0, 0) F_(0, 0)
-#define MOD_SEL5_13 F_(0, 0) F_(0, 0)
+#define MOD_SEL5_14
+#define MOD_SEL5_13
#define MOD_SEL5_12 FM(SEL_AVB2_TD1_0) FM(SEL_AVB2_TD1_1)
#define MOD_SEL5_11 FM(SEL_AVB2_TD2_0) FM(SEL_AVB2_TD2_1)
-#define MOD_SEL5_10 F_(0, 0) F_(0, 0)
-#define MOD_SEL5_9 F_(0, 0) F_(0, 0)
+#define MOD_SEL5_10
+#define MOD_SEL5_9
#define MOD_SEL5_8 FM(SEL_AVB2_TD3_0) FM(SEL_AVB2_TD3_1)
-#define MOD_SEL5_7 F_(0, 0) F_(0, 0)
+#define MOD_SEL5_7
#define MOD_SEL5_6 FM(SEL_AVB2_MDC_0) FM(SEL_AVB2_MDC_1)
#define MOD_SEL5_5 FM(SEL_AVB2_MAGIC_0) FM(SEL_AVB2_MAGIC_1)
-#define MOD_SEL5_4 F_(0, 0) F_(0, 0)
-#define MOD_SEL5_3 F_(0, 0) F_(0, 0)
+#define MOD_SEL5_4
+#define MOD_SEL5_3
#define MOD_SEL5_2 FM(SEL_AVB2_AVTP_MATCH_0) FM(SEL_AVB2_AVTP_MATCH_1)
-#define MOD_SEL5_1 F_(0, 0) F_(0, 0)
+#define MOD_SEL5_1
#define MOD_SEL5_0 FM(SEL_AVB2_AVTP_PPS_0) FM(SEL_AVB2_AVTP_PPS_1)
/* MOD_SEL6 */ /* 0 */ /* 1 */
#define MOD_SEL6_18 FM(SEL_AVB1_TD3_0) FM(SEL_AVB1_TD3_1)
-#define MOD_SEL6_17 F_(0, 0) F_(0, 0)
+#define MOD_SEL6_17
#define MOD_SEL6_16 FM(SEL_AVB1_TD2_0) FM(SEL_AVB1_TD2_1)
-#define MOD_SEL6_15 F_(0, 0) F_(0, 0)
-#define MOD_SEL6_14 F_(0, 0) F_(0, 0)
+#define MOD_SEL6_15
+#define MOD_SEL6_14
#define MOD_SEL6_13 FM(SEL_AVB1_TD0_0) FM(SEL_AVB1_TD0_1)
#define MOD_SEL6_12 FM(SEL_AVB1_TD1_0) FM(SEL_AVB1_TD1_1)
-#define MOD_SEL6_11 F_(0, 0) F_(0, 0)
+#define MOD_SEL6_11
#define MOD_SEL6_10 FM(SEL_AVB1_AVTP_PPS_0) FM(SEL_AVB1_AVTP_PPS_1)
-#define MOD_SEL6_9 F_(0, 0) F_(0, 0)
-#define MOD_SEL6_8 F_(0, 0) F_(0, 0)
+#define MOD_SEL6_9
+#define MOD_SEL6_8
#define MOD_SEL6_7 FM(SEL_AVB1_TX_CTL_0) FM(SEL_AVB1_TX_CTL_1)
#define MOD_SEL6_6 FM(SEL_AVB1_TXC_0) FM(SEL_AVB1_TXC_1)
#define MOD_SEL6_5 FM(SEL_AVB1_AVTP_MATCH_0) FM(SEL_AVB1_AVTP_MATCH_1)
-#define MOD_SEL6_4 F_(0, 0) F_(0, 0)
-#define MOD_SEL6_3 F_(0, 0) F_(0, 0)
+#define MOD_SEL6_4
+#define MOD_SEL6_3
#define MOD_SEL6_2 FM(SEL_AVB1_MDC_0) FM(SEL_AVB1_MDC_1)
#define MOD_SEL6_1 FM(SEL_AVB1_MAGIC_0) FM(SEL_AVB1_MAGIC_1)
-#define MOD_SEL6_0 F_(0, 0) F_(0, 0)
+#define MOD_SEL6_0
/* MOD_SEL7 */ /* 0 */ /* 1 */
#define MOD_SEL7_16 FM(SEL_AVB0_TX_CTL_0) FM(SEL_AVB0_TX_CTL_1)
#define MOD_SEL7_15 FM(SEL_AVB0_TXC_0) FM(SEL_AVB0_TXC_1)
-#define MOD_SEL7_14 F_(0, 0) F_(0, 0)
+#define MOD_SEL7_14
#define MOD_SEL7_13 FM(SEL_AVB0_MDC_0) FM(SEL_AVB0_MDC_1)
-#define MOD_SEL7_12 F_(0, 0) F_(0, 0)
+#define MOD_SEL7_12
#define MOD_SEL7_11 FM(SEL_AVB0_TD0_0) FM(SEL_AVB0_TD0_1)
#define MOD_SEL7_10 FM(SEL_AVB0_MAGIC_0) FM(SEL_AVB0_MAGIC_1)
-#define MOD_SEL7_9 F_(0, 0) F_(0, 0)
-#define MOD_SEL7_8 F_(0, 0) F_(0, 0)
+#define MOD_SEL7_9
+#define MOD_SEL7_8
#define MOD_SEL7_7 FM(SEL_AVB0_TD1_0) FM(SEL_AVB0_TD1_1)
#define MOD_SEL7_6 FM(SEL_AVB0_TD2_0) FM(SEL_AVB0_TD2_1)
-#define MOD_SEL7_5 F_(0, 0) F_(0, 0)
-#define MOD_SEL7_4 F_(0, 0) F_(0, 0)
+#define MOD_SEL7_5
+#define MOD_SEL7_4
#define MOD_SEL7_3 FM(SEL_AVB0_TD3_0) FM(SEL_AVB0_TD3_1)
#define MOD_SEL7_2 FM(SEL_AVB0_AVTP_MATCH_0) FM(SEL_AVB0_AVTP_MATCH_1)
-#define MOD_SEL7_1 F_(0, 0) F_(0, 0)
+#define MOD_SEL7_1
#define MOD_SEL7_0 FM(SEL_AVB0_AVTP_PPS_0) FM(SEL_AVB0_AVTP_PPS_1)
/* MOD_SEL8 */ /* 0 */ /* 1 */
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 08/21] pinctrl: renesas: r8a779g0: tidyup ioctrl_regs
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (5 preceding siblings ...)
2022-06-14 5:59 ` [PATCH v3 07/21] pinctrl: renesas: r8a779g0: remove not used MOD_SELx definitions Kuninori Morimoto
@ 2022-06-14 5:59 ` Kuninori Morimoto
2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X Kuninori Morimoto
` (13 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:59 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch comment out POC2 which is not used/documented,
and remove TD0SEL3 which is no need to have.
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 76d2cdddebe2..ae179b2f7e1b 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -3657,27 +3657,25 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
enum ioctrl_regs {
POC0,
POC1,
- POC2,
+/* POC2, is not used */
POC3,
POC4,
POC5,
POC6,
POC7,
POC8,
- TD0SEL3,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POC0] = { 0xE60500A0, },
[POC1] = { 0xE60508A0, },
- [POC2] = { 0xE60580A0, },
+/* [POC2] = { 0xE60580A0, }, is not used */
[POC3] = { 0xE60588A0, },
[POC4] = { 0xE60600A0, },
[POC5] = { 0xE60608A0, },
[POC6] = { 0xE60610A0, },
[POC7] = { 0xE60618A0, },
[POC8] = { 0xE60680A0, },
- [TD0SEL3] = { 0xE60589C0, },
{ /* sentinel */ },
};
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (6 preceding siblings ...)
2022-06-14 5:59 ` [PATCH v3 08/21] pinctrl: renesas: r8a779g0: tidyup ioctrl_regs Kuninori Morimoto
@ 2022-06-14 5:59 ` Kuninori Morimoto
2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 10/21] pinctrl: renesas: r8a779g0: add missing IRQx_A/IRQx_B Kuninori Morimoto
` (12 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:59 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X
Because Document has 2xTCLK3/TCLK4 with no suffix (_A, _B),
this patch name it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index ae179b2f7e1b..e70e6aa82268 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -263,7 +263,7 @@
/* SR0 */
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -334,15 +334,15 @@
#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_31_28 FM(TPU0TO1) FM(CANFD6_TX) F_(0, 0) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_7_4 FM(CAN_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_11_8 FM(CANFD0_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -369,8 +369,8 @@
#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -766,6 +766,7 @@ static const u16 pinmux_data[] = {
/* IP0SR0 */
PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC),
+ PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A),
PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
@@ -920,10 +921,12 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP0SR2_31_28, TPU0TO1),
PINMUX_IPSR_GPSR(IP0SR2_31_28, CANFD6_TX),
+ PINMUX_IPSR_GPSR(IP0SR2_31_28, TCLK2_B),
/* IP1SR2 */
PINMUX_IPSR_GPSR(IP1SR2_3_0, TPU0TO0),
PINMUX_IPSR_GPSR(IP1SR2_3_0, CANFD6_RX),
+ PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A),
PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
@@ -934,10 +937,12 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX),
PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2),
+ PINMUX_IPSR_GPSR(IP1SR2_19_16, TCLK3_A),
PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1),
+ PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
@@ -980,9 +985,11 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
+ PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X),
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
+ PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X),
PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 10/21] pinctrl: renesas: r8a779g0: add missing IRQx_A/IRQx_B
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (7 preceding siblings ...)
2022-06-14 5:59 ` [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X Kuninori Morimoto
@ 2022-06-14 5:59 ` Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 11/21] pinctrl: renesas: r8a779g0: add missing HSCIF3_A Kuninori Morimoto
` (11 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:59 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch adds missing IRQx_A/IRQx_B
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index e70e6aa82268..4e4ccbc32dac 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -278,7 +278,7 @@
#define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -313,10 +313,10 @@
#define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_11_8 FM(SSI_SCK) FM(TCLK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_19_16 FM(SSI_SD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_23_20 FM(AUDIO_CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP3SR1_3_0 FM(HRX3) FM(SCK3) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -330,7 +330,7 @@
#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_23_20 FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_27_24 FM(FXR_TXDB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -799,6 +799,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR0_23_20, MSIOF2_SS2),
PINMUX_IPSR_GPSR(IP1SR0_23_20, TCLK1),
+ PINMUX_IPSR_GPSR(IP1SR0_23_20, IRQ2_A),
PINMUX_IPSR_GPSR(IP1SR0_27_24, MSIOF2_SS1),
PINMUX_IPSR_GPSR(IP1SR0_27_24, HTX1),
@@ -869,14 +870,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2SR1_15_12, TCLK4),
PINMUX_IPSR_GPSR(IP2SR1_19_16, SSI_SD),
+ PINMUX_IPSR_GPSR(IP2SR1_19_16, IRQ0_A),
PINMUX_IPSR_GPSR(IP2SR1_23_20, AUDIO_CLKOUT),
+ PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A),
PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3),
PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2),
PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
+ PINMUX_IPSR_GPSR(IP2SR1_31_28, IRQ3_B),
/* IP3SR1 */
PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
@@ -912,6 +916,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP0SR2_15_12, CLK_EXTFXR),
PINMUX_IPSR_GPSR(IP0SR2_15_12, CANFD5_RX),
+ PINMUX_IPSR_GPSR(IP0SR2_15_12, IRQ4_B),
PINMUX_IPSR_GPSR(IP0SR2_19_16, RXDB_EXTFXR),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 11/21] pinctrl: renesas: r8a779g0: add missing HSCIF3_A
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (8 preceding siblings ...)
2022-06-14 5:59 ` [PATCH v3 10/21] pinctrl: renesas: r8a779g0: add missing IRQx_A/IRQx_B Kuninori Morimoto
@ 2022-06-14 5:59 ` Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 12/21] pinctrl: renesas: r8a779g0: add missing HSCIF1_X Kuninori Morimoto
` (10 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:59 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch adds missing HSCIF3_A
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 53 +++++++++++++++++++++++---
1 file changed, 48 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 4e4ccbc32dac..d84fa59a0bcc 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -289,11 +289,11 @@
/* SR1 */
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR1_3_0 FM(MSIOF1_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_7_4 FM(MSIOF1_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_11_8 FM(MSIOF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_15_12 FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_19_16 FM(MSIOF1_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_27_24 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_31_28 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -824,10 +824,20 @@ static const u16 pinmux_data[] = {
/* IP0SR1 */
PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
+ PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
+
PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
+ PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_A_N),
+
PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
+ PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_A_N),
+
PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
+ PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
+
PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
+ PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
+
PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
@@ -1590,6 +1600,29 @@ static const unsigned int hscif3_ctrl_mux[] = {
HRTS3_N_MARK, HCTS3_N_MARK,
};
+/* - HSCIF3_A ----------------------------------------------------------------- */
+static const unsigned int hscif3_a_data_pins[] = {
+ /* HRX3, HTX3 */
+ RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
+};
+static const unsigned int hscif3_a_data_mux[] = {
+ HRX3_A_MARK, HTX3_A_MARK,
+};
+static const unsigned int hscif3_a_clk_pins[] = {
+ /* HSCK3 */
+ RCAR_GP_PIN(1, 3),
+};
+static const unsigned int hscif3_a_clk_mux[] = {
+ HSCK3_A_MARK,
+};
+static const unsigned int hscif3_a_ctrl_pins[] = {
+ /* HRTS3#, HCTS3# */
+ RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
+};
+static const unsigned int hscif3_a_ctrl_mux[] = {
+ HRTS3_A_N_MARK, HCTS3_A_N_MARK,
+};
+
/* - I2C0 ------------------------------------------------------------------- */
static const unsigned int i2c0_pins[] = {
/* SDA0, SCL0 */
@@ -2351,6 +2384,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hscif3_data),
SH_PFC_PIN_GROUP(hscif3_clk),
SH_PFC_PIN_GROUP(hscif3_ctrl),
+ SH_PFC_PIN_GROUP(hscif3_a_data),
+ SH_PFC_PIN_GROUP(hscif3_a_clk),
+ SH_PFC_PIN_GROUP(hscif3_a_ctrl),
SH_PFC_PIN_GROUP(i2c0),
SH_PFC_PIN_GROUP(i2c1),
@@ -2555,6 +2591,12 @@ static const char * const hscif3_groups[] = {
"hscif3_ctrl",
};
+static const char * const hscif3_a_groups[] = {
+ "hscif3_a_data",
+ "hscif3_a_clk",
+ "hscif3_a_ctrl",
+};
+
static const char * const i2c0_groups[] = {
"i2c0",
};
@@ -2765,6 +2807,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
+ SH_PFC_FUNCTION(hscif3_a),
SH_PFC_FUNCTION(i2c0),
SH_PFC_FUNCTION(i2c1),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 12/21] pinctrl: renesas: r8a779g0: add missing HSCIF1_X
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (9 preceding siblings ...)
2022-06-14 5:59 ` [PATCH v3 11/21] pinctrl: renesas: r8a779g0: add missing HSCIF3_A Kuninori Morimoto
@ 2022-06-14 5:59 ` Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 13/21] pinctrl: renesas: r8a779g0: add missing SCIF3 Kuninori Morimoto
` (9 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 5:59 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch adds missing HSCIF1.
Because Document has 2xHSCIF1 with no suffix (_A, _B),
this patch name it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 50 +++++++++++++++++++++++---
1 file changed, 45 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index d84fa59a0bcc..8af0bc89d4e1 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -295,13 +295,13 @@
#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_27_24 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_31_28 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR1_3_0 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_7_4 FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_11_8 FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -839,15 +839,22 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
+
PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
+ PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X),
+
PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
+ PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X),
/* IP1SR1 */
PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
+ PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_X_N),
PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
+ PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_X_N),
PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
+ PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X),
PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
@@ -1554,6 +1561,29 @@ static const unsigned int hscif1_ctrl_mux[] = {
HRTS1_N_MARK, HCTS1_N_MARK,
};
+/* - HSCIF1_X---------------------------------------------------------------- */
+static const unsigned int hscif1_x_data_pins[] = {
+ /* HRX1_X, HTX1_X */
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int hscif1_x_data_mux[] = {
+ HRX1_X_MARK, HTX1_X_MARK,
+};
+static const unsigned int hscif1_x_clk_pins[] = {
+ /* HSCK1_X */
+ RCAR_GP_PIN(1, 10),
+};
+static const unsigned int hscif1_x_clk_mux[] = {
+ HSCK1_X_MARK,
+};
+static const unsigned int hscif1_x_ctrl_pins[] = {
+ /* HRTS1_X_N, HCTS1_X_N */
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int hscif1_x_ctrl_mux[] = {
+ HRTS1_X_N_MARK, HCTS1_X_N_MARK,
+};
+
/* - HSCIF2 ----------------------------------------------------------------- */
static const unsigned int hscif2_data_pins[] = {
/* HRX2, HTX2 */
@@ -2378,6 +2408,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(hscif1_data),
SH_PFC_PIN_GROUP(hscif1_clk),
SH_PFC_PIN_GROUP(hscif1_ctrl),
+ SH_PFC_PIN_GROUP(hscif1_x_data),
+ SH_PFC_PIN_GROUP(hscif1_x_clk),
+ SH_PFC_PIN_GROUP(hscif1_x_ctrl),
SH_PFC_PIN_GROUP(hscif2_data),
SH_PFC_PIN_GROUP(hscif2_clk),
SH_PFC_PIN_GROUP(hscif2_ctrl),
@@ -2579,6 +2612,12 @@ static const char * const hscif1_groups[] = {
"hscif1_ctrl",
};
+static const char * const hscif1_x_groups[] = {
+ "hscif1_x_data",
+ "hscif1_x_clk",
+ "hscif1_x_ctrl",
+};
+
static const char * const hscif2_groups[] = {
"hscif2_data",
"hscif2_clk",
@@ -2805,6 +2844,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
+ SH_PFC_FUNCTION(hscif1_x),
SH_PFC_FUNCTION(hscif2),
SH_PFC_FUNCTION(hscif3),
SH_PFC_FUNCTION(hscif3_a),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 13/21] pinctrl: renesas: r8a779g0: add missing SCIF3
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (10 preceding siblings ...)
2022-06-14 5:59 ` [PATCH v3 12/21] pinctrl: renesas: r8a779g0: add missing HSCIF1_X Kuninori Morimoto
@ 2022-06-14 6:00 ` Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 14/21] pinctrl: renesas: r8a779g0: add missing SCIF1_X Kuninori Morimoto
` (8 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 6:00 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
Exising SCIF3 settings on IP3SR1 should be SCIF3_A,
and existing settings on scif3_xxx[] are for SCIF3.
This patch add missing SCIF3 settings on IP0SR1,
rename IP3SR1 settings to SCIF3_A,
add missing scif3_a_xxx[].
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 68 ++++++++++++++++++++------
1 file changed, 53 insertions(+), 15 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 8af0bc89d4e1..634ef17b76f0 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -289,11 +289,11 @@
/* SR1 */
/* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) FM(TX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_A_N) FM(RX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_A_N) FM(RTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -319,11 +319,11 @@
#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP3SR1_3_0 FM(HRX3) FM(SCK3) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_19_16 FM(HTX3) FM(TX3) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_A_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_A_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR2 */
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -825,18 +825,23 @@ static const u16 pinmux_data[] = {
/* IP0SR1 */
PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
+ PINMUX_IPSR_GPSR(IP0SR1_3_0, TX3),
PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_A_N),
+ PINMUX_IPSR_GPSR(IP0SR1_7_4, RX3),
PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_A_N),
+ PINMUX_IPSR_GPSR(IP0SR1_11_8, RTS3_N),
PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
+ PINMUX_IPSR_GPSR(IP0SR1_15_12, CTS3_N),
PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
+ PINMUX_IPSR_GPSR(IP0SR1_19_16, SCK3),
PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
@@ -901,23 +906,23 @@ static const u16 pinmux_data[] = {
/* IP3SR1 */
PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
- PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3),
+ PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
- PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N),
+ PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_A_N),
PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
- PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N),
+ PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_A_N),
PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
- PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3),
+ PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
- PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3),
+ PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
/* IP0SR2 */
@@ -2228,6 +2233,29 @@ static const unsigned int scif3_ctrl_mux[] = {
RTS3_N_MARK, CTS3_N_MARK,
};
+/* - SCIF3_A ------------------------------------------------------------------ */
+static const unsigned int scif3_a_data_pins[] = {
+ /* RX3_A, TX3_A */
+ RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
+};
+static const unsigned int scif3_a_data_mux[] = {
+ RX3_A_MARK, TX3_A_MARK,
+};
+static const unsigned int scif3_a_clk_pins[] = {
+ /* SCK3_A */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int scif3_a_clk_mux[] = {
+ SCK3_A_MARK,
+};
+static const unsigned int scif3_a_ctrl_pins[] = {
+ /* RTS3_A_N, CTS3_A_N */
+ RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
+};
+static const unsigned int scif3_a_ctrl_mux[] = {
+ RTS3_A_N_MARK, CTS3_A_N_MARK,
+};
+
/* - SCIF4 ------------------------------------------------------------------ */
static const unsigned int scif4_data_pins[] = {
/* RX4, TX4 */
@@ -2508,6 +2536,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif3_data),
SH_PFC_PIN_GROUP(scif3_clk),
SH_PFC_PIN_GROUP(scif3_ctrl),
+ SH_PFC_PIN_GROUP(scif3_a_data),
+ SH_PFC_PIN_GROUP(scif3_a_clk),
+ SH_PFC_PIN_GROUP(scif3_a_ctrl),
SH_PFC_PIN_GROUP(scif4_data),
SH_PFC_PIN_GROUP(scif4_clk),
SH_PFC_PIN_GROUP(scif4_ctrl),
@@ -2799,6 +2830,12 @@ static const char * const scif3_groups[] = {
"scif3_ctrl",
};
+static const char * const scif3_a_groups[] = {
+ "scif3_a_data",
+ "scif3_a_clk",
+ "scif3_a_ctrl",
+};
+
static const char * const scif4_groups[] = {
"scif4_data",
"scif4_clk",
@@ -2884,6 +2921,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif3_a),
SH_PFC_FUNCTION(scif4),
SH_PFC_FUNCTION(scif_clk),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 14/21] pinctrl: renesas: r8a779g0: add missing SCIF1_X
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (11 preceding siblings ...)
2022-06-14 6:00 ` [PATCH v3 13/21] pinctrl: renesas: r8a779g0: add missing SCIF3 Kuninori Morimoto
@ 2022-06-14 6:00 ` Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 15/21] pinctrl: renesas: r8a779g0: add missing CANFD5_B Kuninori Morimoto
` (7 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 6:00 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch adds missing SCIF1_X.
Because Document has 2xSCIF1 with no suffix (_A, _B),
this patch name it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 48 +++++++++++++++++++++++---
1 file changed, 43 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 634ef17b76f0..68b1c1ba2450 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -295,13 +295,13 @@
#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_X_N) FM(CTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_X_N) FM(RTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -847,19 +847,24 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
PINMUX_IPSR_GPSR(IP0SR1_27_24, HTX1_X),
+ PINMUX_IPSR_GPSR(IP0SR1_27_24, TX1_X),
PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
PINMUX_IPSR_GPSR(IP0SR1_31_28, HRX1_X),
+ PINMUX_IPSR_GPSR(IP0SR1_31_28, RX1_X),
/* IP1SR1 */
PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_X_N),
+ PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_X_N),
PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_X_N),
+ PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_X_N),
PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X),
+ PINMUX_IPSR_GPSR(IP1SR1_11_8, SCK1_X),
PINMUX_IPSR_GPSR(IP1SR1_15_12, MSIOF0_RXD),
@@ -2210,6 +2215,29 @@ static const unsigned int scif1_ctrl_mux[] = {
RTS1_N_MARK, CTS1_N_MARK,
};
+/* - SCIF1_X ------------------------------------------------------------------ */
+static const unsigned int scif1_x_data_pins[] = {
+ /* RX1_X, TX1_X */
+ RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int scif1_x_data_mux[] = {
+ RX1_X_MARK, TX1_X_MARK,
+};
+static const unsigned int scif1_x_clk_pins[] = {
+ /* SCK1_X */
+ RCAR_GP_PIN(1, 10),
+};
+static const unsigned int scif1_x_clk_mux[] = {
+ SCK1_X_MARK,
+};
+static const unsigned int scif1_x_ctrl_pins[] = {
+ /* RTS1_X_N, CTS1_X_N */
+ RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int scif1_x_ctrl_mux[] = {
+ RTS1_X_N_MARK, CTS1_X_N_MARK,
+};
+
/* - SCIF3 ------------------------------------------------------------------ */
static const unsigned int scif3_data_pins[] = {
/* RX3, TX3 */
@@ -2533,6 +2561,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif1_data),
SH_PFC_PIN_GROUP(scif1_clk),
SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_x_data),
+ SH_PFC_PIN_GROUP(scif1_x_clk),
+ SH_PFC_PIN_GROUP(scif1_x_ctrl),
SH_PFC_PIN_GROUP(scif3_data),
SH_PFC_PIN_GROUP(scif3_clk),
SH_PFC_PIN_GROUP(scif3_ctrl),
@@ -2824,6 +2855,12 @@ static const char * const scif1_groups[] = {
"scif1_ctrl",
};
+static const char * const scif1_x_groups[] = {
+ "scif1_x_data",
+ "scif1_x_clk",
+ "scif1_x_ctrl",
+};
+
static const char * const scif3_groups[] = {
"scif3_data",
"scif3_clk",
@@ -2920,6 +2957,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif1_x),
SH_PFC_FUNCTION(scif3),
SH_PFC_FUNCTION(scif3_a),
SH_PFC_FUNCTION(scif4),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 15/21] pinctrl: renesas: r8a779g0: add missing CANFD5_B
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (12 preceding siblings ...)
2022-06-14 6:00 ` [PATCH v3 14/21] pinctrl: renesas: r8a779g0: add missing SCIF1_X Kuninori Morimoto
@ 2022-06-14 6:00 ` Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 16/21] pinctrl: renesas: r8a779g0: add missing TPU0TOx_A Kuninori Morimoto
` (6 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 6:00 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch adds missing CANFD5_B
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 21 +++++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 68b1c1ba2450..5bee4ab2d132 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -299,8 +299,8 @@
#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_X_N) FM(CTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_X_N) FM(RTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_X_N) FM(CTS1_X_N) FM(CANFD5_B_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_X_N) FM(RTS1_X_N) FM(CANFD5_B_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -857,10 +857,12 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR1_3_0, MSIOF0_SYNC),
PINMUX_IPSR_GPSR(IP1SR1_3_0, HCTS1_X_N),
PINMUX_IPSR_GPSR(IP1SR1_3_0, CTS1_X_N),
+ PINMUX_IPSR_GPSR(IP1SR1_3_0, CANFD5_B_TX),
PINMUX_IPSR_GPSR(IP1SR1_7_4, MSIOF0_TXD),
PINMUX_IPSR_GPSR(IP1SR1_7_4, HRTS1_X_N),
PINMUX_IPSR_GPSR(IP1SR1_7_4, RTS1_X_N),
+ PINMUX_IPSR_GPSR(IP1SR1_7_4, CANFD5_B_RX),
PINMUX_IPSR_GPSR(IP1SR1_11_8, MSIOF0_SCK),
PINMUX_IPSR_GPSR(IP1SR1_11_8, HSCK1_X),
@@ -1498,6 +1500,15 @@ static const unsigned int canfd5_data_mux[] = {
CANFD5_TX_MARK, CANFD5_RX_MARK,
};
+/* - CANFD5_B ----------------------------------------------------------------- */
+static const unsigned int canfd5_b_data_pins[] = {
+ /* CANFD5_B_TX, CANFD5_B_RX */
+ RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
+};
+static const unsigned int canfd5_b_data_mux[] = {
+ CANFD5_B_TX_MARK, CANFD5_B_RX_MARK,
+};
+
/* - CANFD6 ----------------------------------------------------------------- */
static const unsigned int canfd6_data_pins[] = {
/* CANFD6_TX, CANFD6_RX */
@@ -2454,6 +2465,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(canfd3_data),
SH_PFC_PIN_GROUP(canfd4_data),
SH_PFC_PIN_GROUP(canfd5_data),
+ SH_PFC_PIN_GROUP(canfd5_b_data),
SH_PFC_PIN_GROUP(canfd6_data),
SH_PFC_PIN_GROUP(canfd7_data),
SH_PFC_PIN_GROUP(can_clk),
@@ -2650,6 +2662,10 @@ static const char * const canfd5_groups[] = {
"canfd5_data",
};
+static const char * const canfd5_b_groups[] = {
+ "canfd5_b_data",
+};
+
static const char * const canfd6_groups[] = {
"canfd6_data",
};
@@ -2912,6 +2928,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(canfd3),
SH_PFC_FUNCTION(canfd4),
SH_PFC_FUNCTION(canfd5),
+ SH_PFC_FUNCTION(canfd5_b),
SH_PFC_FUNCTION(canfd6),
SH_PFC_FUNCTION(canfd7),
SH_PFC_FUNCTION(can_clk),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 16/21] pinctrl: renesas: r8a779g0: add missing TPU0TOx_A
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (13 preceding siblings ...)
2022-06-14 6:00 ` [PATCH v3 15/21] pinctrl: renesas: r8a779g0: add missing CANFD5_B Kuninori Morimoto
@ 2022-06-14 6:00 ` Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 17/21] pinctrl: renesas: r8a779g0: add missing FlaxRay Kuninori Morimoto
` (5 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 6:00 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch adds missing TPU0TOx_A
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 54 ++++++++++++++++++++++++--
1 file changed, 50 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 5bee4ab2d132..18881a651d1b 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -320,15 +320,15 @@
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_A_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_A_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_A_N) FM(MSIOF4_SCK) FM(TPU0TO0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_A_N) FM(MSIOF4_TXD) FM(TPU0TO1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* SR2 */
/* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_3_0 FM(FXR_TXDA) FM(CANFD1_TX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR2_7_4 FM(FXR_TXENA_N) FM(CANFD1_RX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_11_8 FM(RXDA_EXTFXR) FM(CANFD5_TX) FM(IRQ5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_15_12 FM(CLK_EXTFXR) FM(CANFD5_RX) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR2_19_16 FM(RXDB_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -919,10 +919,12 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_A_N),
PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
+ PINMUX_IPSR_GPSR(IP3SR1_7_4, TPU0TO0_A),
PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_A_N),
PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
+ PINMUX_IPSR_GPSR(IP3SR1_11_8, TPU0TO1_A),
PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
@@ -935,9 +937,11 @@ static const u16 pinmux_data[] = {
/* IP0SR2 */
PINMUX_IPSR_GPSR(IP0SR2_3_0, FXR_TXDA),
PINMUX_IPSR_GPSR(IP0SR2_3_0, CANFD1_TX),
+ PINMUX_IPSR_GPSR(IP0SR2_3_0, TPU0TO2_A),
PINMUX_IPSR_GPSR(IP0SR2_7_4, FXR_TXENA_N),
PINMUX_IPSR_GPSR(IP0SR2_7_4, CANFD1_RX),
+ PINMUX_IPSR_GPSR(IP0SR2_7_4, TPU0TO3_A),
PINMUX_IPSR_GPSR(IP0SR2_11_8, RXDA_EXTFXR),
PINMUX_IPSR_GPSR(IP0SR2_11_8, CANFD5_TX),
@@ -2357,6 +2361,36 @@ static const unsigned int tpu_to3_mux[] = {
TPU0TO3_MARK,
};
+/* - TPU_A ------------------------------------------------------------------- */
+static const unsigned int tpu_to0_a_pins[] = {
+ /* TPU0TO0_A */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int tpu_to0_a_mux[] = {
+ TPU0TO0_A_MARK,
+};
+static const unsigned int tpu_to1_a_pins[] = {
+ /* TPU0TO1_A */
+ RCAR_GP_PIN(1, 26),
+};
+static const unsigned int tpu_to1_a_mux[] = {
+ TPU0TO1_A_MARK,
+};
+static const unsigned int tpu_to2_a_pins[] = {
+ /* TPU0TO2_A */
+ RCAR_GP_PIN(2, 0),
+};
+static const unsigned int tpu_to2_a_mux[] = {
+ TPU0TO2_A_MARK,
+};
+static const unsigned int tpu_to3_a_pins[] = {
+ /* TPU0TO3_A */
+ RCAR_GP_PIN(2, 1),
+};
+static const unsigned int tpu_to3_a_mux[] = {
+ TPU0TO3_A_MARK,
+};
+
/* - TSN0 ------------------------------------------------ */
static const unsigned int tsn0_link_pins[] = {
/* TSN0_LINK */
@@ -2588,9 +2622,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(scif_clk),
SH_PFC_PIN_GROUP(tpu_to0),
+ SH_PFC_PIN_GROUP(tpu_to0_a),
SH_PFC_PIN_GROUP(tpu_to1),
+ SH_PFC_PIN_GROUP(tpu_to1_a),
SH_PFC_PIN_GROUP(tpu_to2),
+ SH_PFC_PIN_GROUP(tpu_to2_a),
SH_PFC_PIN_GROUP(tpu_to3),
+ SH_PFC_PIN_GROUP(tpu_to3_a),
SH_PFC_PIN_GROUP(tsn0_link),
SH_PFC_PIN_GROUP(tsn0_phy_int),
@@ -2906,6 +2944,13 @@ static const char * const tpu_groups[] = {
"tpu_to3",
};
+static const char * const tpu_a_groups[] = {
+ "tpu_to0_a",
+ "tpu_to1_a",
+ "tpu_to2_a",
+ "tpu_to3_a",
+};
+
static const char * const tsn0_groups[] = {
"tsn0_link",
"tsn0_phy_int",
@@ -2981,6 +3026,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(scif_clk),
SH_PFC_FUNCTION(tpu),
+ SH_PFC_FUNCTION(tpu_a),
SH_PFC_FUNCTION(tsn0),
};
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 17/21] pinctrl: renesas: r8a779g0: add missing FlaxRay
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (14 preceding siblings ...)
2022-06-14 6:00 ` [PATCH v3 16/21] pinctrl: renesas: r8a779g0: add missing TPU0TOx_A Kuninori Morimoto
@ 2022-06-14 6:00 ` Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 18/21] pinctrl: renesas: r8a779g0: add missing PWM Kuninori Morimoto
` (4 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 6:00 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch adds missing FlaxRay pins.
Because Document has 2xFXR_TXENA/B pin with no suffix (_A, _B),
this patch name it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 18881a651d1b..b68d6e24b18f 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -338,8 +338,8 @@
/* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_7_4 FM(CAN_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_11_8 FM(CANFD0_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -967,8 +967,10 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR2_3_0, TCLK1_A),
PINMUX_IPSR_GPSR(IP1SR2_7_4, CAN_CLK),
+ PINMUX_IPSR_GPSR(IP1SR2_7_4, FXR_TXENA_X_N),
PINMUX_IPSR_GPSR(IP1SR2_11_8, CANFD0_TX),
+ PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_X_N),
PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX),
PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 18/21] pinctrl: renesas: r8a779g0: add missing PWM
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (15 preceding siblings ...)
2022-06-14 6:00 ` [PATCH v3 17/21] pinctrl: renesas: r8a779g0: add missing FlaxRay Kuninori Morimoto
@ 2022-06-14 6:00 ` Kuninori Morimoto
2022-06-17 15:19 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 19/21] pinctrl: renesas: r8a779g0: add missing ERROROUTC_A Kuninori Morimoto
` (3 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 6:00 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed.
This patch add missing PWM settings, and tidyup these.
According to Document, GP3_14 Function4 is PWM2_A,
but we can't select it at P1SR3[27:24].
This patch just ignore it for now.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 168 +++++++++++++++----------
1 file changed, 100 insertions(+), 68 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index b68d6e24b18f..ba9489d1074c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -304,9 +304,9 @@
#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR1_3_0 FM(HRX0) FM(RX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -315,7 +315,7 @@
#define IP2SR1_15_12 FM(SSI_WS) FM(TCLK4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_19_16 FM(SSI_SD) FM(IRQ0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_23_20 FM(AUDIO_CLKOUT) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP2SR1_27_24 FM(AUDIO_CLKIN) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -342,9 +342,9 @@
#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1_B) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR2_31_28 FM(CANFD3_RX) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
#define IP2SR2_3_0 FM(CANFD4_TX) F_(0, 0) FM(PWM4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -369,7 +369,7 @@
#define IP1SR3_11_8 FM(MMC_SD_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -875,15 +875,15 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR1_23_20, HCTS0_N),
PINMUX_IPSR_GPSR(IP1SR1_23_20, CTS0_N),
- PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8),
+ PINMUX_IPSR_GPSR(IP1SR1_23_20, PWM8_A),
PINMUX_IPSR_GPSR(IP1SR1_27_24, HRTS0_N),
PINMUX_IPSR_GPSR(IP1SR1_27_24, RTS0_N),
- PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9),
+ PINMUX_IPSR_GPSR(IP1SR1_27_24, PWM9_A),
PINMUX_IPSR_GPSR(IP1SR1_31_28, HSCK0),
PINMUX_IPSR_GPSR(IP1SR1_31_28, SCK0),
- PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0),
+ PINMUX_IPSR_GPSR(IP1SR1_31_28, PWM0_A),
/* IP2SR1 */
PINMUX_IPSR_GPSR(IP2SR1_3_0, HRX0),
@@ -905,7 +905,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP2SR1_23_20, IRQ1_A),
PINMUX_IPSR_GPSR(IP2SR1_27_24, AUDIO_CLKIN),
- PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3),
+ PINMUX_IPSR_GPSR(IP2SR1_27_24, PWM3_A),
PINMUX_IPSR_GPSR(IP2SR1_31_28, TCLK2),
PINMUX_IPSR_GPSR(IP2SR1_31_28, MSIOF4_SS1),
@@ -981,13 +981,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR2_23_20, CANFD2_RX),
PINMUX_IPSR_GPSR(IP1SR2_23_20, TPU0TO3),
- PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1),
+ PINMUX_IPSR_GPSR(IP1SR2_23_20, PWM1_B),
PINMUX_IPSR_GPSR(IP1SR2_23_20, TCLK4_A),
PINMUX_IPSR_GPSR(IP1SR2_27_24, CANFD3_TX),
- PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2),
+ PINMUX_IPSR_GPSR(IP1SR2_27_24, PWM2_B),
PINMUX_IPSR_GPSR(IP1SR2_31_28, CANFD3_RX),
+ PINMUX_IPSR_GPSR(IP1SR2_31_28, PWM3_B),
/* IP2SR2 */
PINMUX_IPSR_GPSR(IP2SR2_3_0, CANFD4_TX),
@@ -1025,6 +1026,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKIN),
PINMUX_IPSR_GPSR(IP1SR3_23_20, IPC_CLKEN_IN),
+ PINMUX_IPSR_GPSR(IP1SR3_23_20, PWM1_A),
PINMUX_IPSR_GPSR(IP1SR3_23_20, TCLK3_X),
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
@@ -2060,40 +2062,58 @@ static const unsigned int pcie1_clkreq_n_mux[] = {
PCIE1_CLKREQ_N_MARK,
};
-/* - PWM0 ------------------------------------------------------------------- */
-static const unsigned int pwm0_pins[] = {
- /* PWM0 */
+/* - PWM0_A ------------------------------------------------------------------- */
+static const unsigned int pwm0_a_pins[] = {
+ /* PWM0_A */
RCAR_GP_PIN(1, 15),
};
-static const unsigned int pwm0_mux[] = {
- PWM0_MARK,
+static const unsigned int pwm0_a_mux[] = {
+ PWM0_A_MARK,
};
-/* - PWM1 ------------------------------------------------------------------- */
-static const unsigned int pwm1_pins[] = {
- /* PWM1 */
+/* - PWM1_A ------------------------------------------------------------------- */
+static const unsigned int pwm1_a_pins[] = {
+ /* PWM1_A */
+ RCAR_GP_PIN(3, 13),
+};
+static const unsigned int pwm1_a_mux[] = {
+ PWM1_A_MARK,
+};
+
+/* - PWM1_B ------------------------------------------------------------------- */
+static const unsigned int pwm1_b_pins[] = {
+ /* PWM1_B */
RCAR_GP_PIN(2, 13),
};
-static const unsigned int pwm1_mux[] = {
- PWM1_MARK,
+static const unsigned int pwm1_b_mux[] = {
+ PWM1_B_MARK,
};
-/* - PWM2 ------------------------------------------------------------------- */
-static const unsigned int pwm2_pins[] = {
- /* PWM2 */
+/* - PWM2_B ------------------------------------------------------------------- */
+static const unsigned int pwm2_b_pins[] = {
+ /* PWM2_B */
RCAR_GP_PIN(2, 14),
};
-static const unsigned int pwm2_mux[] = {
- PWM2_MARK,
+static const unsigned int pwm2_b_mux[] = {
+ PWM2_B_MARK,
};
-/* - PWM3 ------------------------------------------------------------------- */
-static const unsigned int pwm3_pins[] = {
- /* PWM3 */
+/* - PWM3_A ------------------------------------------------------------------- */
+static const unsigned int pwm3_a_pins[] = {
+ /* PWM3_A */
RCAR_GP_PIN(1, 22),
};
-static const unsigned int pwm3_mux[] = {
- PWM3_MARK,
+static const unsigned int pwm3_a_mux[] = {
+ PWM3_A_MARK,
+};
+
+/* - PWM3_B ------------------------------------------------------------------- */
+static const unsigned int pwm3_b_pins[] = {
+ /* PWM3_B */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int pwm3_b_mux[] = {
+ PWM3_B_MARK,
};
/* - PWM4 ------------------------------------------------------------------- */
@@ -2132,22 +2152,22 @@ static const unsigned int pwm7_mux[] = {
PWM7_MARK,
};
-/* - PWM8 ------------------------------------------------------------------- */
-static const unsigned int pwm8_pins[] = {
- /* PWM8 */
+/* - PWM8_A ------------------------------------------------------------------- */
+static const unsigned int pwm8_a_pins[] = {
+ /* PWM8_A */
RCAR_GP_PIN(1, 13),
};
-static const unsigned int pwm8_mux[] = {
- PWM8_MARK,
+static const unsigned int pwm8_a_mux[] = {
+ PWM8_A_MARK,
};
-/* - PWM9 ------------------------------------------------------------------- */
-static const unsigned int pwm9_pins[] = {
- /* PWM9 */
+/* - PWM9_A ------------------------------------------------------------------- */
+static const unsigned int pwm9_a_pins[] = {
+ /* PWM9_A */
RCAR_GP_PIN(1, 14),
};
-static const unsigned int pwm9_mux[] = {
- PWM9_MARK,
+static const unsigned int pwm9_a_mux[] = {
+ PWM9_A_MARK,
};
/* - QSPI0 ------------------------------------------------------------------ */
@@ -2585,16 +2605,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pcie0_clkreq_n),
SH_PFC_PIN_GROUP(pcie1_clkreq_n),
- SH_PFC_PIN_GROUP(pwm0),
- SH_PFC_PIN_GROUP(pwm1),
- SH_PFC_PIN_GROUP(pwm2),
- SH_PFC_PIN_GROUP(pwm3),
+ SH_PFC_PIN_GROUP(pwm0_a),
+ SH_PFC_PIN_GROUP(pwm1_a),
+ SH_PFC_PIN_GROUP(pwm1_b),
+ SH_PFC_PIN_GROUP(pwm2_b),
+ SH_PFC_PIN_GROUP(pwm3_a),
+ SH_PFC_PIN_GROUP(pwm3_b),
SH_PFC_PIN_GROUP(pwm4),
SH_PFC_PIN_GROUP(pwm5),
SH_PFC_PIN_GROUP(pwm6),
SH_PFC_PIN_GROUP(pwm7),
- SH_PFC_PIN_GROUP(pwm8),
- SH_PFC_PIN_GROUP(pwm9),
+ SH_PFC_PIN_GROUP(pwm8_a),
+ SH_PFC_PIN_GROUP(pwm9_a),
SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
@@ -2847,20 +2869,28 @@ static const char * const pcie_groups[] = {
"pcie1_clkreq_n",
};
-static const char * const pwm0_groups[] = {
- "pwm0",
+static const char * const pwm0_a_groups[] = {
+ "pwm0_a",
+};
+
+static const char * const pwm1_a_groups[] = {
+ "pwm1_a",
+};
+
+static const char * const pwm1_b_groups[] = {
+ "pwm1_b",
};
-static const char * const pwm1_groups[] = {
- "pwm1",
+static const char * const pwm2_b_groups[] = {
+ "pwm2_b",
};
-static const char * const pwm2_groups[] = {
- "pwm2",
+static const char * const pwm3_a_groups[] = {
+ "pwm3_a",
};
-static const char * const pwm3_groups[] = {
- "pwm3",
+static const char * const pwm3_b_groups[] = {
+ "pwm3_b",
};
static const char * const pwm4_groups[] = {
@@ -2879,12 +2909,12 @@ static const char * const pwm7_groups[] = {
"pwm7",
};
-static const char * const pwm8_groups[] = {
- "pwm8",
+static const char * const pwm8_a_groups[] = {
+ "pwm8_a",
};
-static const char * const pwm9_groups[] = {
- "pwm9",
+static const char * const pwm9_a_groups[] = {
+ "pwm9_a",
};
static const char * const qspi0_groups[] = {
@@ -3005,16 +3035,18 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(pcie),
- SH_PFC_FUNCTION(pwm0),
- SH_PFC_FUNCTION(pwm1),
- SH_PFC_FUNCTION(pwm2),
- SH_PFC_FUNCTION(pwm3),
+ SH_PFC_FUNCTION(pwm0_a),
+ SH_PFC_FUNCTION(pwm1_a),
+ SH_PFC_FUNCTION(pwm1_b),
+ SH_PFC_FUNCTION(pwm2_b),
+ SH_PFC_FUNCTION(pwm3_a),
+ SH_PFC_FUNCTION(pwm3_b),
SH_PFC_FUNCTION(pwm4),
SH_PFC_FUNCTION(pwm5),
SH_PFC_FUNCTION(pwm6),
SH_PFC_FUNCTION(pwm7),
- SH_PFC_FUNCTION(pwm8),
- SH_PFC_FUNCTION(pwm9),
+ SH_PFC_FUNCTION(pwm8_a),
+ SH_PFC_FUNCTION(pwm9_a),
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 19/21] pinctrl: renesas: r8a779g0: add missing ERROROUTC_A
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (16 preceding siblings ...)
2022-06-14 6:00 ` [PATCH v3 18/21] pinctrl: renesas: r8a779g0: add missing PWM Kuninori Morimoto
@ 2022-06-14 6:00 ` Kuninori Morimoto
2022-06-17 15:19 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 20/21] pinctrl: renesas: r8a779g0: add missing MODSELx for TSN0 Kuninori Morimoto
` (2 subsequent siblings)
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 6:00 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
This patch add missing ERROROUTC_A settings.
Current existing ERROROUTC should be _B, this patch tidyup it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index ba9489d1074c..06a1b08a3cb7 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -263,7 +263,7 @@
/* SR0 */
/* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
-#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -370,7 +370,7 @@
#define IP1SR3_15_12 FM(SD_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_19_16 FM(SD_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_23_20 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) FM(PWM1_A) FM(TCLK3_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) F_(0, 0) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP1SR3_27_24 FM(IPC_CLKOUT) FM(IPC_CLKEN_OUT) FM(ERROROUTC_A) FM(TCLK4_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1SR3_31_28 FM(QSPI0_SSL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IP2SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
@@ -765,7 +765,7 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVB2_AVTP_PPS),
/* IP0SR0 */
- PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC),
+ PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_B),
PINMUX_IPSR_GPSR(IP0SR0_3_0, TCLK2_A),
PINMUX_IPSR_GPSR(IP0SR0_7_4, MSIOF3_SS1),
@@ -1031,6 +1031,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKOUT),
PINMUX_IPSR_GPSR(IP1SR3_27_24, IPC_CLKEN_OUT),
+ PINMUX_IPSR_GPSR(IP1SR3_27_24, ERROROUTC_A),
PINMUX_IPSR_GPSR(IP1SR3_27_24, TCLK4_X),
PINMUX_IPSR_GPSR(IP1SR3_31_28, QSPI0_SSL),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 20/21] pinctrl: renesas: r8a779g0: add missing MODSELx for TSN0
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (17 preceding siblings ...)
2022-06-14 6:00 ` [PATCH v3 19/21] pinctrl: renesas: r8a779g0: add missing ERROROUTC_A Kuninori Morimoto
@ 2022-06-14 6:00 ` Kuninori Morimoto
2022-06-17 15:19 ` Geert Uytterhoeven
2022-06-14 6:01 ` [PATCH v3 21/21] pinctrl: renesas: r8a779g0: add missing MODSELx for AVBx Kuninori Morimoto
[not found] ` <87zgifkcqa.wl-kuninori.morimoto.gx@renesas.com>
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 6:00 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
TSN0 needs MODSEL4 settings.
This patch adds missing MODSELx setting for these.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index 06a1b08a3cb7..c96d95907972 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -720,27 +720,30 @@ static const u16 pinmux_data[] = {
PINMUX_SINGLE(AVS0),
PINMUX_SINGLE(PCIE1_CLKREQ_N),
PINMUX_SINGLE(PCIE0_CLKREQ_N),
+
+ /* TSN0 without MDSEL4 */
PINMUX_SINGLE(TSN0_TXCREFCLK),
- PINMUX_SINGLE(TSN0_TD2),
- PINMUX_SINGLE(TSN0_TD3),
PINMUX_SINGLE(TSN0_RD2),
PINMUX_SINGLE(TSN0_RD3),
- PINMUX_SINGLE(TSN0_TD0),
- PINMUX_SINGLE(TSN0_TD1),
PINMUX_SINGLE(TSN0_RD1),
- PINMUX_SINGLE(TSN0_TXC),
PINMUX_SINGLE(TSN0_RXC),
PINMUX_SINGLE(TSN0_RD0),
- PINMUX_SINGLE(TSN0_TX_CTL),
- PINMUX_SINGLE(TSN0_AVTP_PPS0),
PINMUX_SINGLE(TSN0_RX_CTL),
PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
- PINMUX_SINGLE(TSN0_AVTP_MATCH),
PINMUX_SINGLE(TSN0_LINK),
PINMUX_SINGLE(TSN0_PHY_INT),
- PINMUX_SINGLE(TSN0_AVTP_PPS1),
- PINMUX_SINGLE(TSN0_MDC),
PINMUX_SINGLE(TSN0_MDIO),
+ /* TSN0 with MDSEL4 */
+ PINMUX_IPSR_NOGM(0, TSN0_TD2, SEL_TSN0_TD2_1),
+ PINMUX_IPSR_NOGM(0, TSN0_TD3, SEL_TSN0_TD3_1),
+ PINMUX_IPSR_NOGM(0, TSN0_TD0, SEL_TSN0_TD0_1),
+ PINMUX_IPSR_NOGM(0, TSN0_TD1, SEL_TSN0_TD1_1),
+ PINMUX_IPSR_NOGM(0, TSN0_TXC, SEL_TSN0_TXC_1),
+ PINMUX_IPSR_NOGM(0, TSN0_TX_CTL, SEL_TSN0_TX_CTL_1),
+ PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS0, SEL_TSN0_AVTP_PPS0_1),
+ PINMUX_IPSR_NOGM(0, TSN0_AVTP_MATCH, SEL_TSN0_AVTP_MATCH_1),
+ PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1, SEL_TSN0_AVTP_PPS1_1),
+ PINMUX_IPSR_NOGM(0, TSN0_MDC, SEL_TSN0_MDC_1),
PINMUX_SINGLE(AVB2_RX_CTL),
PINMUX_SINGLE(AVB2_TX_CTL),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v3 21/21] pinctrl: renesas: r8a779g0: add missing MODSELx for AVBx
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
` (18 preceding siblings ...)
2022-06-14 6:00 ` [PATCH v3 20/21] pinctrl: renesas: r8a779g0: add missing MODSELx for TSN0 Kuninori Morimoto
@ 2022-06-14 6:01 ` Kuninori Morimoto
2022-06-17 15:19 ` Geert Uytterhoeven
[not found] ` <87zgifkcqa.wl-kuninori.morimoto.gx@renesas.com>
20 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-14 6:01 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, linux-renesas-soc, linux-gpio
From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
AVB1 needs MODSEL1, AVB2 needs MODSEL5 settings.
This patch adds missing MODSELx setting for these.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
---
drivers/pinctrl/renesas/pfc-r8a779g0.c | 58 +++++++++++++-------------
1 file changed, 30 insertions(+), 28 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c
index c96d95907972..195b0959a73b 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
@@ -745,27 +745,29 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1, SEL_TSN0_AVTP_PPS1_1),
PINMUX_IPSR_NOGM(0, TSN0_MDC, SEL_TSN0_MDC_1),
+ /* TSN0 without MDSEL5 */
PINMUX_SINGLE(AVB2_RX_CTL),
- PINMUX_SINGLE(AVB2_TX_CTL),
PINMUX_SINGLE(AVB2_RXC),
PINMUX_SINGLE(AVB2_RD0),
- PINMUX_SINGLE(AVB2_TXC),
- PINMUX_SINGLE(AVB2_TD0),
PINMUX_SINGLE(AVB2_RD1),
PINMUX_SINGLE(AVB2_RD2),
- PINMUX_SINGLE(AVB2_TD1),
- PINMUX_SINGLE(AVB2_TD2),
PINMUX_SINGLE(AVB2_MDIO),
PINMUX_SINGLE(AVB2_RD3),
- PINMUX_SINGLE(AVB2_TD3),
PINMUX_SINGLE(AVB2_TXCREFCLK),
- PINMUX_SINGLE(AVB2_MDC),
- PINMUX_SINGLE(AVB2_MAGIC),
PINMUX_SINGLE(AVB2_PHY_INT),
PINMUX_SINGLE(AVB2_LINK),
- PINMUX_SINGLE(AVB2_AVTP_MATCH),
PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
- PINMUX_SINGLE(AVB2_AVTP_PPS),
+ /* TSN0 with MDSEL5 */
+ PINMUX_IPSR_NOGM(0, AVB2_TX_CTL, SEL_AVB2_TX_CTL_1),
+ PINMUX_IPSR_NOGM(0, AVB2_TXC, SEL_AVB2_TXC_1),
+ PINMUX_IPSR_NOGM(0, AVB2_TD0, SEL_AVB2_TD0_1),
+ PINMUX_IPSR_NOGM(0, AVB2_TD1, SEL_AVB2_TD1_1),
+ PINMUX_IPSR_NOGM(0, AVB2_TD2, SEL_AVB2_TD2_1),
+ PINMUX_IPSR_NOGM(0, AVB2_TD3, SEL_AVB2_TD3_1),
+ PINMUX_IPSR_NOGM(0, AVB2_MDC, SEL_AVB2_MDC_1),
+ PINMUX_IPSR_NOGM(0, AVB2_MAGIC, SEL_AVB2_MAGIC_1),
+ PINMUX_IPSR_NOGM(0, AVB2_AVTP_MATCH, SEL_AVB2_AVTP_MATCH_1),
+ PINMUX_IPSR_NOGM(0, AVB2_AVTP_PPS, SEL_AVB2_AVTP_PPS_1),
/* IP0SR0 */
PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_B),
@@ -1060,23 +1062,23 @@ static const u16 pinmux_data[] = {
/* IP0SR6 */
PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
- PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
+ PINMUX_IPSR_MSEL(IP0SR6_7_4, AVB1_MAGIC, SEL_AVB1_MAGIC_1),
- PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
+ PINMUX_IPSR_MSEL(IP0SR6_11_8, AVB1_MDC, SEL_AVB1_MDC_1),
PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
- PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
- PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
+ PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_AVTP_MATCH, SEL_AVB1_AVTP_MATCH_1),
+ PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_MII_RX_ER, SEL_AVB1_AVTP_MATCH_0),
- PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
- PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
+ PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_TXC, SEL_AVB1_TXC_1),
+ PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_MII_TXC, SEL_AVB1_TXC_0),
- PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
- PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
+ PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_TX_CTL, SEL_AVB1_TX_CTL_1),
+ PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_MII_TX_EN, SEL_AVB1_TX_CTL_0),
/* IP1SR6 */
PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
@@ -1085,17 +1087,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
- PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
- PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
+ PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_AVTP_PPS, SEL_AVB1_AVTP_PPS_1),
+ PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_MII_COL, SEL_AVB1_AVTP_PPS_0),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
- PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
- PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
+ PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_TD1, SEL_AVB1_TD1_1),
+ PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_MII_TD1, SEL_AVB1_TD1_0),
- PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
- PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
+ PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_TD0, SEL_AVB1_TD0_1),
+ PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_MII_TD0, SEL_AVB1_TD0_0),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
@@ -1104,14 +1106,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
/* IP2SR6 */
- PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
- PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
+ PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_TD2, SEL_AVB1_TD2_1),
+ PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_MII_TD2, SEL_AVB1_TD2_0),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
- PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
- PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
+ PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_TD3, SEL_AVB1_TD3_1),
+ PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_MII_TD3, SEL_AVB1_TD3_0),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* Re: [PATCH v3 01/21] dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support
2022-06-14 5:58 ` [PATCH v3 01/21] dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support Kuninori Morimoto
@ 2022-06-17 12:30 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 12:30 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
On Tue, Jun 14, 2022 at 7:58 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> Document Pin Function Controller (PFC) support for the Renesas
> R-Car V4H (R8A779G0) SoC.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
My
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
on v2 is still valid.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 02/21] pinctrl: renesas: Add PORT_GP_CFG_13 macros
2022-06-14 5:58 ` [PATCH v3 02/21] pinctrl: renesas: Add PORT_GP_CFG_13 macros Kuninori Morimoto
@ 2022-06-17 12:30 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 12:30 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
On Tue, Jun 14, 2022 at 7:58 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> Add PORT_GP_CFG_13() and PORT_GP_13() helper macros,
> to be used by the r8a779g0 subdriver.
>
> Based on a larger patch in the BSP by LUU HOAI.
>
> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
My
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
on v2 is still valid.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 03/21] pinctrl: renesas: Initial R8A779G0 (V4H) PFC support
[not found] ` <87zgifkcqa.wl-kuninori.morimoto.gx@renesas.com>
@ 2022-06-17 15:13 ` Geert Uytterhoeven
2022-06-20 0:18 ` Kuninori Morimoto
0 siblings, 1 reply; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:13 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 7:58 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: LUU HOAI <hoai.luu.ub@renesas.com>
>
> This patch adds initial pinctrl support for the R8A779G0 (V4H) SoC,
> including bias, drive strength and voltage control.
>
> [Morimoto merged Kihara-san's MODSEL8 fixup patch,
> cleanuped white space, care reserved bit on each configs,
> fixup comments, etc]
> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +static const u16 pinmux_data[] = {
> + /* IP0SR8 */
> + PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
> + PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
These are definitely still wrong, and not fixed by any of your
subsequent patches: to enable I2C0 functionality, the corresponding
SEL_{SCL,SDA}0 bit should be set to 1, not 0.
Same for I2C[1-5] below.
> + PINMUX_IPSR_MSEL(IP0SR8_11_8, SCL1, SEL_SCL1_0),
> + PINMUX_IPSR_MSEL(IP0SR8_15_12, SDA1, SEL_SDA1_0),
> + PINMUX_IPSR_MSEL(IP0SR8_19_16, SCL2, SEL_SCL2_0),
> + PINMUX_IPSR_MSEL(IP0SR8_23_20, SDA2, SEL_SDA2_0),
> + PINMUX_IPSR_MSEL(IP0SR8_27_24, SCL3, SEL_SCL3_0),
> + PINMUX_IPSR_MSEL(IP0SR8_31_28, SDA3, SEL_SDA3_0),
> +
> + /* IP1SR8 */
> + PINMUX_IPSR_MSEL(IP1SR8_3_0, SCL4, SEL_SCL4_0),
> + PINMUX_IPSR_MSEL(IP1SR8_3_0, HRX2, SEL_SCL4_0),
> + PINMUX_IPSR_MSEL(IP1SR8_3_0, SCK4, SEL_SCL4_0),
> +
> + PINMUX_IPSR_MSEL(IP1SR8_7_4, SDA4, SEL_SDA4_0),
> + PINMUX_IPSR_MSEL(IP1SR8_7_4, HTX2, SEL_SDA4_0),
> + PINMUX_IPSR_MSEL(IP1SR8_7_4, CTS4_N, SEL_SDA4_0),
> +
> + PINMUX_IPSR_MSEL(IP1SR8_11_8, SCL5, SEL_SCL5_0),
> + PINMUX_IPSR_MSEL(IP1SR8_11_8, HRTS2_N, SEL_SCL5_0),
> + PINMUX_IPSR_MSEL(IP1SR8_11_8, RTS4_N, SEL_SCL5_0),
> +
> + PINMUX_IPSR_MSEL(IP1SR8_15_12, SDA5, SEL_SDA5_0),
> + PINMUX_IPSR_MSEL(IP1SR8_15_12, SCIF_CLK2, SEL_SDA5_0),
> +
> + PINMUX_IPSR_GPSR(IP1SR8_19_16, HCTS2_N),
> + PINMUX_IPSR_GPSR(IP1SR8_19_16, TX4),
> +
> + PINMUX_IPSR_GPSR(IP1SR8_23_20, HSCK2),
> + PINMUX_IPSR_GPSR(IP1SR8_23_20, RX4),
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 04/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions
2022-06-14 5:58 ` [PATCH v3 04/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
@ 2022-06-17 15:15 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:15 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 7:58 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Phong Hoang <phong.hoang.wz@renesas.com>
>
> This patch adds SCIF, I2C, EthernetAVB, HSCIF, MMC, QSPI,
> MSIOF, PWM, CAN-FD, Ethernet-TSN, PCIe pins, groups, and functions
>
> [Morimoto merged above patches into one, cleanup white space,
> sort modules alphabetically, fixup comments]
> Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
> Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
> Signed-off-by: CongDang <cong.dang.xn@renesas.com>
> Signed-off-by: Kazuya Mizuguch <kazuya.mizuguchi.ks@renesas.com>
> Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +/* - SCIF0 ------------------------------------------------------------------ */
> +static const unsigned int scif0_data_pins[] = {
> + /* RX0, TX0 */
> + RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
> +};
> +static const unsigned int scif0_data_mux[] = {
> + RX0_MARK, TX0_MARK,
> +};
> +static const unsigned int scif0_clk_pins[] = {
> + /* SCK0 */
> + RCAR_GP_PIN(1, 15),
> +};
> +static const unsigned int scif0_clk_mux[] = {
> + SCK0_MARK,
> +};
> +static const unsigned int scif0_ctrl_pins[] = {
> + /* RTS0#, CTS0# */
> + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
> +};
> +static const unsigned int scif0_ctrl_mux[] = {
> + RTS0_N_MARK, CTS0_N_MARK,
> +};
> +
> +/* - SCIF1 ------------------------------------------------------------------ */
> +static const unsigned int scif1_data_pins[] = {
> + /* RX1, TX1 */
> + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
> +};
> +static const unsigned int scif1_data_mux[] = {
> + RX1_MARK, TX1_MARK,
> +};
> +static const unsigned int scif1_clk_pins[] = {
> + /* SCK1 */
> + RCAR_GP_PIN(0, 18),
> +};
> +static const unsigned int scif1_clk_mux[] = {
> + SCK1_MARK,
> +};
> +static const unsigned int scif1_ctrl_pins[] = {
> + /* RTS1_N, CTS1_N */
Compared to v2, you changed:
-+ /* RTS1#, CTS1# */
++ /* RTS1_N, CTS1_N */
(same for SCIF3).
While this makes sense, as all but the *_pins[] comments use "_N"
instead of "#", it does make SCIF1/SCIF3 inconsistent with the other
(H)SCIF ports, here and in later patches.
> + RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
> +};
> +static const unsigned int scif1_ctrl_mux[] = {
> + RTS1_N_MARK, CTS1_N_MARK,
> +};
> +
> +/* - SCIF3 ------------------------------------------------------------------ */
> +static const unsigned int scif3_data_pins[] = {
> + /* RX3, TX3 */
> + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
> +};
> +static const unsigned int scif3_data_mux[] = {
> + RX3_MARK, TX3_MARK,
> +};
> +static const unsigned int scif3_clk_pins[] = {
> + /* SCK3 */
> + RCAR_GP_PIN(1, 4),
> +};
> +static const unsigned int scif3_clk_mux[] = {
> + SCK3_MARK,
> +};
> +static const unsigned int scif3_ctrl_pins[] = {
> + /* RTS3_N, CTS3_N */
> + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
> +};
> +static const unsigned int scif3_ctrl_mux[] = {
> + RTS3_N_MARK, CTS3_N_MARK,
> +};
> +
> +/* - SCIF4 ------------------------------------------------------------------ */
> +static const unsigned int scif4_data_pins[] = {
> + /* RX4, TX4 */
> + RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
> +};
> +static const unsigned int scif4_data_mux[] = {
> + RX4_MARK, TX4_MARK,
> +};
> +static const unsigned int scif4_clk_pins[] = {
> + /* SCK4 */
> + RCAR_GP_PIN(8, 8),
> +};
> +static const unsigned int scif4_clk_mux[] = {
> + SCK4_MARK,
> +};
> +static const unsigned int scif4_ctrl_pins[] = {
> + /* RTS4#, CTS4# */
> + RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
> +};
> +static const unsigned int scif4_ctrl_mux[] = {
> + RTS4_N_MARK, CTS4_N_MARK,
> +};
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 05/21] pinctrl: renesas: r8a779g0: remove not used NOGP definitions
2022-06-14 5:59 ` [PATCH v3 05/21] pinctrl: renesas: r8a779g0: remove not used NOGP definitions Kuninori Morimoto
@ 2022-06-17 15:16 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:16 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 7:59 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> Current V4H PFC code has many NOGP definitions. But these are not used,
> and it is different from original usage. This patch removes these.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -43,22 +43,6 @@
> PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \
> PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33)
>
> -#define CPU_ALL_NOGP(fn) \
> - PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
> - PIN_NOGP_CFG(PRESETOUT0_N, "PRESETOUT0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
> - PIN_NOGP_CFG(PRESETOUT1_N, "PRESETOUT1#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
> - PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
> - PIN_NOGP_CFG(DCUTRST0_N, "DCUTRST0#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
> - PIN_NOGP_CFG(DCUTCK0, "DCUTCK0", fn, SH_PFC_PIN_CFG_PULL_UP), \
> - PIN_NOGP_CFG(DCUTMS0, "DCUTMS0", fn, SH_PFC_PIN_CFG_PULL_UP), \
> - PIN_NOGP_CFG(DCUTDI0, "DCUTDI0", fn, SH_PFC_PIN_CFG_PULL_UP), \
> - PIN_NOGP_CFG(DCUTRST1_N, "DCUTRST1#", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
> - PIN_NOGP_CFG(DCUTCK1, "DCUTCK1", fn, SH_PFC_PIN_CFG_PULL_UP), \
> - PIN_NOGP_CFG(DCUTMS1, "DCUTMS1", fn, SH_PFC_PIN_CFG_PULL_UP), \
> - PIN_NOGP_CFG(DCUTDI1, "DCUTDI1", fn, SH_PFC_PIN_CFG_PULL_UP), \
> - PIN_NOGP_CFG(EVTI_N, "EVTI#", fn, SH_PFC_PIN_CFG_PULL_UP), \
> - PIN_NOGP_CFG(MSYN_N, "MSYN#", fn, SH_PFC_PIN_CFG_PULL_UP)
As several of the NOGP definitions are wrong, I prefer to never
include them.
> -
> /* GPSR0 */
> #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8)
> #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4)
> @@ -1204,7 +1188,6 @@ static const u16 pinmux_data[] = {
> */
> enum {
> GP_ASSIGN_LAST(),
> - NOGP_ALL(),
> };
>
> static const struct sh_pfc_pin pinmux_pins[] = {
As the definitions are not used anyway, and don't have any impact on
other enums (they're last in the list), I think it is safe to fold
this into "[PATCH v3 03/21] pinctrl: renesas: Initial R8A779G0 (V4H)
PFC support".
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 06/21] pinctrl: renesas: r8a779g0: remove not used IPxSRx definitions
2022-06-14 5:59 ` [PATCH v3 06/21] pinctrl: renesas: r8a779g0: remove not used IPxSRx definitions Kuninori Morimoto
@ 2022-06-17 15:17 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:17 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 7:59 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> Current V4H PFC code has many IPxSRx definitions with all 0.
> But these have no meaning. This patch removes these.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
As the only net impact of this patch is the removal of several enums,
and a shift in the numbering of later (internal) enums, I think
it is safe to fold this into "[PATCH v3 03/21] pinctrl: renesas:
Initial R8A779G0 (V4H) PFC support".
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 07/21] pinctrl: renesas: r8a779g0: remove not used MOD_SELx definitions
2022-06-14 5:59 ` [PATCH v3 07/21] pinctrl: renesas: r8a779g0: remove not used MOD_SELx definitions Kuninori Morimoto
@ 2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-21 0:12 ` Kuninori Morimoto
0 siblings, 1 reply; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:17 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
Thanks for your patch!
On Tue, Jun 14, 2022 at 7:59 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> Current V4H PFC code has many MOD_SELx definitions with all 0.
> But these have no meaning. This patch removes these, but keep
> its definition to avoid unreadable PINMUX_MOD_SELS.
You can just replace them with blanks, keeping the structure of the
PINMUX_MOD_SELS table alive.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Again, as the only net impact of this patch is the removal of several
enums, and a shift in the numbering of later (internal) enums, I think
it is safe to fold this into "[PATCH v3 03/21] pinctrl: renesas:
Initial R8A779G0 (V4H) PFC support".
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X
2022-06-14 5:59 ` [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X Kuninori Morimoto
@ 2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-29 1:26 ` Kuninori Morimoto
0 siblings, 1 reply; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:17 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 7:59 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X
>
> Because Document has 2xTCLK3/TCLK4 with no suffix (_A, _B),
> this patch name it as _X.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
LGTM, but as the suffixes become part of the DT ABI when defining
pin groups, we should get the conflicts resolved, and this cannot
be applied as-is.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 08/21] pinctrl: renesas: r8a779g0: tidyup ioctrl_regs
2022-06-14 5:59 ` [PATCH v3 08/21] pinctrl: renesas: r8a779g0: tidyup ioctrl_regs Kuninori Morimoto
@ 2022-06-17 15:17 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:17 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 7:59 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch comment out POC2 which is not used/documented,
> and remove TD0SEL3 which is no need to have.
>
> Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -3657,27 +3657,25 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
> enum ioctrl_regs {
> POC0,
> POC1,
> - POC2,
> +/* POC2, is not used */
Please drop it completely, as POC2 is not documented to exist at all
(unlike TD0SEL3).
> POC3,
> POC4,
> POC5,
> POC6,
> POC7,
> POC8,
> - TD0SEL3,
> };
>
> static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
> [POC0] = { 0xE60500A0, },
> [POC1] = { 0xE60508A0, },
> - [POC2] = { 0xE60580A0, },
> +/* [POC2] = { 0xE60580A0, }, is not used */
> [POC3] = { 0xE60588A0, },
> [POC4] = { 0xE60600A0, },
> [POC5] = { 0xE60608A0, },
> [POC6] = { 0xE60610A0, },
> [POC7] = { 0xE60618A0, },
> [POC8] = { 0xE60680A0, },
> - [TD0SEL3] = { 0xE60589C0, },
> { /* sentinel */ },
> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 10/21] pinctrl: renesas: r8a779g0: add missing IRQx_A/IRQx_B
2022-06-14 5:59 ` [PATCH v3 10/21] pinctrl: renesas: r8a779g0: add missing IRQx_A/IRQx_B Kuninori Morimoto
@ 2022-06-17 15:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:18 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 7:59 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch adds missing IRQx_A/IRQx_B
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -278,7 +278,7 @@
> #define IP1SR0_11_8 FM(MSIOF5_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR0_15_12 FM(MSIOF5_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR0_19_16 FM(MSIOF5_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP1SR0_23_20 FM(MSIOF2_SS2) FM(TCLK1) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR0_27_24 FM(MSIOF2_SS1) FM(HTX1) FM(TX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR0_31_28 FM(MSIOF2_SYNC) FM(HRX1) FM(RX1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>
> @@ -313,10 +313,10 @@
> #define IP2SR1_7_4 FM(SCIF_CLK) FM(IRQ4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
"IRQ4" here should be "IRQ4_A", also in the corresponding
PINMUX_IPSR_GPSR() definition. Probably this should be fixed in
"[PATCH v3 03/21] pinctrl: renesas: Initial R8A779G0 (V4H) PFC
support"?
The rest LGTM, as it matches the documentation, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
However, given the inconsistent naming of pins for IRQs with two
possible pin alternatives:
- IRQ2 and IRQ2_A,
- IRQ3 and IRQ3_B,
- IRQ4_A and IRQ4_B,
I expect several of these to be renamed in future revisions of the
documentation. As these names become part of the DT ABI when defining
pin groups, that happens sooner rather than later...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 11/21] pinctrl: renesas: r8a779g0: add missing HSCIF3_A
2022-06-14 5:59 ` [PATCH v3 11/21] pinctrl: renesas: r8a779g0: add missing HSCIF3_A Kuninori Morimoto
@ 2022-06-17 15:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:18 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 7:59 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch adds missing HSCIF3_A
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -289,11 +289,11 @@
>
> /* SR1 */
> /* IP0SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
> -#define IP0SR1_3_0 FM(MSIOF1_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP0SR1_7_4 FM(MSIOF1_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP0SR1_11_8 FM(MSIOF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP0SR1_15_12 FM(MSIOF1_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP0SR1_19_16 FM(MSIOF1_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP0SR1_3_0 FM(MSIOF1_SS2) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP0SR1_7_4 FM(MSIOF1_SS1) FM(HCTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
HCTS3_N_A
> +#define IP0SR1_11_8 FM(MSIOF1_SYNC) FM(HRTS3_A_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
HRTS3_N_A
> +#define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP0SR1_27_24 FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP0SR1_31_28 FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> @@ -824,10 +824,20 @@ static const u16 pinmux_data[] = {
>
> /* IP0SR1 */
> PINMUX_IPSR_GPSR(IP0SR1_3_0, MSIOF1_SS2),
> + PINMUX_IPSR_GPSR(IP0SR1_3_0, HTX3_A),
> +
> PINMUX_IPSR_GPSR(IP0SR1_7_4, MSIOF1_SS1),
> + PINMUX_IPSR_GPSR(IP0SR1_7_4, HCTS3_A_N),
HCTS3_N_A
> +
> PINMUX_IPSR_GPSR(IP0SR1_11_8, MSIOF1_SYNC),
> + PINMUX_IPSR_GPSR(IP0SR1_11_8, HRTS3_A_N),
HRTS3_N_A
> +
> PINMUX_IPSR_GPSR(IP0SR1_15_12, MSIOF1_SCK),
> + PINMUX_IPSR_GPSR(IP0SR1_15_12, HSCK3_A),
> +
> PINMUX_IPSR_GPSR(IP0SR1_19_16, MSIOF1_TXD),
> + PINMUX_IPSR_GPSR(IP0SR1_19_16, HRX3_A),
> +
> PINMUX_IPSR_GPSR(IP0SR1_23_20, MSIOF1_RXD),
> PINMUX_IPSR_GPSR(IP0SR1_27_24, MSIOF0_SS2),
> PINMUX_IPSR_GPSR(IP0SR1_31_28, MSIOF0_SS1),
> @@ -1590,6 +1600,29 @@ static const unsigned int hscif3_ctrl_mux[] = {
> HRTS3_N_MARK, HCTS3_N_MARK,
> };
>
> +/* - HSCIF3_A ----------------------------------------------------------------- */
> +static const unsigned int hscif3_a_data_pins[] = {
The "_a" suffix should be at the end of the name,
i.e. "hscif3_data_a_pins"
(Looks like we do have a few exception: ssi[78]*_[bc]_(data|ctrl)
in pfc-r8a7790.c).
> + /* HRX3, HTX3 */
> + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
> +};
> +static const unsigned int hscif3_a_data_mux[] = {
hscif3_data_a_mux
> + HRX3_A_MARK, HTX3_A_MARK,
> +};
> +static const unsigned int hscif3_a_clk_pins[] = {
hscif3_clk_a_pins
> + /* HSCK3 */
> + RCAR_GP_PIN(1, 3),
> +};
> +static const unsigned int hscif3_a_clk_mux[] = {
hscif3_clk_a_mux
> + HSCK3_A_MARK,
> +};
> +static const unsigned int hscif3_a_ctrl_pins[] = {
hscif3_ctrl_a_pins
> + /* HRTS3#, HCTS3# */
> + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
> +};
> +static const unsigned int hscif3_a_ctrl_mux[] = {
hscif3_ctrl_a_mux
> + HRTS3_A_N_MARK, HCTS3_A_N_MARK,
HRTS3_N_A_MARK, HCTS3_N_A_MARK
> +};
> +
> /* - I2C0 ------------------------------------------------------------------- */
> static const unsigned int i2c0_pins[] = {
> /* SDA0, SCL0 */
> @@ -2351,6 +2384,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
> SH_PFC_PIN_GROUP(hscif3_data),
> SH_PFC_PIN_GROUP(hscif3_clk),
> SH_PFC_PIN_GROUP(hscif3_ctrl),
> + SH_PFC_PIN_GROUP(hscif3_a_data),
hscif3_data_a
> + SH_PFC_PIN_GROUP(hscif3_a_clk),
hscif3_clk_a
> + SH_PFC_PIN_GROUP(hscif3_a_ctrl),
hscif3_ctrl_a
>
> SH_PFC_PIN_GROUP(i2c0),
> SH_PFC_PIN_GROUP(i2c1),
> @@ -2555,6 +2591,12 @@ static const char * const hscif3_groups[] = {
> "hscif3_ctrl",
> };
>
> +static const char * const hscif3_a_groups[] = {
> + "hscif3_a_data",
hscif3_data_a
> + "hscif3_a_clk",
hscif3_clk_a
> + "hscif3_a_ctrl",
hscif3_ctrl_a
> +};
> +
> static const char * const i2c0_groups[] = {
> "i2c0",
> };
> @@ -2765,6 +2807,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
> SH_PFC_FUNCTION(hscif1),
> SH_PFC_FUNCTION(hscif2),
> SH_PFC_FUNCTION(hscif3),
> + SH_PFC_FUNCTION(hscif3_a),
Please drop this. Functions don't need alternatives.
>
> SH_PFC_FUNCTION(i2c0),
> SH_PFC_FUNCTION(i2c1),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 12/21] pinctrl: renesas: r8a779g0: add missing HSCIF1_X
2022-06-14 5:59 ` [PATCH v3 12/21] pinctrl: renesas: r8a779g0: add missing HSCIF1_X Kuninori Morimoto
@ 2022-06-17 15:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:18 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 7:59 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch adds missing HSCIF1.
> Because Document has 2xHSCIF1 with no suffix (_A, _B),
> this patch name it as _X.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -1554,6 +1561,29 @@ static const unsigned int hscif1_ctrl_mux[] = {
> HRTS1_N_MARK, HCTS1_N_MARK,
> };
>
> +/* - HSCIF1_X---------------------------------------------------------------- */
> +static const unsigned int hscif1_x_data_pins[] = {
hscif1_data_x_pins etc.
> + /* HRX1_X, HTX1_X */
> + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
> +};
> @@ -2805,6 +2844,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
>
> SH_PFC_FUNCTION(hscif0),
> SH_PFC_FUNCTION(hscif1),
> + SH_PFC_FUNCTION(hscif1_x),
Please drop this.
> SH_PFC_FUNCTION(hscif2),
> SH_PFC_FUNCTION(hscif3),
> SH_PFC_FUNCTION(hscif3_a),
Again, as the pin group names are part of the DT ABI, this cannot be
applied as-is, and we have to wait for clarification of the suffixes.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 13/21] pinctrl: renesas: r8a779g0: add missing SCIF3
2022-06-14 6:00 ` [PATCH v3 13/21] pinctrl: renesas: r8a779g0: add missing SCIF3 Kuninori Morimoto
@ 2022-06-17 15:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:18 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
> Exising SCIF3 settings on IP3SR1 should be SCIF3_A,
> and existing settings on scif3_xxx[] are for SCIF3.
>
> This patch add missing SCIF3 settings on IP0SR1,
> rename IP3SR1 settings to SCIF3_A,
> add missing scif3_a_xxx[].
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -319,11 +319,11 @@
> #define IP2SR1_31_28 F_(0, 0) FM(TCLK2) FM(MSIOF4_SS1) FM(IRQ3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>
> /* IP3SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
> -#define IP3SR1_3_0 FM(HRX3) FM(SCK3) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP3SR1_19_16 FM(HTX3) FM(TX3) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP3SR1_3_0 FM(HRX3) FM(SCK3_A) FM(MSIOF4_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP3SR1_7_4 FM(HSCK3) FM(CTS3_A_N) FM(MSIOF4_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
CTS3_N_A (everywhere)
> +#define IP3SR1_11_8 FM(HRTS3_N) FM(RTS3_A_N) FM(MSIOF4_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
RTS3_N_A (everywhere)
> +#define IP3SR1_15_12 FM(HCTS3_N) FM(RX3_A) FM(MSIOF4_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP3SR1_19_16 FM(HTX3) FM(TX3_A) FM(MSIOF4_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
I think this part belongs in "[PATCH v3 03/21] pinctrl: renesas:
Initial R8A779G0 (V4H) PFC support", as it is a bug in that patch.
>
> /* SR2 */
> /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
> @@ -901,23 +906,23 @@ static const u16 pinmux_data[] = {
>
> /* IP3SR1 */
> PINMUX_IPSR_GPSR(IP3SR1_3_0, HRX3),
> - PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3),
> + PINMUX_IPSR_GPSR(IP3SR1_3_0, SCK3_A),
> PINMUX_IPSR_GPSR(IP3SR1_3_0, MSIOF4_SS2),
>
> PINMUX_IPSR_GPSR(IP3SR1_7_4, HSCK3),
> - PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_N),
> + PINMUX_IPSR_GPSR(IP3SR1_7_4, CTS3_A_N),
> PINMUX_IPSR_GPSR(IP3SR1_7_4, MSIOF4_SCK),
>
> PINMUX_IPSR_GPSR(IP3SR1_11_8, HRTS3_N),
> - PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_N),
> + PINMUX_IPSR_GPSR(IP3SR1_11_8, RTS3_A_N),
> PINMUX_IPSR_GPSR(IP3SR1_11_8, MSIOF4_TXD),
>
> PINMUX_IPSR_GPSR(IP3SR1_15_12, HCTS3_N),
> - PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3),
> + PINMUX_IPSR_GPSR(IP3SR1_15_12, RX3_A),
> PINMUX_IPSR_GPSR(IP3SR1_15_12, MSIOF4_RXD),
>
> PINMUX_IPSR_GPSR(IP3SR1_19_16, HTX3),
> - PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3),
> + PINMUX_IPSR_GPSR(IP3SR1_19_16, TX3_A),
> PINMUX_IPSR_GPSR(IP3SR1_19_16, MSIOF4_SYNC),
I think this part belongs in "[PATCH v3 03/21] pinctrl: renesas:
Initial R8A779G0 (V4H) PFC support", as it is a bug in that patch.
>
> /* IP0SR2 */
> @@ -2228,6 +2233,29 @@ static const unsigned int scif3_ctrl_mux[] = {
> RTS3_N_MARK, CTS3_N_MARK,
> };
>
> +/* - SCIF3_A ------------------------------------------------------------------ */
> +static const unsigned int scif3_a_data_pins[] = {
scif3_data_a_pins etc.
> + /* RX3_A, TX3_A */
> + RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
> +};
> @@ -2884,6 +2921,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
> SH_PFC_FUNCTION(scif0),
> SH_PFC_FUNCTION(scif1),
> SH_PFC_FUNCTION(scif3),
> + SH_PFC_FUNCTION(scif3_a),
Please drop this, as it is not needed.
> SH_PFC_FUNCTION(scif4),
> SH_PFC_FUNCTION(scif_clk),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 14/21] pinctrl: renesas: r8a779g0: add missing SCIF1_X
2022-06-14 6:00 ` [PATCH v3 14/21] pinctrl: renesas: r8a779g0: add missing SCIF1_X Kuninori Morimoto
@ 2022-06-17 15:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:18 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch adds missing SCIF1_X.
> Because Document has 2xSCIF1 with no suffix (_A, _B),
> this patch name it as _X.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -295,13 +295,13 @@
> #define IP0SR1_15_12 FM(MSIOF1_SCK) FM(HSCK3_A) FM(CTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP0SR1_19_16 FM(MSIOF1_TXD) FM(HRX3_A) FM(SCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP0SR1_23_20 FM(MSIOF1_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP0SR1_27_24 FM(MSIOF0_SS2) FM(HTX1_X) FM(TX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>
> /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
> -#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_X_N) FM(CTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
CTS1_N_X (everywhere)
> +#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_X_N) FM(RTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
RTS1_N_X (everywhere)
> +#define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> @@ -2210,6 +2215,29 @@ static const unsigned int scif1_ctrl_mux[] = {
> RTS1_N_MARK, CTS1_N_MARK,
> };
>
> +/* - SCIF1_X ------------------------------------------------------------------ */
> +static const unsigned int scif1_x_data_pins[] = {
scif1_data_x_pins etc.
> + /* RX1_X, TX1_X */
> + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
> +};
> @@ -2920,6 +2957,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
>
> SH_PFC_FUNCTION(scif0),
> SH_PFC_FUNCTION(scif1),
> + SH_PFC_FUNCTION(scif1_x),
Please drop this, as it is not needed.
> SH_PFC_FUNCTION(scif3),
> SH_PFC_FUNCTION(scif3_a),
> SH_PFC_FUNCTION(scif4),
Again, as the pin group names are part of the DT ABI, this cannot be
applied as-is, and we have to wait for clarification of the suffixes.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 15/21] pinctrl: renesas: r8a779g0: add missing CANFD5_B
2022-06-14 6:00 ` [PATCH v3 15/21] pinctrl: renesas: r8a779g0: add missing CANFD5_B Kuninori Morimoto
@ 2022-06-17 15:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:18 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch adds missing CANFD5_B
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -299,8 +299,8 @@
> #define IP0SR1_31_28 FM(MSIOF0_SS1) FM(HRX1_X) FM(RX1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
>
> /* IP1SR1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
> -#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_X_N) FM(CTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_X_N) FM(RTS1_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP1SR1_3_0 FM(MSIOF0_SYNC) FM(HCTS1_X_N) FM(CTS1_X_N) FM(CANFD5_B_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
CANFD5_TX_B (everywhere)
> +#define IP1SR1_7_4 FM(MSIOF0_TXD) FM(HRTS1_X_N) FM(RTS1_X_N) FM(CANFD5_B_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
CANFD5_RX_B (everywhere)
> #define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> @@ -1498,6 +1500,15 @@ static const unsigned int canfd5_data_mux[] = {
> CANFD5_TX_MARK, CANFD5_RX_MARK,
> };
>
> +/* - CANFD5_B ----------------------------------------------------------------- */
> +static const unsigned int canfd5_b_data_pins[] = {
canfd5_data_b_pins etc.
> + /* CANFD5_B_TX, CANFD5_B_RX */
> + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
> +};
> @@ -2912,6 +2928,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
> SH_PFC_FUNCTION(canfd3),
> SH_PFC_FUNCTION(canfd4),
> SH_PFC_FUNCTION(canfd5),
> + SH_PFC_FUNCTION(canfd5_b),
Please drop this, as it is not needed.
> SH_PFC_FUNCTION(canfd6),
> SH_PFC_FUNCTION(canfd7),
> SH_PFC_FUNCTION(can_clk),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 16/21] pinctrl: renesas: r8a779g0: add missing TPU0TOx_A
2022-06-14 6:00 ` [PATCH v3 16/21] pinctrl: renesas: r8a779g0: add missing TPU0TOx_A Kuninori Morimoto
@ 2022-06-17 15:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:18 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch adds missing TPU0TOx_A
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -2906,6 +2944,13 @@ static const char * const tpu_groups[] = {
> "tpu_to3",
> };
>
> +static const char * const tpu_a_groups[] = {
> + "tpu_to0_a",
> + "tpu_to1_a",
> + "tpu_to2_a",
> + "tpu_to3_a",
Please add these to the existing tpu_groups[] instead.
> +};
> +
> static const char * const tsn0_groups[] = {
> "tsn0_link",
> "tsn0_phy_int",
> @@ -2981,6 +3026,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
> SH_PFC_FUNCTION(scif_clk),
>
> SH_PFC_FUNCTION(tpu),
> + SH_PFC_FUNCTION(tpu_a),
Please drop this, as it is not needed.
>
> SH_PFC_FUNCTION(tsn0),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 17/21] pinctrl: renesas: r8a779g0: add missing FlaxRay
2022-06-14 6:00 ` [PATCH v3 17/21] pinctrl: renesas: r8a779g0: add missing FlaxRay Kuninori Morimoto
@ 2022-06-17 15:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:18 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
Thanks for your patch!
On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch adds missing FlaxRay pins.
FlexRay (also in the subject).
> Because Document has 2xFXR_TXENA/B pin with no suffix (_A, _B),
> this patch name it as _X.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -338,8 +338,8 @@
>
> /* IP1SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
> #define IP1SR2_3_0 FM(TPU0TO0) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP1SR2_7_4 FM(CAN_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP1SR2_11_8 FM(CANFD0_TX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
FXR_TXENA_N_X (everywhere)
> +#define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_X_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
FXR_TXENB_N_X (everywhere)
> #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2) F_(0, 0) FM(TCLK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) FM(TCLK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Again, as the suffixes become part of the DT ABI when defining pin
groups, we should get the conflicts resolved, and this cannot be
applied as-is.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 18/21] pinctrl: renesas: r8a779g0: add missing PWM
2022-06-14 6:00 ` [PATCH v3 18/21] pinctrl: renesas: r8a779g0: add missing PWM Kuninori Morimoto
@ 2022-06-17 15:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:19 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed.
> This patch add missing PWM settings, and tidyup these.
>
> According to Document, GP3_14 Function4 is PWM2_A,
> but we can't select it at P1SR3[27:24].
> This patch just ignore it for now.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -304,9 +304,9 @@
> #define IP1SR1_11_8 FM(MSIOF0_SCK) FM(HSCK1_X) FM(SCK1_X) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR1_15_12 FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP1SR1_19_16 FM(HTX0) FM(TX0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> -#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP1SR1_23_20 FM(HCTS0_N) FM(CTS0_N) FM(PWM8_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP1SR1_27_24 FM(HRTS0_N) FM(RTS0_N) FM(PWM9_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP1SR1_31_28 FM(HSCK0) FM(SCK0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
I think all renames belong in "[PATCH v3 03/21] pinctrl: renesas:
Initial R8A779G0 (V4H) PFC support", as it is a bug in that patch.
> @@ -2847,20 +2869,28 @@ static const char * const pcie_groups[] = {
> "pcie1_clkreq_n",
> };
>
> -static const char * const pwm0_groups[] = {
> - "pwm0",
> +static const char * const pwm0_a_groups[] = {
> + "pwm0_a",
> +};
> +
> +static const char * const pwm1_a_groups[] = {
> + "pwm1_a",
> +};
> +
> +static const char * const pwm1_b_groups[] = {
> + "pwm1_b",
> };
Please have a single pwm1_groups[], containing both "pwm1_a" and
"pwm1_b". Same for the other groups.
> @@ -3005,16 +3035,18 @@ static const struct sh_pfc_function pinmux_functions[] = {
>
> SH_PFC_FUNCTION(pcie),
>
> - SH_PFC_FUNCTION(pwm0),
> - SH_PFC_FUNCTION(pwm1),
> - SH_PFC_FUNCTION(pwm2),
> - SH_PFC_FUNCTION(pwm3),
> + SH_PFC_FUNCTION(pwm0_a),
> + SH_PFC_FUNCTION(pwm1_a),
> + SH_PFC_FUNCTION(pwm1_b),
> + SH_PFC_FUNCTION(pwm2_b),
> + SH_PFC_FUNCTION(pwm3_a),
> + SH_PFC_FUNCTION(pwm3_b),
> SH_PFC_FUNCTION(pwm4),
> SH_PFC_FUNCTION(pwm5),
> SH_PFC_FUNCTION(pwm6),
> SH_PFC_FUNCTION(pwm7),
> - SH_PFC_FUNCTION(pwm8),
> - SH_PFC_FUNCTION(pwm9),
> + SH_PFC_FUNCTION(pwm8_a),
> + SH_PFC_FUNCTION(pwm9_a),
Please drop these changes, as they are not needed.
>
> SH_PFC_FUNCTION(qspi0),
> SH_PFC_FUNCTION(qspi1),
However, given the inconsistent naming of pins for PWMs that are
available on a single pin (PWM[08]_A vs. PWM[4-7]), I expect several
of these to be renamed in future revisions of the documentation.
As pin group names are part of the DT ABI, that should happen sooner
rather than later...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 19/21] pinctrl: renesas: r8a779g0: add missing ERROROUTC_A
2022-06-14 6:00 ` [PATCH v3 19/21] pinctrl: renesas: r8a779g0: add missing ERROROUTC_A Kuninori Morimoto
@ 2022-06-17 15:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:19 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> This patch add missing ERROROUTC_A settings.
> Current existing ERROROUTC should be _B, this patch tidyup it.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -263,7 +263,7 @@
>
> /* SR0 */
> /* IP0SR0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */
> -#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> +#define IP0SR0_3_0 F_(0, 0) FM(ERROROUTC_B) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
I think the rename belongs in "[PATCH v3 03/21] pinctrl: renesas:
Initial R8A779G0 (V4H) PFC support", as it is a bug in that patch.
> #define IP0SR0_7_4 F_(0, 0) FM(MSIOF3_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP0SR0_11_8 F_(0, 0) FM(MSIOF3_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
> #define IP0SR0_15_12 FM(IRQ3) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
The rest LGTM, as it matches the documentation, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 20/21] pinctrl: renesas: r8a779g0: add missing MODSELx for TSN0
2022-06-14 6:00 ` [PATCH v3 20/21] pinctrl: renesas: r8a779g0: add missing MODSELx for TSN0 Kuninori Morimoto
@ 2022-06-17 15:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:19 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 14, 2022 at 8:00 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> TSN0 needs MODSEL4 settings.
> This patch adds missing MODSELx setting for these.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Thanks for your patch!
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -720,27 +720,30 @@ static const u16 pinmux_data[] = {
> PINMUX_SINGLE(AVS0),
> PINMUX_SINGLE(PCIE1_CLKREQ_N),
> PINMUX_SINGLE(PCIE0_CLKREQ_N),
> +
> + /* TSN0 without MDSEL4 */
MODSEL4
> PINMUX_SINGLE(TSN0_TXCREFCLK),
> - PINMUX_SINGLE(TSN0_TD2),
> - PINMUX_SINGLE(TSN0_TD3),
> PINMUX_SINGLE(TSN0_RD2),
> PINMUX_SINGLE(TSN0_RD3),
> - PINMUX_SINGLE(TSN0_TD0),
> - PINMUX_SINGLE(TSN0_TD1),
> PINMUX_SINGLE(TSN0_RD1),
> - PINMUX_SINGLE(TSN0_TXC),
> PINMUX_SINGLE(TSN0_RXC),
> PINMUX_SINGLE(TSN0_RD0),
> - PINMUX_SINGLE(TSN0_TX_CTL),
> - PINMUX_SINGLE(TSN0_AVTP_PPS0),
> PINMUX_SINGLE(TSN0_RX_CTL),
> PINMUX_SINGLE(TSN0_AVTP_CAPTURE),
> - PINMUX_SINGLE(TSN0_AVTP_MATCH),
> PINMUX_SINGLE(TSN0_LINK),
> PINMUX_SINGLE(TSN0_PHY_INT),
> - PINMUX_SINGLE(TSN0_AVTP_PPS1),
> - PINMUX_SINGLE(TSN0_MDC),
> PINMUX_SINGLE(TSN0_MDIO),
> + /* TSN0 with MDSEL4 */
MODSEL4
> + PINMUX_IPSR_NOGM(0, TSN0_TD2, SEL_TSN0_TD2_1),
> + PINMUX_IPSR_NOGM(0, TSN0_TD3, SEL_TSN0_TD3_1),
> + PINMUX_IPSR_NOGM(0, TSN0_TD0, SEL_TSN0_TD0_1),
> + PINMUX_IPSR_NOGM(0, TSN0_TD1, SEL_TSN0_TD1_1),
> + PINMUX_IPSR_NOGM(0, TSN0_TXC, SEL_TSN0_TXC_1),
> + PINMUX_IPSR_NOGM(0, TSN0_TX_CTL, SEL_TSN0_TX_CTL_1),
> + PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS0, SEL_TSN0_AVTP_PPS0_1),
> + PINMUX_IPSR_NOGM(0, TSN0_AVTP_MATCH, SEL_TSN0_AVTP_MATCH_1),
> + PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1, SEL_TSN0_AVTP_PPS1_1),
> + PINMUX_IPSR_NOGM(0, TSN0_MDC, SEL_TSN0_MDC_1),
>
> PINMUX_SINGLE(AVB2_RX_CTL),
> PINMUX_SINGLE(AVB2_TX_CTL),
With the above fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 21/21] pinctrl: renesas: r8a779g0: add missing MODSELx for AVBx
2022-06-14 6:01 ` [PATCH v3 21/21] pinctrl: renesas: r8a779g0: add missing MODSELx for AVBx Kuninori Morimoto
@ 2022-06-17 15:19 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-17 15:19 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
Thanks for your patch!
On Tue, Jun 14, 2022 at 8:01 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> AVB1 needs MODSEL1, AVB2 needs MODSEL5 settings.
AVB1 needs MODSEL6
> This patch adds missing MODSELx setting for these.
>
> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c
> +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c
> @@ -745,27 +745,29 @@ static const u16 pinmux_data[] = {
> PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1, SEL_TSN0_AVTP_PPS1_1),
> PINMUX_IPSR_NOGM(0, TSN0_MDC, SEL_TSN0_MDC_1),
>
> + /* TSN0 without MDSEL5 */
MODSEL5
> PINMUX_SINGLE(AVB2_RX_CTL),
> - PINMUX_SINGLE(AVB2_TX_CTL),
> PINMUX_SINGLE(AVB2_RXC),
> PINMUX_SINGLE(AVB2_RD0),
> - PINMUX_SINGLE(AVB2_TXC),
> - PINMUX_SINGLE(AVB2_TD0),
> PINMUX_SINGLE(AVB2_RD1),
> PINMUX_SINGLE(AVB2_RD2),
> - PINMUX_SINGLE(AVB2_TD1),
> - PINMUX_SINGLE(AVB2_TD2),
> PINMUX_SINGLE(AVB2_MDIO),
> PINMUX_SINGLE(AVB2_RD3),
> - PINMUX_SINGLE(AVB2_TD3),
> PINMUX_SINGLE(AVB2_TXCREFCLK),
> - PINMUX_SINGLE(AVB2_MDC),
> - PINMUX_SINGLE(AVB2_MAGIC),
> PINMUX_SINGLE(AVB2_PHY_INT),
> PINMUX_SINGLE(AVB2_LINK),
> - PINMUX_SINGLE(AVB2_AVTP_MATCH),
> PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
> - PINMUX_SINGLE(AVB2_AVTP_PPS),
> + /* TSN0 with MDSEL5 */
MODSEL5
> + PINMUX_IPSR_NOGM(0, AVB2_TX_CTL, SEL_AVB2_TX_CTL_1),
> + PINMUX_IPSR_NOGM(0, AVB2_TXC, SEL_AVB2_TXC_1),
> + PINMUX_IPSR_NOGM(0, AVB2_TD0, SEL_AVB2_TD0_1),
> + PINMUX_IPSR_NOGM(0, AVB2_TD1, SEL_AVB2_TD1_1),
> + PINMUX_IPSR_NOGM(0, AVB2_TD2, SEL_AVB2_TD2_1),
> + PINMUX_IPSR_NOGM(0, AVB2_TD3, SEL_AVB2_TD3_1),
> + PINMUX_IPSR_NOGM(0, AVB2_MDC, SEL_AVB2_MDC_1),
> + PINMUX_IPSR_NOGM(0, AVB2_MAGIC, SEL_AVB2_MAGIC_1),
> + PINMUX_IPSR_NOGM(0, AVB2_AVTP_MATCH, SEL_AVB2_AVTP_MATCH_1),
> + PINMUX_IPSR_NOGM(0, AVB2_AVTP_PPS, SEL_AVB2_AVTP_PPS_1),
>
> /* IP0SR0 */
> PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_B),
> @@ -1060,23 +1062,23 @@ static const u16 pinmux_data[] = {
> /* IP0SR6 */
> PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
>
> - PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
> + PINMUX_IPSR_MSEL(IP0SR6_7_4, AVB1_MAGIC, SEL_AVB1_MAGIC_1),
>
> - PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
> + PINMUX_IPSR_MSEL(IP0SR6_11_8, AVB1_MDC, SEL_AVB1_MDC_1),
>
> PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
>
> PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
> PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
>
> - PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
> - PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
> + PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_AVTP_MATCH, SEL_AVB1_AVTP_MATCH_1),
> + PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_MII_RX_ER, SEL_AVB1_AVTP_MATCH_0),
>
> - PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
> - PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
> + PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_TXC, SEL_AVB1_TXC_1),
> + PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_MII_TXC, SEL_AVB1_TXC_0),
This doesn't look right to me: if TXC needs output enable, I would
expect MII_TXC to need output enable, too.
The same is true for (at least) TD[0-3].
>
> - PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
> - PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
> + PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_TX_CTL, SEL_AVB1_TX_CTL_1),
> + PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_MII_TX_EN, SEL_AVB1_TX_CTL_0),
>
> /* IP1SR6 */
> PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
> @@ -1085,17 +1087,17 @@ static const u16 pinmux_data[] = {
> PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
> PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
>
> - PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
> - PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
> + PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_AVTP_PPS, SEL_AVB1_AVTP_PPS_1),
> + PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_MII_COL, SEL_AVB1_AVTP_PPS_0),
>
> PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
> PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
>
> - PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
> - PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
> + PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_TD1, SEL_AVB1_TD1_1),
> + PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_MII_TD1, SEL_AVB1_TD1_0),
>
> - PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
> - PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
> + PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_TD0, SEL_AVB1_TD0_1),
> + PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_MII_TD0, SEL_AVB1_TD0_0),
>
> PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
> PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
> @@ -1104,14 +1106,14 @@ static const u16 pinmux_data[] = {
> PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
>
> /* IP2SR6 */
> - PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
> - PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
> + PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_TD2, SEL_AVB1_TD2_1),
> + PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_MII_TD2, SEL_AVB1_TD2_0),
>
> PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
> PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
>
> - PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
> - PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
> + PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_TD3, SEL_AVB1_TD3_1),
> + PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_MII_TD3, SEL_AVB1_TD3_0),
>
> PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
> PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 03/21] pinctrl: renesas: Initial R8A779G0 (V4H) PFC support
2022-06-17 15:13 ` [PATCH v3 03/21] pinctrl: renesas: Initial R8A779G0 (V4H) PFC support Geert Uytterhoeven
@ 2022-06-20 0:18 ` Kuninori Morimoto
2022-06-20 6:21 ` Geert Uytterhoeven
0 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-20 0:18 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Geert
Thank you for review.
> > + /* IP0SR8 */
> > + PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
> > + PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
>
> These are definitely still wrong, and not fixed by any of your
> subsequent patches: to enable I2C0 functionality, the corresponding
> SEL_{SCL,SDA}0 bit should be set to 1, not 0.
> Same for I2C[1-5] below.
There was such patch, and this patch series merged it.
Now I'm asking why the patch was needed.
I will fix and re-post v4.
But, 1 things. As I mentioned before, I want to keep original patch as much as possible,
even though it has bug (missing pins, having unnecessary settings).
In other words, the difference from original patch is only cleanup:ed.
I will keep current style on v4, too.
About suffix, I'm asking it to Doc team.
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 03/21] pinctrl: renesas: Initial R8A779G0 (V4H) PFC support
2022-06-20 0:18 ` Kuninori Morimoto
@ 2022-06-20 6:21 ` Geert Uytterhoeven
2022-06-20 6:58 ` Kuninori Morimoto
0 siblings, 1 reply; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-20 6:21 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Mon, Jun 20, 2022 at 2:18 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> > > + /* IP0SR8 */
> > > + PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
> > > + PINMUX_IPSR_MSEL(IP0SR8_7_4, SDA0, SEL_SDA0_0),
> >
> > These are definitely still wrong, and not fixed by any of your
> > subsequent patches: to enable I2C0 functionality, the corresponding
> > SEL_{SCL,SDA}0 bit should be set to 1, not 0.
> > Same for I2C[1-5] below.
>
> There was such patch, and this patch series merged it.
I don't see such a patch in this series?
> Now I'm asking why the patch was needed.
Sorry, I don't understand.
> I will fix and re-post v4.
>
> But, 1 things. As I mentioned before, I want to keep original patch as much as possible,
> even though it has bug (missing pins, having unnecessary settings).
> In other words, the difference from original patch is only cleanup:ed.
> I will keep current style on v4, too.
OK.
> About suffix, I'm asking it to Doc team.
Thank you!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 03/21] pinctrl: renesas: Initial R8A779G0 (V4H) PFC support
2022-06-20 6:21 ` Geert Uytterhoeven
@ 2022-06-20 6:58 ` Kuninori Morimoto
0 siblings, 0 replies; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-20 6:58 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Geert
> > > These are definitely still wrong, and not fixed by any of your
> > > subsequent patches: to enable I2C0 functionality, the corresponding
> > > SEL_{SCL,SDA}0 bit should be set to 1, not 0.
> > > Same for I2C[1-5] below.
> >
> > There was such patch, and this patch series merged it.
>
> I don't see such a patch in this series?
>
> > Now I'm asking why the patch was needed.
>
> Sorry, I don't understand.
Sorry for un-clear explaination.
[03/21] and [04/21] merged some/many BSP original patches into one.
[03/21] is including I2C fixup patch from Kihara-san
which fixup the SEL_{SCL,SDA} value from 1 to 0,
but this fixup seems strange, and you are now pointing it.
I'm not sure why this patch was needed, now, I'm asking.
https://github.com/renesas-rcar/linux-bsp/commit/2155127dacd61a4bb2f6f316f716a9338799a786
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 07/21] pinctrl: renesas: r8a779g0: remove not used MOD_SELx definitions
2022-06-17 15:17 ` Geert Uytterhoeven
@ 2022-06-21 0:12 ` Kuninori Morimoto
2022-06-21 6:36 ` Geert Uytterhoeven
0 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-21 0:12 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Geert
> > Current V4H PFC code has many MOD_SELx definitions with all 0.
> > But these have no meaning. This patch removes these, but keep
> > its definition to avoid unreadable PINMUX_MOD_SELS.
>
> You can just replace them with blanks, keeping the structure of the
> PINMUX_MOD_SELS table alive.
Sorry, but I don't understand this. Maybe "blanks" and "alive".
Do you mean
1) "remove unnecessary MOD_SELx, and update PINMUX_MOD_SELS table"
(= need update on v4)
or
2) "use NULL #define, and keep PINMUX_MOD_SELS" (= no update on v4)
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 07/21] pinctrl: renesas: r8a779g0: remove not used MOD_SELx definitions
2022-06-21 0:12 ` Kuninori Morimoto
@ 2022-06-21 6:36 ` Geert Uytterhoeven
0 siblings, 0 replies; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-21 6:36 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Tue, Jun 21, 2022 at 2:12 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> > > Current V4H PFC code has many MOD_SELx definitions with all 0.
> > > But these have no meaning. This patch removes these, but keep
> > > its definition to avoid unreadable PINMUX_MOD_SELS.
> >
> > You can just replace them with blanks, keeping the structure of the
> > PINMUX_MOD_SELS table alive.
>
> Sorry, but I don't understand this. Maybe "blanks" and "alive".
blanks = TABs, i.e. a hole in the table structure
perhaps s/alive/intact/?
> Do you mean
> 1) "remove unnecessary MOD_SELx, and update PINMUX_MOD_SELS table"
> (= need update on v4)
>
> or
>
> 2) "use NULL #define, and keep PINMUX_MOD_SELS" (= no update on v4)
I meant 1).
E.g.
-#define MOD_SEL7_1
and
-MOD_SEL4_1 MOD_SEL5_1 MOD_SEL6_1
MOD_SEL7_1 MOD_SEL8_1 \
+MOD_SEL4_1 MOD_SEL5_1 MOD_SEL6_1
MOD_SEL8_1 \
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X
2022-06-17 15:17 ` Geert Uytterhoeven
@ 2022-06-29 1:26 ` Kuninori Morimoto
2022-06-29 2:49 ` Kuninori Morimoto
0 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-29 1:26 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Geert
> > From: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
> >
> > This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X
> >
> > Because Document has 2xTCLK3/TCLK4 with no suffix (_A, _B),
> > this patch name it as _X.
> >
> > Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
>
> Thanks for your patch!
>
> LGTM, but as the suffixes become part of the DT ABI when defining
> pin groups, we should get the conflicts resolved, and this cannot
> be applied as-is.
It seems HW team / Doc team are now fixuping suffixes.
I think I need to use new Doc for v4.
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X
2022-06-29 1:26 ` Kuninori Morimoto
@ 2022-06-29 2:49 ` Kuninori Morimoto
2022-06-29 7:16 ` Geert Uytterhoeven
0 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-29 2:49 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Geert
> > LGTM, but as the suffixes become part of the DT ABI when defining
> > pin groups, we should get the conflicts resolved, and this cannot
> > be applied as-is.
>
> It seems HW team / Doc team are now fixuping suffixes.
> I think I need to use new Doc for v4.
We don't know when new Doc comming,
and I don't think there is someone who will get DT naming exchange issue for now
(Because no uses).
So, I'm happy if you can accept my next v4 patch-set (suffix is still using _X).
and I'm happy to post new incremental patch which is for
"update PFC to adjust to latest Datasheet" in such case.
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X
2022-06-29 2:49 ` Kuninori Morimoto
@ 2022-06-29 7:16 ` Geert Uytterhoeven
2022-06-29 23:37 ` Kuninori Morimoto
0 siblings, 1 reply; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-29 7:16 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Wed, Jun 29, 2022 at 4:49 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> > > LGTM, but as the suffixes become part of the DT ABI when defining
> > > pin groups, we should get the conflicts resolved, and this cannot
> > > be applied as-is.
> >
> > It seems HW team / Doc team are now fixuping suffixes.
> > I think I need to use new Doc for v4.
>
> We don't know when new Doc comming,
> and I don't think there is someone who will get DT naming exchange issue for now
> (Because no uses).
>
> So, I'm happy if you can accept my next v4 patch-set (suffix is still using _X).
> and I'm happy to post new incremental patch which is for
> "update PFC to adjust to latest Datasheet" in such case.
My worry is not about the group of pins marked _X, but about its
siblings without _X. E.g. your patches have SCIF1 and SCIF1_X,
but we do not know yet if SCIF1 should be renamed, too.
I agree it is unlikely to become an issue with TCLK soon, but (H)SCIF1
are more likely to become enabled, also on real products.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X
2022-06-29 7:16 ` Geert Uytterhoeven
@ 2022-06-29 23:37 ` Kuninori Morimoto
2022-06-30 9:30 ` Geert Uytterhoeven
0 siblings, 1 reply; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-29 23:37 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Geert
Thank you for your feedback
> My worry is not about the group of pins marked _X, but about its
> siblings without _X. E.g. your patches have SCIF1 and SCIF1_X,
> but we do not know yet if SCIF1 should be renamed, too.
Yes.
> I agree it is unlikely to become an issue with TCLK soon, but (H)SCIF1
> are more likely to become enabled, also on real products.
Yeah.
But *current* product (White Hawk) is using (H)SCIF0 which doesn't
have rename issue. I think we don't need to super care about not
used SCIF for now (?), at least it is following *current* latest datasheet.
If you can accept about it, I will post v4 patch-set soon,
and will post naming update patch when new datasheet coming.
If you can't, I will wait new datasheet, and post v4 patch-set
which is including naming update.
But one note here is that we don't know when the new datasheet will comming,
and we don't know it solves all naming issue and/or there will be no more naming issue.
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X
2022-06-29 23:37 ` Kuninori Morimoto
@ 2022-06-30 9:30 ` Geert Uytterhoeven
2022-06-30 23:35 ` Kuninori Morimoto
0 siblings, 1 reply; 53+ messages in thread
From: Geert Uytterhoeven @ 2022-06-30 9:30 UTC (permalink / raw)
To: Kuninori Morimoto; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Morimoto-san,
On Thu, Jun 30, 2022 at 1:37 AM Kuninori Morimoto
<kuninori.morimoto.gx@renesas.com> wrote:
> > My worry is not about the group of pins marked _X, but about its
> > siblings without _X. E.g. your patches have SCIF1 and SCIF1_X,
> > but we do not know yet if SCIF1 should be renamed, too.
>
> Yes.
>
> > I agree it is unlikely to become an issue with TCLK soon, but (H)SCIF1
> > are more likely to become enabled, also on real products.
>
> Yeah.
>
> But *current* product (White Hawk) is using (H)SCIF0 which doesn't
> have rename issue. I think we don't need to super care about not
> used SCIF for now (?), at least it is following *current* latest datasheet.
>
> If you can accept about it, I will post v4 patch-set soon,
> and will post naming update patch when new datasheet coming.
>
> If you can't, I will wait new datasheet, and post v4 patch-set
> which is including naming update.
>
> But one note here is that we don't know when the new datasheet will comming,
> and we don't know it solves all naming issue and/or there will be no more naming issue.
OK, then please continue.
But perhaps add a comment to the SH_PFC_PIN_GROUP() definitions,
to make it clear they are preliminary?
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X
2022-06-30 9:30 ` Geert Uytterhoeven
@ 2022-06-30 23:35 ` Kuninori Morimoto
0 siblings, 0 replies; 53+ messages in thread
From: Kuninori Morimoto @ 2022-06-30 23:35 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM
Hi Geert
> OK, then please continue.
> But perhaps add a comment to the SH_PFC_PIN_GROUP() definitions,
> to make it clear they are preliminary?
Yes ! Good idea !
Thank you for your help !!
Best regards
---
Kuninori Morimoto
^ permalink raw reply [flat|nested] 53+ messages in thread
end of thread, other threads:[~2022-06-30 23:35 UTC | newest]
Thread overview: 53+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-14 5:57 [PATCH v3 00/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
2022-06-14 5:58 ` [PATCH v3 01/21] dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support Kuninori Morimoto
2022-06-17 12:30 ` Geert Uytterhoeven
2022-06-14 5:58 ` [PATCH v3 02/21] pinctrl: renesas: Add PORT_GP_CFG_13 macros Kuninori Morimoto
2022-06-17 12:30 ` Geert Uytterhoeven
2022-06-14 5:58 ` [PATCH v3 04/21] pinctrl: renesas: r8a779g0: Add pins, groups and functions Kuninori Morimoto
2022-06-17 15:15 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 05/21] pinctrl: renesas: r8a779g0: remove not used NOGP definitions Kuninori Morimoto
2022-06-17 15:16 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 06/21] pinctrl: renesas: r8a779g0: remove not used IPxSRx definitions Kuninori Morimoto
2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 07/21] pinctrl: renesas: r8a779g0: remove not used MOD_SELx definitions Kuninori Morimoto
2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-21 0:12 ` Kuninori Morimoto
2022-06-21 6:36 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 08/21] pinctrl: renesas: r8a779g0: tidyup ioctrl_regs Kuninori Morimoto
2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 09/21] pinctrl: renesas: r8a779g0: add missing TCLKx_A/TCLK_B/TCLKx_X Kuninori Morimoto
2022-06-17 15:17 ` Geert Uytterhoeven
2022-06-29 1:26 ` Kuninori Morimoto
2022-06-29 2:49 ` Kuninori Morimoto
2022-06-29 7:16 ` Geert Uytterhoeven
2022-06-29 23:37 ` Kuninori Morimoto
2022-06-30 9:30 ` Geert Uytterhoeven
2022-06-30 23:35 ` Kuninori Morimoto
2022-06-14 5:59 ` [PATCH v3 10/21] pinctrl: renesas: r8a779g0: add missing IRQx_A/IRQx_B Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 11/21] pinctrl: renesas: r8a779g0: add missing HSCIF3_A Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 5:59 ` [PATCH v3 12/21] pinctrl: renesas: r8a779g0: add missing HSCIF1_X Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 13/21] pinctrl: renesas: r8a779g0: add missing SCIF3 Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 14/21] pinctrl: renesas: r8a779g0: add missing SCIF1_X Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 15/21] pinctrl: renesas: r8a779g0: add missing CANFD5_B Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 16/21] pinctrl: renesas: r8a779g0: add missing TPU0TOx_A Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 17/21] pinctrl: renesas: r8a779g0: add missing FlaxRay Kuninori Morimoto
2022-06-17 15:18 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 18/21] pinctrl: renesas: r8a779g0: add missing PWM Kuninori Morimoto
2022-06-17 15:19 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 19/21] pinctrl: renesas: r8a779g0: add missing ERROROUTC_A Kuninori Morimoto
2022-06-17 15:19 ` Geert Uytterhoeven
2022-06-14 6:00 ` [PATCH v3 20/21] pinctrl: renesas: r8a779g0: add missing MODSELx for TSN0 Kuninori Morimoto
2022-06-17 15:19 ` Geert Uytterhoeven
2022-06-14 6:01 ` [PATCH v3 21/21] pinctrl: renesas: r8a779g0: add missing MODSELx for AVBx Kuninori Morimoto
2022-06-17 15:19 ` Geert Uytterhoeven
[not found] ` <87zgifkcqa.wl-kuninori.morimoto.gx@renesas.com>
2022-06-17 15:13 ` [PATCH v3 03/21] pinctrl: renesas: Initial R8A779G0 (V4H) PFC support Geert Uytterhoeven
2022-06-20 0:18 ` Kuninori Morimoto
2022-06-20 6:21 ` Geert Uytterhoeven
2022-06-20 6:58 ` Kuninori Morimoto
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