* [PATCH] clk: renesas: r9a07g043: Hide WDT2 clock and reset entries for RZ/Five
@ 2022-09-19 11:58 Prabhakar
2022-09-19 12:08 ` Geert Uytterhoeven
0 siblings, 1 reply; 3+ messages in thread
From: Prabhakar @ 2022-09-19 11:58 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: linux-renesas-soc, linux-kernel, Prabhakar, Biju Das, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Make the clock and reset entries for WDT2 only visible for RZ/G2UL (ARM64)
as the RZ/Five SoC doesn't have the WDT2 channel.
While at it, add the WDT2 clocks to r9a07g043_crit_mod_clks[] list as WDT
CH2 is specifically to check the operation of Cortex-M33 CPU on the RZ/G2UL
SoC and we dont want to turn off the clocks of WDT2 if it isn't enabled by
Cortex-A55.
Fixes: 95d48d270305 ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
Reported-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 37475465100d..06692274025d 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -158,10 +158,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x548, 0),
DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
0x548, 1),
+#ifdef CONFIG_ARM64
DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
0x548, 4),
DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
0x548, 5),
+#endif
DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
0x550, 0),
DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
@@ -269,7 +271,9 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
+#ifdef CONFIG_ARM64
DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
+#endif
DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
@@ -311,6 +315,8 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
#ifdef CONFIG_ARM64
MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
MOD_CLK_BASE + R9A07G043_IA55_CLK,
+ MOD_CLK_BASE + R9A07G043_WDT2_PCLK,
+ MOD_CLK_BASE + R9A07G043_WDT2_CLK,
#endif
#ifdef CONFIG_RISCV
MOD_CLK_BASE + R9A07G043_IAX45_CLK,
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: renesas: r9a07g043: Hide WDT2 clock and reset entries for RZ/Five
2022-09-19 11:58 [PATCH] clk: renesas: r9a07g043: Hide WDT2 clock and reset entries for RZ/Five Prabhakar
@ 2022-09-19 12:08 ` Geert Uytterhoeven
2022-09-19 12:27 ` Lad, Prabhakar
0 siblings, 1 reply; 3+ messages in thread
From: Geert Uytterhoeven @ 2022-09-19 12:08 UTC (permalink / raw)
To: Prabhakar
Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-kernel,
Biju Das, Lad Prabhakar
Hi Prabhakar,
On Mon, Sep 19, 2022 at 2:00 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Make the clock and reset entries for WDT2 only visible for RZ/G2UL (ARM64)
> as the RZ/Five SoC doesn't have the WDT2 channel.
>
> While at it, add the WDT2 clocks to r9a07g043_crit_mod_clks[] list as WDT
> CH2 is specifically to check the operation of Cortex-M33 CPU on the RZ/G2UL
> SoC and we dont want to turn off the clocks of WDT2 if it isn't enabled by
> Cortex-A55.
>
> Fixes: 95d48d270305 ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
> Reported-by: Biju Das <biju.das.jz@bp.renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a07g043-cpg.c
> +++ b/drivers/clk/renesas/r9a07g043-cpg.c
> @@ -158,10 +158,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
> 0x548, 0),
> DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
> 0x548, 1),
> +#ifdef CONFIG_ARM64
> DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
> 0x548, 4),
> DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
> 0x548, 5),
> +#endif
Please move these into the existing section for arm64.
> DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
> 0x550, 0),
> DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
> @@ -269,7 +271,9 @@ static struct rzg2l_reset r9a07g043_resets[] = {
> DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
> DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
> DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
> +#ifdef CONFIG_ARM64
> DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
> +#endif
Likewise.
> DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
> DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
> DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: renesas: r9a07g043: Hide WDT2 clock and reset entries for RZ/Five
2022-09-19 12:08 ` Geert Uytterhoeven
@ 2022-09-19 12:27 ` Lad, Prabhakar
0 siblings, 0 replies; 3+ messages in thread
From: Lad, Prabhakar @ 2022-09-19 12:27 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, linux-renesas-soc, linux-kernel,
Biju Das, Lad Prabhakar
Hi Geert,
Thank you for the review.
On Mon, Sep 19, 2022 at 1:08 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Sep 19, 2022 at 2:00 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Make the clock and reset entries for WDT2 only visible for RZ/G2UL (ARM64)
> > as the RZ/Five SoC doesn't have the WDT2 channel.
> >
> > While at it, add the WDT2 clocks to r9a07g043_crit_mod_clks[] list as WDT
> > CH2 is specifically to check the operation of Cortex-M33 CPU on the RZ/G2UL
> > SoC and we dont want to turn off the clocks of WDT2 if it isn't enabled by
> > Cortex-A55.
> >
> > Fixes: 95d48d270305 ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
> > Reported-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a07g043-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g043-cpg.c
> > @@ -158,10 +158,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
> > 0x548, 0),
> > DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
> > 0x548, 1),
> > +#ifdef CONFIG_ARM64
> > DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
> > 0x548, 4),
> > DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
> > 0x548, 5),
> > +#endif
>
> Please move these into the existing section for arm64.
>
OK, I will move this to the existing section (and below).
Cheers,
Prabhakar
> > DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1,
> > 0x550, 0),
> > DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0,
> > @@ -269,7 +271,9 @@ static struct rzg2l_reset r9a07g043_resets[] = {
> > DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
> > DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
> > DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
> > +#ifdef CONFIG_ARM64
> > DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
> > +#endif
>
> Likewise.
>
> > DEF_RST(R9A07G043_SPI_RST, 0x850, 0),
> > DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
> > DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-09-19 12:28 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-19 11:58 [PATCH] clk: renesas: r9a07g043: Hide WDT2 clock and reset entries for RZ/Five Prabhakar
2022-09-19 12:08 ` Geert Uytterhoeven
2022-09-19 12:27 ` Lad, Prabhakar
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).