* [PATCH v3 0/2] Add Initial Device Tree for RZ/A2
@ 2018-12-17 14:43 Chris Brandt
2018-12-17 14:43 ` [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree Chris Brandt
2018-12-17 14:43 ` [PATCH v3 2/2] ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB Chris Brandt
0 siblings, 2 replies; 8+ messages in thread
From: Chris Brandt @ 2018-12-17 14:43 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Mark Rutland
Cc: devicetree, linux-renesas-soc, Chris Brandt
Add a Device Tree for RZ/A2 and the existing eval board.
Once these get approved, I'll start piling on the other drivers in
another patch series
NOTE:
Since Rob is currently converting shmobile.txt to renesas.yaml,
I'll wait till renesas.yaml hits -next, then add this RZ/A2M EVB
board (it's too confusing to me to figure out how to make a patch
series using multiple different trees)
Chris Brandt (2):
ARM: dts: r7s9210: Initial SoC device tree
ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 82 +++++++++++++
arch/arm/boot/dts/r7s9210.dtsi | 204 +++++++++++++++++++++++++++++++++
3 files changed, 287 insertions(+)
create mode 100644 arch/arm/boot/dts/r7s9210-rza2mevb.dts
create mode 100644 arch/arm/boot/dts/r7s9210.dtsi
--
2.16.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree
2018-12-17 14:43 [PATCH v3 0/2] Add Initial Device Tree for RZ/A2 Chris Brandt
@ 2018-12-17 14:43 ` Chris Brandt
2018-12-18 15:05 ` Rob Herring
2018-12-17 14:43 ` [PATCH v3 2/2] ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB Chris Brandt
1 sibling, 1 reply; 8+ messages in thread
From: Chris Brandt @ 2018-12-17 14:43 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Mark Rutland
Cc: devicetree, linux-renesas-soc, Chris Brandt
Basic support for the RZ/A2 (R7S9210) SoC.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v2:
* Fixed cpg node name to match reg address
* Removed the clocks subnode
* SCIF register range 18 to 0x18
* Removed 'reset-cells' from cpg because resets not supported (yet?)
* Sorted nodes by address (per group of device
---
arch/arm/boot/dts/r7s9210.dtsi | 204 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 204 insertions(+)
create mode 100644 arch/arm/boot/dts/r7s9210.dtsi
diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
new file mode 100644
index 000000000000..2b589226895e
--- /dev/null
+++ b/arch/arm/boot/dts/r7s9210.dtsi
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the R7S9210 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corporation
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
+
+/ {
+ compatible = "renesas,r7s9210";
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bsid: chipid@fcfe8004 {
+ compatible = "renesas,bsid";
+ reg = <0xfcfe8004 4>;
+ };
+
+ /* External clocks */
+ extal_clk: extal {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ /* Value must be set by board */
+ clock-frequency = <0>;
+ };
+
+ rtc_x1_clk: rtc_x1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ /* If clk present, value (32678) must be set by board */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ clock-frequency = <528000000>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ L2: cache-controller@1f003000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1f003000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ arm,early-bresp-disable;
+ arm,full-line-zero-disable;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ gic: interrupt-controller@e8221000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0xe8221000 0x1000>,
+ <0xe8222000 0x1000>;
+ };
+
+ cpg: clock-controller@fcfe0010 {
+ compatible = "renesas,r7s9210-cpg-mssr";
+ reg = <0xfcfe0010 0x455>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ };
+
+ wdt: watchdog@fcfe7000 {
+ compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
+ reg = <0xfcfe7000 0x26>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
+ };
+
+ pinctrl: pin-controller@fcffe000 {
+ compatible = "renesas,r7s9210-pinctrl";
+ reg = <0xfcffe000 0x1000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 176>;
+ };
+
+ scif0: serial@e8007000 {
+ compatible = "renesas,scif-r7s9210";
+ reg = <0xe8007000 0x18>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD 47>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ scif1: serial@e8007800 {
+ compatible = "renesas,scif-r7s9210";
+ reg = <0xe8007800 0x18>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD 46>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ scif2: serial@e8008000 {
+ compatible = "renesas,scif-r7s9210";
+ reg = <0xe8008000 0x18>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD 45>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ scif3: serial@e8008800 {
+ compatible = "renesas,scif-r7s9210";
+ reg = <0xe8008800 0x18>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD 44>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ scif4: serial@e8009000 {
+ compatible = "renesas,scif-r7s9210";
+ reg = <0xe8009000 0x18>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD 43>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ostm0: timer@e803b000 {
+ compatible = "renesas,r7s9210-ostm", "renesas,ostm";
+ reg = <0xe803b000 0x30>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD 36>;
+ clock-names = "ostm0";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ostm1: timer@e803c000 {
+ compatible = "renesas,r7s9210-ostm", "renesas,ostm";
+ reg = <0xe803c000 0x30>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD 35>;
+ clock-names = "ostm1";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ ostm2: timer@e803d000 {
+ compatible = "renesas,r7s9210-ostm", "renesas,ostm";
+ reg = <0xe803d000 0x30>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD 34>;
+ clock-names = "ostm2";
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+};
--
2.16.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB
2018-12-17 14:43 [PATCH v3 0/2] Add Initial Device Tree for RZ/A2 Chris Brandt
2018-12-17 14:43 ` [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree Chris Brandt
@ 2018-12-17 14:43 ` Chris Brandt
1 sibling, 0 replies; 8+ messages in thread
From: Chris Brandt @ 2018-12-17 14:43 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Mark Rutland
Cc: devicetree, linux-renesas-soc, Chris Brandt
Add support for Renesas RZ/A2M evaluation board.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v3:
* Removed QSPI partition (because half baked at the moment)
v2:
* Removed patch for shmobile.txt
* Added SPDX
* Removed earlycon from bootargs
* Fixed address in memory node name
* Removed un-needed "okay" from leds node
* Added green LED node
* Dropped this blank line in pinctrl node
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r7s9210-rza2mevb.dts | 82 ++++++++++++++++++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 arch/arm/boot/dts/r7s9210-rza2mevb.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1ef2133a18c2..9665694b6494 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -824,6 +824,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r7s72100-genmai.dtb \
r7s72100-gr-peach.dtb \
r7s72100-rskrza1.dtb \
+ r7s9210-rza2mevb.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-iwg20d-q7.dtb \
diff --git a/arch/arm/boot/dts/r7s9210-rza2mevb.dts b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
new file mode 100644
index 000000000000..991e09de1219
--- /dev/null
+++ b/arch/arm/boot/dts/r7s9210-rza2mevb.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZA2MEVB board
+ *
+ * Copyright (C) 2018 Renesas Electronics
+ *
+ */
+
+/dts-v1/;
+#include "r7s9210.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
+
+/ {
+ model = "RZA2MEVB";
+ compatible = "renesas,rza2mevb", "renesas,r7s9210";
+
+ aliases {
+ serial0 = &scif4;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x00800000>; /* HyperRAM */
+ };
+
+ lbsc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ red {
+ gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
+ };
+ green {
+ gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+/* EXTAL */
+&extal_clk {
+ clock-frequency = <24000000>; /* 24MHz */
+};
+
+/* RTC_X1 */
+&rtc_x1_clk {
+ clock-frequency = <32768>;
+};
+
+&pinctrl {
+ /* Serial Console */
+ scif4_pins: serial4 {
+ pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
+ <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
+ };
+};
+
+/* High resolution System tick timers */
+&ostm0 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
+/* Serial Console */
+&scif4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&scif4_pins>;
+
+ status = "okay";
+};
--
2.16.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree
2018-12-17 14:43 ` [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree Chris Brandt
@ 2018-12-18 15:05 ` Rob Herring
2018-12-18 15:40 ` Chris Brandt
2018-12-19 14:05 ` Rob Herring
0 siblings, 2 replies; 8+ messages in thread
From: Rob Herring @ 2018-12-18 15:05 UTC (permalink / raw)
To: Chris Brandt; +Cc: Simon Horman, Mark Rutland, devicetree, linux-renesas-soc
On Mon, Dec 17, 2018 at 09:43:23AM -0500, Chris Brandt wrote:
> Basic support for the RZ/A2 (R7S9210) SoC.
>
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
> v2:
> * Fixed cpg node name to match reg address
> * Removed the clocks subnode
> * SCIF register range 18 to 0x18
> * Removed 'reset-cells' from cpg because resets not supported (yet?)
> * Sorted nodes by address (per group of device
> ---
> arch/arm/boot/dts/r7s9210.dtsi | 204 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 204 insertions(+)
> create mode 100644 arch/arm/boot/dts/r7s9210.dtsi
>
> diff --git a/arch/arm/boot/dts/r7s9210.dtsi b/arch/arm/boot/dts/r7s9210.dtsi
> new file mode 100644
> index 000000000000..2b589226895e
> --- /dev/null
> +++ b/arch/arm/boot/dts/r7s9210.dtsi
> @@ -0,0 +1,204 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the R7S9210 SoC
> + *
> + * Copyright (C) 2018 Renesas Electronics Corporation
> + *
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
> +
> +/ {
> + compatible = "renesas,r7s9210";
> + interrupt-parent = <&gic>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + bsid: chipid@fcfe8004 {
Put all the mmio peripherals under a simple-bus node or nodes.
> + compatible = "renesas,bsid";
> + reg = <0xfcfe8004 4>;
> + };
> +
> + /* External clocks */
> + extal_clk: extal {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + /* Value must be set by board */
> + clock-frequency = <0>;
> + };
> +
> + rtc_x1_clk: rtc_x1 {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + /* If clk present, value (32678) must be set by board */
> + clock-frequency = <0>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a9";
> + reg = <0>;
> + clock-frequency = <528000000>;
> + next-level-cache = <&L2>;
> + };
> + };
> +
> + L2: cache-controller@1f003000 {
> + compatible = "arm,pl310-cache";
> + reg = <0x1f003000 0x1000>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + arm,early-bresp-disable;
> + arm,full-line-zero-disable;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + gic: interrupt-controller@e8221000 {
> + compatible = "arm,gic-400";
Kind of strange that a single core A9 uses an external GIC rather than
the built-in one.
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> + interrupt-controller;
> + reg = <0xe8221000 0x1000>,
> + <0xe8222000 0x1000>;
> + };
> +
> + cpg: clock-controller@fcfe0010 {
> + compatible = "renesas,r7s9210-cpg-mssr";
> + reg = <0xfcfe0010 0x455>;
> + clocks = <&extal_clk>;
> + clock-names = "extal";
> + #clock-cells = <2>;
> + #power-domain-cells = <0>;
> + };
> +
> + wdt: watchdog@fcfe7000 {
> + compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
> + reg = <0xfcfe7000 0x26>;
> + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
> + };
> +
> + pinctrl: pin-controller@fcffe000 {
> + compatible = "renesas,r7s9210-pinctrl";
> + reg = <0xfcffe000 0x1000>;
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl 0 0 176>;
> + };
> +
> + scif0: serial@e8007000 {
> + compatible = "renesas,scif-r7s9210";
> + reg = <0xe8007000 0x18>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> + clocks = <&cpg CPG_MOD 47>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> + scif1: serial@e8007800 {
> + compatible = "renesas,scif-r7s9210";
> + reg = <0xe8007800 0x18>;
> + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> + clocks = <&cpg CPG_MOD 46>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> + scif2: serial@e8008000 {
> + compatible = "renesas,scif-r7s9210";
> + reg = <0xe8008000 0x18>;
> + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> + clocks = <&cpg CPG_MOD 45>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> + scif3: serial@e8008800 {
> + compatible = "renesas,scif-r7s9210";
> + reg = <0xe8008800 0x18>;
> + interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> + clocks = <&cpg CPG_MOD 44>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> + scif4: serial@e8009000 {
> + compatible = "renesas,scif-r7s9210";
> + reg = <0xe8009000 0x18>;
> + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eri", "rxi", "txi", "bri", "dri", "tei";
> + clocks = <&cpg CPG_MOD 43>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> + ostm0: timer@e803b000 {
> + compatible = "renesas,r7s9210-ostm", "renesas,ostm";
> + reg = <0xe803b000 0x30>;
> + interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&cpg CPG_MOD 36>;
> + clock-names = "ostm0";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> + ostm1: timer@e803c000 {
> + compatible = "renesas,r7s9210-ostm", "renesas,ostm";
> + reg = <0xe803c000 0x30>;
> + interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&cpg CPG_MOD 35>;
> + clock-names = "ostm1";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +
> + ostm2: timer@e803d000 {
> + compatible = "renesas,r7s9210-ostm", "renesas,ostm";
> + reg = <0xe803d000 0x30>;
> + interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
> + clocks = <&cpg CPG_MOD 34>;
> + clock-names = "ostm2";
> + power-domains = <&cpg>;
> + status = "disabled";
> + };
> +};
> --
> 2.16.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree
2018-12-18 15:05 ` Rob Herring
@ 2018-12-18 15:40 ` Chris Brandt
2018-12-18 15:44 ` Rob Herring
2018-12-19 14:05 ` Rob Herring
1 sibling, 1 reply; 8+ messages in thread
From: Chris Brandt @ 2018-12-18 15:40 UTC (permalink / raw)
To: Rob Herring; +Cc: Simon Horman, Mark Rutland, devicetree, linux-renesas-soc
On Tuesday, December 18, 2018 1, Rob Herring wrote:
> > +/ {
> > + compatible = "renesas,r7s9210";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + bsid: chipid@fcfe8004 {
>
> Put all the mmio peripherals under a simple-bus node or nodes.
Just to be clear on what you mean, basically put all the peripherals
under a 'soc' node like the other Renesas parts?
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
Thanks,
Chris
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree
2018-12-18 15:40 ` Chris Brandt
@ 2018-12-18 15:44 ` Rob Herring
0 siblings, 0 replies; 8+ messages in thread
From: Rob Herring @ 2018-12-18 15:44 UTC (permalink / raw)
To: Chris Brandt
Cc: Simon Horman, Mark Rutland, devicetree,
open list:MEDIA DRIVERS FOR RENESAS - FCP
On Tue, Dec 18, 2018 at 9:40 AM Chris Brandt <Chris.Brandt@renesas.com> wrote:
>
> On Tuesday, December 18, 2018 1, Rob Herring wrote:
> > > +/ {
> > > + compatible = "renesas,r7s9210";
> > > + interrupt-parent = <&gic>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > +
> > > + bsid: chipid@fcfe8004 {
> >
> > Put all the mmio peripherals under a simple-bus node or nodes.
>
> Just to be clear on what you mean, basically put all the peripherals
> under a 'soc' node like the other Renesas parts?
Yes.
>
> soc {
> compatible = "simple-bus";
> interrupt-parent = <&gic>;
>
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
>
>
> Thanks,
> Chris
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree
2018-12-18 15:05 ` Rob Herring
2018-12-18 15:40 ` Chris Brandt
@ 2018-12-19 14:05 ` Rob Herring
2018-12-19 14:22 ` Geert Uytterhoeven
1 sibling, 1 reply; 8+ messages in thread
From: Rob Herring @ 2018-12-19 14:05 UTC (permalink / raw)
To: Chris Brandt
Cc: Simon Horman, Mark Rutland, devicetree,
open list:MEDIA DRIVERS FOR RENESAS - FCP
On Tue, Dec 18, 2018 at 9:05 AM Rob Herring <robh@kernel.org> wrote:
>
> On Mon, Dec 17, 2018 at 09:43:23AM -0500, Chris Brandt wrote:
> > Basic support for the RZ/A2 (R7S9210) SoC.
> >
> > Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> > ---
> > + gic: interrupt-controller@e8221000 {
> > + compatible = "arm,gic-400";
>
> Kind of strange that a single core A9 uses an external GIC rather than
> the built-in one.
Still have this question on v4. It should be "arm,cortex-a9-gic" if
the A9 built-in GIC is used.
Rob
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree
2018-12-19 14:05 ` Rob Herring
@ 2018-12-19 14:22 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2018-12-19 14:22 UTC (permalink / raw)
To: Rob Herring
Cc: Chris Brandt, Simon Horman, Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:MEDIA DRIVERS FOR RENESAS - FCP
Hi Rob,
On Wed, Dec 19, 2018 at 3:07 PM Rob Herring <robh@kernel.org> wrote:
> On Tue, Dec 18, 2018 at 9:05 AM Rob Herring <robh@kernel.org> wrote:
> > On Mon, Dec 17, 2018 at 09:43:23AM -0500, Chris Brandt wrote:
> > > Basic support for the RZ/A2 (R7S9210) SoC.
> > >
> > > Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> > > ---
>
> > > + gic: interrupt-controller@e8221000 {
> > > + compatible = "arm,gic-400";
> >
> > Kind of strange that a single core A9 uses an external GIC rather than
> > the built-in one.
>
> Still have this question on v4. It should be "arm,cortex-a9-gic" if
> the A9 built-in GIC is used.
The GIC in RZ/A2 is documented to be a GIC-400. Apparently the A9 GIC does
not have enough interrupt sources to serve all RZ/A2 peripherals.
Note that several Renesas A9 SoCs use a PL390.
https://lore.kernel.org/lkml/20150429125703.GB11757@leverpostej/
has a patch to print the GIC variant ID at runtime, to be 100% sure.
0x0000043b = arm,pl390
0x0102043b = arm,cortex-a9-gic
0x0200043b = arm,gic-400
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-12-19 14:22 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-17 14:43 [PATCH v3 0/2] Add Initial Device Tree for RZ/A2 Chris Brandt
2018-12-17 14:43 ` [PATCH v3 1/2] ARM: dts: r7s9210: Initial SoC device tree Chris Brandt
2018-12-18 15:05 ` Rob Herring
2018-12-18 15:40 ` Chris Brandt
2018-12-18 15:44 ` Rob Herring
2018-12-19 14:05 ` Rob Herring
2018-12-19 14:22 ` Geert Uytterhoeven
2018-12-17 14:43 ` [PATCH v3 2/2] ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB Chris Brandt
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