* [PATCH 0/4] clk: renesas: rcar-gen3: Add ZG support for E3, D3 and RZ/G2E
@ 2019-02-28 13:52 Simon Horman
2019-02-28 13:52 ` [PATCH 1/4] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock register offset Simon Horman
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Simon Horman @ 2019-02-28 13:52 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, linux-renesas-soc, linux-clk, Simon Horman
Hi,
this series introduces ZG support for the E3, D3 and RZ/G2E.
On these SoCs these are programmable clocks similar to the Z and Z2 clocks
which are already supported. This implementation leverages those
similarities to support the Z2 clock by parameterising existing Z and Z2
clock support.
---
Simon Horman (4):
clk: renesas: rcar-gen3: Parameterise Z and Z2 clock register offset
clk: renesas: r8a77990: Add ZG clock
[RFT] clk: renesas: r8a774c0: Add ZG clock
[RFT] clk: renesas: r8a77995: Add ZG clock
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 6 ++++--
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 5 ++++-
drivers/clk/renesas/r8a7795-cpg-mssr.c | 6 ++++--
drivers/clk/renesas/r8a7796-cpg-mssr.c | 6 ++++--
drivers/clk/renesas/r8a77965-cpg-mssr.c | 3 ++-
drivers/clk/renesas/r8a77990-cpg-mssr.c | 5 ++++-
drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 ++
drivers/clk/renesas/rcar-gen3-cpg.c | 11 +++++------
drivers/clk/renesas/rcar-gen3-cpg.h | 14 ++++++++++++--
9 files changed, 41 insertions(+), 17 deletions(-)
--
2.11.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 1/4] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock register offset 2019-02-28 13:52 [PATCH 0/4] clk: renesas: rcar-gen3: Add ZG support for E3, D3 and RZ/G2E Simon Horman @ 2019-02-28 13:52 ` Simon Horman 2019-03-01 12:38 ` Geert Uytterhoeven 2019-02-28 13:52 ` [PATCH 2/4] clk: renesas: r8a77990: Add ZG clock Simon Horman ` (2 subsequent siblings) 3 siblings, 1 reply; 11+ messages in thread From: Simon Horman @ 2019-02-28 13:52 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, linux-renesas-soc, linux-clk, Simon Horman Parameterise the offset of the control register for for Z and Z2 clocks. This is in preparation for supporting the ZG clock on the R-Car E3 (r8a77990), D3 (r8a7795) and RZ/G2E (r8a774c0) SoCs which uses a different control register to existing support for Z and Z2 clocks. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- Tested for regressions on Ebisu by using CPUFreq to alter Z and Z2 clock rates --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 6 ++++-- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 3 ++- drivers/clk/renesas/r8a7795-cpg-mssr.c | 6 ++++-- drivers/clk/renesas/r8a7796-cpg-mssr.c | 6 ++++-- drivers/clk/renesas/r8a77965-cpg-mssr.c | 3 ++- drivers/clk/renesas/r8a77990-cpg-mssr.c | 3 ++- drivers/clk/renesas/rcar-gen3-cpg.c | 10 +++++----- drivers/clk/renesas/rcar-gen3-cpg.h | 13 +++++++++++-- 8 files changed, 34 insertions(+), 16 deletions(-) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index d93eb4da152b..9ac61fae993a 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -71,8 +71,10 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, + CLK_PLL0, 2, CPG_FRQCRC, 8), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, + CLK_PLL2, 2, CPG_FRQCRC, 0), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index 5ba575242eee..d9130723d6c8 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -79,7 +79,8 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A774C0_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), - DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), + DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, + CLK_PLL0, 4, CPG_FRQCRC, 8), DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 8287816523c3..935085161b47 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -74,8 +74,10 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), - DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, + 2, CPG_FRQCRC, 8), + DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, + 2, CPG_FRQCRC, 0), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 5cde1bff8923..ca7fcec5bce2 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -74,8 +74,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), - DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, + 2, CPG_FRQCRC, 8), + DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, + 2, CPG_FRQCRC, 0), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index fefa26a1a797..fb5de677f828 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -71,7 +71,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), + DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, + CLK_PLL0, 2, CPG_FRQCRC, 8), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 99f602cb30a5..0e475dcb68b9 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -81,7 +81,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), - DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8), + DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, + 4, CPG_FRQCRC, 8), DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index a40ad6d03ece..14a82c51682e 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -72,7 +72,6 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, */ #define CPG_FRQCRB 0x00000004 #define CPG_FRQCRB_KICK BIT(31) -#define CPG_FRQCRC 0x000000e0 struct cpg_z_clk { struct clk_hw hw; @@ -166,7 +165,7 @@ static const struct clk_ops cpg_z_clk_ops = { static struct clk * __init cpg_z_clk_register(const char *name, const char *parent_name, - void __iomem *reg, + void __iomem *base, unsigned int div, unsigned int offset) { @@ -184,10 +183,11 @@ static struct clk * __init cpg_z_clk_register(const char *name, init.parent_names = &parent_name; init.num_parents = 1; - zclk->reg = reg + CPG_FRQCRC; - zclk->kick_reg = reg + CPG_FRQCRB; + zclk->reg = base + GEN3_Z_REG_OFFSET(offset); + zclk->kick_reg = base + CPG_FRQCRB; zclk->hw.init = &init; - zclk->mask = GENMASK(offset + 4, offset); + zclk->mask = GENMASK(GEN3_Z_BIT_OFFSET(offset) + 4, + GEN3_Z_BIT_OFFSET(offset)); zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ clk = clk_register(NULL, &zclk->hw); diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index a0535341b5da..02bf3785263c 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -48,8 +48,16 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) -#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ - DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) +#define DEF_GEN3_Z_OFFSET(_reg_offset, _bit_offset) \ + ((_reg_offset) << 16 | (_bit_offset) ) + +#define GEN3_Z_REG_OFFSET(_offset) ((_offset) >> 16) + +#define GEN3_Z_BIT_OFFSET(_offset) ((_offset) & 0xffff) + +#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _reg_offset, _bit_offset)\ + DEF_BASE(_name, _id, _type, _parent, .div = _div, \ + .offset = DEF_GEN3_Z_OFFSET(_reg_offset, _bit_offset)) struct rcar_gen3_cpg_pll_config { u8 extal_div; @@ -60,6 +68,7 @@ struct rcar_gen3_cpg_pll_config { u8 osc_prediv; }; +#define CPG_FRQCRC 0x0e0 #define CPG_RCKCR 0x240 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, -- 2.11.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/4] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock register offset 2019-02-28 13:52 ` [PATCH 1/4] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock register offset Simon Horman @ 2019-03-01 12:38 ` Geert Uytterhoeven 2019-03-04 9:44 ` Simon Horman 0 siblings, 1 reply; 11+ messages in thread From: Geert Uytterhoeven @ 2019-03-01 12:38 UTC (permalink / raw) To: Simon Horman; +Cc: Geert Uytterhoeven, Magnus Damm, Linux-Renesas, linux-clk Hi Simon, Thanks for your patch! On Thu, Feb 28, 2019 at 2:53 PM Simon Horman <horms+renesas@verge.net.au> wrote: > Parameterise the offset of the control register for > for Z and Z2 clocks. double "for" > This is in preparation for supporting the ZG clock on the R-Car E3 > (r8a77990), D3 (r8a7795) and RZ/G2E (r8a774c0) SoCs which uses a different D3 (r8a77995) ... use > control register to existing support for Z and Z2 clocks. > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > @@ -71,8 +71,10 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { > DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), > > /* Core Clock Outputs */ > - DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), > - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), Given "[PATCH v5 0/6] clk: renesas: r8a77990, r8a774c0: Add Z2 clock" still used CLK_TYPE_GEN3_Z2, this patch does not apply. Have you forgotten to send out v6? > + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, > + CLK_PLL0, 2, CPG_FRQCRC, 8), > + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, > + CLK_PLL2, 2, CPG_FRQCRC, 0), > DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), > DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), > DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), > --- a/drivers/clk/renesas/rcar-gen3-cpg.c > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c > @@ -166,7 +165,7 @@ static const struct clk_ops cpg_z_clk_ops = { > > static struct clk * __init cpg_z_clk_register(const char *name, > const char *parent_name, > - void __iomem *reg, > + void __iomem *base, > unsigned int div, > unsigned int offset) > { > @@ -184,10 +183,11 @@ static struct clk * __init cpg_z_clk_register(const char *name, > init.parent_names = &parent_name; > init.num_parents = 1; > > - zclk->reg = reg + CPG_FRQCRC; > - zclk->kick_reg = reg + CPG_FRQCRB; > + zclk->reg = base + GEN3_Z_REG_OFFSET(offset); > + zclk->kick_reg = base + CPG_FRQCRB; > zclk->hw.init = &init; > - zclk->mask = GENMASK(offset + 4, offset); > + zclk->mask = GENMASK(GEN3_Z_BIT_OFFSET(offset) + 4, > + GEN3_Z_BIT_OFFSET(offset)); I think the code would be easier to read if you would move the splitting of offset to the caller, and thus pass separate reg_offset and bit_offset parameters. > zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ > > clk = clk_register(NULL, &zclk->hw); > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h > index a0535341b5da..02bf3785263c 100644 > --- a/drivers/clk/renesas/rcar-gen3-cpg.h > +++ b/drivers/clk/renesas/rcar-gen3-cpg.h > @@ -48,8 +48,16 @@ enum rcar_gen3_clk_types { > DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ > (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) > > -#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ > - DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) > +#define DEF_GEN3_Z_OFFSET(_reg_offset, _bit_offset) \ > + ((_reg_offset) << 16 | (_bit_offset) ) > + > +#define GEN3_Z_REG_OFFSET(_offset) ((_offset) >> 16) > + > +#define GEN3_Z_BIT_OFFSET(_offset) ((_offset) & 0xffff) Do you think these 3 (un)marshalling macros add much value, given they're used in a single place only? > + > +#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _reg_offset, _bit_offset)\ > + DEF_BASE(_name, _id, _type, _parent, .div = _div, \ > + .offset = DEF_GEN3_Z_OFFSET(_reg_offset, _bit_offset)) > > struct rcar_gen3_cpg_pll_config { > u8 extal_div; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/4] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock register offset 2019-03-01 12:38 ` Geert Uytterhoeven @ 2019-03-04 9:44 ` Simon Horman 0 siblings, 0 replies; 11+ messages in thread From: Simon Horman @ 2019-03-04 9:44 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Geert Uytterhoeven, Magnus Damm, Linux-Renesas, linux-clk On Fri, Mar 01, 2019 at 01:38:43PM +0100, Geert Uytterhoeven wrote: > Hi Simon, > > Thanks for your patch! > > On Thu, Feb 28, 2019 at 2:53 PM Simon Horman <horms+renesas@verge.net.au> wrote: > > Parameterise the offset of the control register for > > for Z and Z2 clocks. > > double "for" > > > This is in preparation for supporting the ZG clock on the R-Car E3 > > (r8a77990), D3 (r8a7795) and RZ/G2E (r8a774c0) SoCs which uses a different > > D3 (r8a77995) ... use > > > control register to existing support for Z and Z2 clocks. > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > > --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c > > +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > > @@ -71,8 +71,10 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { > > DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), > > > > /* Core Clock Outputs */ > > - DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), > > - DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), > > Given "[PATCH v5 0/6] clk: renesas: r8a77990, r8a774c0: Add Z2 clock" > still used CLK_TYPE_GEN3_Z2, this patch does not apply. > Have you forgotten to send out v6? There was supposed to be a consolidation patch at the beginning of this series. Sorry for omitting it. > > > + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, > > + CLK_PLL0, 2, CPG_FRQCRC, 8), > > + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, > > + CLK_PLL2, 2, CPG_FRQCRC, 0), > > DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), > > DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), > > DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), > > > --- a/drivers/clk/renesas/rcar-gen3-cpg.c > > +++ b/drivers/clk/renesas/rcar-gen3-cpg.c > > > @@ -166,7 +165,7 @@ static const struct clk_ops cpg_z_clk_ops = { > > > > static struct clk * __init cpg_z_clk_register(const char *name, > > const char *parent_name, > > - void __iomem *reg, > > + void __iomem *base, > > unsigned int div, > > unsigned int offset) > > { > > @@ -184,10 +183,11 @@ static struct clk * __init cpg_z_clk_register(const char *name, > > init.parent_names = &parent_name; > > init.num_parents = 1; > > > > - zclk->reg = reg + CPG_FRQCRC; > > - zclk->kick_reg = reg + CPG_FRQCRB; > > + zclk->reg = base + GEN3_Z_REG_OFFSET(offset); > > + zclk->kick_reg = base + CPG_FRQCRB; > > zclk->hw.init = &init; > > - zclk->mask = GENMASK(offset + 4, offset); > > + zclk->mask = GENMASK(GEN3_Z_BIT_OFFSET(offset) + 4, > > + GEN3_Z_BIT_OFFSET(offset)); > > I think the code would be easier to read if you would move the splitting > of offset to the caller, and thus pass separate reg_offset and bit_offset > parameters. Sure, that sounds reasonable. > > > zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ > > > > clk = clk_register(NULL, &zclk->hw); > > diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h > > index a0535341b5da..02bf3785263c 100644 > > --- a/drivers/clk/renesas/rcar-gen3-cpg.h > > +++ b/drivers/clk/renesas/rcar-gen3-cpg.h > > @@ -48,8 +48,16 @@ enum rcar_gen3_clk_types { > > DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ > > (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) > > > > -#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ > > - DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) > > +#define DEF_GEN3_Z_OFFSET(_reg_offset, _bit_offset) \ > > + ((_reg_offset) << 16 | (_bit_offset) ) > > + > > +#define GEN3_Z_REG_OFFSET(_offset) ((_offset) >> 16) > > + > > +#define GEN3_Z_BIT_OFFSET(_offset) ((_offset) & 0xffff) > > Do you think these 3 (un)marshalling macros add much value, given they're > used in a single place only? Yes, they make things very clear to my mind. But I'm open to an alternative if you have one in mind. > > > + > > +#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _reg_offset, _bit_offset)\ > > + DEF_BASE(_name, _id, _type, _parent, .div = _div, \ > > + .offset = DEF_GEN3_Z_OFFSET(_reg_offset, _bit_offset)) > > > > struct rcar_gen3_cpg_pll_config { > > u8 extal_div; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/4] clk: renesas: r8a77990: Add ZG clock 2019-02-28 13:52 [PATCH 0/4] clk: renesas: rcar-gen3: Add ZG support for E3, D3 and RZ/G2E Simon Horman 2019-02-28 13:52 ` [PATCH 1/4] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock register offset Simon Horman @ 2019-02-28 13:52 ` Simon Horman 2019-03-01 12:52 ` Geert Uytterhoeven 2019-02-28 13:52 ` [PATCH 3/4] [RFT] clk: renesas: r8a774c0: " Simon Horman 2019-02-28 13:52 ` [PATCH 4/4] [RFT] clk: renesas: r8a77995: " Simon Horman 3 siblings, 1 reply; 11+ messages in thread From: Simon Horman @ 2019-02-28 13:52 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, linux-renesas-soc, linux-clk, Simon Horman Adds support for R-Car E3 (r8a77990) ZG clock. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- Tested on Ebisu to the extent that the clock rate is 600MHz on boot --- drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 ++ drivers/clk/renesas/rcar-gen3-cpg.c | 1 - drivers/clk/renesas/rcar-gen3-cpg.h | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 0e475dcb68b9..d0d29fc942ff 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -83,6 +83,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, CPG_FRQCRC, 8), + DEF_GEN3_Z("zg", R8A77990_CLK_ZG, CLK_TYPE_GEN3_Z, CLK_PLL0, + 8, CPG_FRQCRB, 24), DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 14a82c51682e..0d0e698442e2 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -70,7 +70,6 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, * rate - rate is adjustable. clk->rate = (parent->rate * mult / 32 ) / 2 * parent - fixed parent. No clk_set_parent support */ -#define CPG_FRQCRB 0x00000004 #define CPG_FRQCRB_KICK BIT(31) struct cpg_z_clk { diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 02bf3785263c..9525df8a835c 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -68,6 +68,7 @@ struct rcar_gen3_cpg_pll_config { u8 osc_prediv; }; +#define CPG_FRQCRB 0x004 #define CPG_FRQCRC 0x0e0 #define CPG_RCKCR 0x240 -- 2.11.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/4] clk: renesas: r8a77990: Add ZG clock 2019-02-28 13:52 ` [PATCH 2/4] clk: renesas: r8a77990: Add ZG clock Simon Horman @ 2019-03-01 12:52 ` Geert Uytterhoeven 2019-03-04 9:45 ` Simon Horman 0 siblings, 1 reply; 11+ messages in thread From: Geert Uytterhoeven @ 2019-03-01 12:52 UTC (permalink / raw) To: Simon Horman; +Cc: Geert Uytterhoeven, Magnus Damm, Linux-Renesas, linux-clk Hi Simon, On Thu, Feb 28, 2019 at 2:52 PM Simon Horman <horms+renesas@verge.net.au> wrote: > Adds support for R-Car E3 (r8a77990) ZG clock. > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > --- > Tested on Ebisu to the extent that the clock rate is 600MHz on boot > --- > drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 ++ > drivers/clk/renesas/rcar-gen3-cpg.c | 1 - > drivers/clk/renesas/rcar-gen3-cpg.h | 1 + > 3 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c > index 0e475dcb68b9..d0d29fc942ff 100644 > --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c > @@ -83,6 +83,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { > DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), > DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, > 4, CPG_FRQCRC, 8), > + DEF_GEN3_Z("zg", R8A77990_CLK_ZG, CLK_TYPE_GEN3_Z, CLK_PLL0, > + 8, CPG_FRQCRB, 24), While this approach may be correct for R-Car H3, M3-W, and M3-N, this is not correct for R-Car E3, due to the presence of Spread Spectrum Clock Generator support: - When SCCG is enabled (MD12=1), the parent clock is either S0 or S1, with only 2 or 3 (out of 32) supported dividers, - When SCCG is disabled (MD12=0), the parent clock is PLL0, with only 2 (out of 32) supported dividers. So I'm afraid the ZG clock on SCCG-capable SoCs needs its own very special clock type. This applies also to R-Car D3 and RZ/G2E. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/4] clk: renesas: r8a77990: Add ZG clock 2019-03-01 12:52 ` Geert Uytterhoeven @ 2019-03-04 9:45 ` Simon Horman 2019-03-04 10:04 ` Geert Uytterhoeven 0 siblings, 1 reply; 11+ messages in thread From: Simon Horman @ 2019-03-04 9:45 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Geert Uytterhoeven, Magnus Damm, Linux-Renesas, linux-clk On Fri, Mar 01, 2019 at 01:52:50PM +0100, Geert Uytterhoeven wrote: > Hi Simon, > > On Thu, Feb 28, 2019 at 2:52 PM Simon Horman <horms+renesas@verge.net.au> wrote: > > Adds support for R-Car E3 (r8a77990) ZG clock. > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > --- > > Tested on Ebisu to the extent that the clock rate is 600MHz on boot > > --- > > drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 ++ > > drivers/clk/renesas/rcar-gen3-cpg.c | 1 - > > drivers/clk/renesas/rcar-gen3-cpg.h | 1 + > > 3 files changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c > > index 0e475dcb68b9..d0d29fc942ff 100644 > > --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c > > +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c > > @@ -83,6 +83,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { > > DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), > > DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, > > 4, CPG_FRQCRC, 8), > > + DEF_GEN3_Z("zg", R8A77990_CLK_ZG, CLK_TYPE_GEN3_Z, CLK_PLL0, > > + 8, CPG_FRQCRB, 24), > > While this approach may be correct for R-Car H3, M3-W, and M3-N, this is > not correct for R-Car E3, due to the presence of Spread Spectrum Clock > Generator support: > - When SCCG is enabled (MD12=1), the parent clock is either S0 or S1, > with only 2 or 3 (out of 32) supported dividers, > - When SCCG is disabled (MD12=0), the parent clock is PLL0, with only > 2 (out of 32) supported dividers. > > So I'm afraid the ZG clock on SCCG-capable SoCs needs its own very special > clock type. Thanks for pointing this out, I'll investigate further. > > This applies also to R-Car D3 and RZ/G2E. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/4] clk: renesas: r8a77990: Add ZG clock 2019-03-04 9:45 ` Simon Horman @ 2019-03-04 10:04 ` Geert Uytterhoeven 0 siblings, 0 replies; 11+ messages in thread From: Geert Uytterhoeven @ 2019-03-04 10:04 UTC (permalink / raw) To: Simon Horman; +Cc: Geert Uytterhoeven, Magnus Damm, Linux-Renesas, linux-clk Hi Simon, On Mon, Mar 4, 2019 at 10:45 AM Simon Horman <horms@verge.net.au> wrote: > On Fri, Mar 01, 2019 at 01:52:50PM +0100, Geert Uytterhoeven wrote: > > On Thu, Feb 28, 2019 at 2:52 PM Simon Horman <horms+renesas@verge.net.au> wrote: > > > Adds support for R-Car E3 (r8a77990) ZG clock. > > > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > > --- > > > Tested on Ebisu to the extent that the clock rate is 600MHz on boot > > > --- > > > drivers/clk/renesas/r8a77990-cpg-mssr.c | 2 ++ > > > drivers/clk/renesas/rcar-gen3-cpg.c | 1 - > > > drivers/clk/renesas/rcar-gen3-cpg.h | 1 + > > > 3 files changed, 3 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c > > > index 0e475dcb68b9..d0d29fc942ff 100644 > > > --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c > > > +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c > > > @@ -83,6 +83,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { > > > DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), > > > DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, > > > 4, CPG_FRQCRC, 8), > > > + DEF_GEN3_Z("zg", R8A77990_CLK_ZG, CLK_TYPE_GEN3_Z, CLK_PLL0, > > > + 8, CPG_FRQCRB, 24), > > > > While this approach may be correct for R-Car H3, M3-W, and M3-N, this is > > not correct for R-Car E3, due to the presence of Spread Spectrum Clock > > Generator support: > > - When SCCG is enabled (MD12=1), the parent clock is either S0 or S1, > > with only 2 or 3 (out of 32) supported dividers, > > - When SCCG is disabled (MD12=0), the parent clock is PLL0, with only > > 2 (out of 32) supported dividers. > > > > So I'm afraid the ZG clock on SCCG-capable SoCs needs its own very special > > clock type. > > Thanks for pointing this out, I'll investigate further. Given MD12 is sampled a reset time, there's no need to handle both cases at runtime. I.e. if MD12=0, you can register a simple clock with one parent and two dividers. If MD12=1, you can register a more complex custom clock with two parents and 2 or 3 dividers. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/4] [RFT] clk: renesas: r8a774c0: Add ZG clock 2019-02-28 13:52 [PATCH 0/4] clk: renesas: rcar-gen3: Add ZG support for E3, D3 and RZ/G2E Simon Horman 2019-02-28 13:52 ` [PATCH 1/4] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock register offset Simon Horman 2019-02-28 13:52 ` [PATCH 2/4] clk: renesas: r8a77990: Add ZG clock Simon Horman @ 2019-02-28 13:52 ` Simon Horman 2019-03-01 10:24 ` Simon Horman 2019-02-28 13:52 ` [PATCH 4/4] [RFT] clk: renesas: r8a77995: " Simon Horman 3 siblings, 1 reply; 11+ messages in thread From: Simon Horman @ 2019-02-28 13:52 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, linux-renesas-soc, linux-clk, Simon Horman Adds support for R-Car RZ/G2E (r8a774c0) ZG clock. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> --- Compile tested only --- drivers/clk/renesas/r8a774c0-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index d9130723d6c8..2c12bfddca95 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -81,6 +81,8 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, CPG_FRQCRC, 8), + DEF_GEN3_Z("zg", R8A774C0_CLK_ZG, CLK_TYPE_GEN3_Z, + CLK_PLL0, 8, CPG_FRQCRB, 24), DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1), -- 2.11.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 3/4] [RFT] clk: renesas: r8a774c0: Add ZG clock 2019-02-28 13:52 ` [PATCH 3/4] [RFT] clk: renesas: r8a774c0: " Simon Horman @ 2019-03-01 10:24 ` Simon Horman 0 siblings, 0 replies; 11+ messages in thread From: Simon Horman @ 2019-03-01 10:24 UTC (permalink / raw) To: Geert Uytterhoeven; +Cc: Magnus Damm, linux-renesas-soc, linux-clk On Thu, Feb 28, 2019 at 02:52:45PM +0100, Simon Horman wrote: > Adds support for R-Car RZ/G2E (r8a774c0) ZG clock. > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > Tested-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Apologies, the Tested-by tag should not be present above. It is a cut-and-paste error. > --- > Compile tested only > --- > drivers/clk/renesas/r8a774c0-cpg-mssr.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c > index d9130723d6c8..2c12bfddca95 100644 > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c > @@ -81,6 +81,8 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = { > DEF_FIXED("za8", R8A774C0_CLK_ZA8, CLK_PLL0D8, 1, 1), > DEF_GEN3_Z("z2", R8A774C0_CLK_Z2, CLK_TYPE_GEN3_Z, > CLK_PLL0, 4, CPG_FRQCRC, 8), > + DEF_GEN3_Z("zg", R8A774C0_CLK_ZG, CLK_TYPE_GEN3_Z, > + CLK_PLL0, 8, CPG_FRQCRB, 24), > DEF_FIXED("ztr", R8A774C0_CLK_ZTR, CLK_PLL1, 6, 1), > DEF_FIXED("zt", R8A774C0_CLK_ZT, CLK_PLL1, 4, 1), > DEF_FIXED("zx", R8A774C0_CLK_ZX, CLK_PLL1, 3, 1), > -- > 2.11.0 > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 4/4] [RFT] clk: renesas: r8a77995: Add ZG clock 2019-02-28 13:52 [PATCH 0/4] clk: renesas: rcar-gen3: Add ZG support for E3, D3 and RZ/G2E Simon Horman ` (2 preceding siblings ...) 2019-02-28 13:52 ` [PATCH 3/4] [RFT] clk: renesas: r8a774c0: " Simon Horman @ 2019-02-28 13:52 ` Simon Horman 3 siblings, 0 replies; 11+ messages in thread From: Simon Horman @ 2019-02-28 13:52 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Magnus Damm, linux-renesas-soc, linux-clk, Simon Horman Adds support for R-Car D3 (r8a77995) ZG clock. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- Compile tested only --- drivers/clk/renesas/r8a77995-cpg-mssr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index eee3874865a9..0a13a1a7a909 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -76,6 +76,8 @@ static const struct cpg_core_clk r8a77995_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), + DEF_GEN3_Z("zg", R8A77995_CLK_ZG, CLK_TYPE_GEN3_Z, CLK_PLL0, + 5, CPG_FRQCRB, 24), DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1), -- 2.11.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-03-04 10:05 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-02-28 13:52 [PATCH 0/4] clk: renesas: rcar-gen3: Add ZG support for E3, D3 and RZ/G2E Simon Horman 2019-02-28 13:52 ` [PATCH 1/4] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock register offset Simon Horman 2019-03-01 12:38 ` Geert Uytterhoeven 2019-03-04 9:44 ` Simon Horman 2019-02-28 13:52 ` [PATCH 2/4] clk: renesas: r8a77990: Add ZG clock Simon Horman 2019-03-01 12:52 ` Geert Uytterhoeven 2019-03-04 9:45 ` Simon Horman 2019-03-04 10:04 ` Geert Uytterhoeven 2019-02-28 13:52 ` [PATCH 3/4] [RFT] clk: renesas: r8a774c0: " Simon Horman 2019-03-01 10:24 ` Simon Horman 2019-02-28 13:52 ` [PATCH 4/4] [RFT] clk: renesas: r8a77995: " Simon Horman
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