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From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Magnus Damm <magnus.damm@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Prabhakar <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's
Date: Wed, 9 Jun 2021 09:27:05 +0200	[thread overview]
Message-ID: <CAMuHMdVkKhD3kU-DtPzrGfNf4Sn5Ht09Z1N0scwx1XJoG-F6Mg@mail.gmail.com> (raw)
In-Reply-To: <20210604180933.16754-3-prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi Prabhakar,

On Fri, Jun 4, 2021 at 8:09 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add support for reading the LSI DEVID register which is present in
> SYSC block of RZ/G2{L,LC} SoC's.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/drivers/soc/renesas/renesas-soc.c
> +++ b/drivers/soc/renesas/renesas-soc.c
> @@ -56,6 +56,11 @@ static const struct renesas_family fam_rzg2 __initconst __maybe_unused = {
>         .reg    = 0xfff00044,           /* PRR (Product Register) */
>  };
>
> +static const struct renesas_family fam_rzg2l __initconst __maybe_unused = {
> +       .name   = "RZ/G2L",
> +       .reg    = 0x11020a04,

Please don't add hardcoded register addresses for new SoCs (i.e. drop
".reg").  The "renesas,r9a07g044-sysc" is always present.
And if it were missing, the hardcoded fallback would lead into the
classic CCCR/PRR scheme, which is not correct for RZ/G2L...

> @@ -348,6 +361,25 @@ static int __init renesas_soc_init(void)
>                 goto done;
>         }
>
> +       np = of_find_compatible_node(NULL, NULL, "renesas,r9a07g044-sysc");
> +       if (np) {
> +               of_node_put(np);
> +               chipid = ioremap(family->reg, 4);

Just use of_iomap(np, 0)...

> +
> +               if (chipid) {
> +                       product = readl(chipid);

... and add the DEVID offset within the SYSC block here.

> +                       iounmap(chipid);
> +
> +                       if (soc->id && (product & 0xfffffff) != soc->id) {
> +                               pr_warn("SoC mismatch (product = 0x%x)\n",
> +                                       product);
> +                               return -ENODEV;
> +                       }
> +               }
> +
> +               goto done;
> +       }
> +
>         /* Try PRR first, then hardcoded fallback */
>         np = of_find_compatible_node(NULL, NULL, "renesas,prr");
>         if (np) {

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

  reply	other threads:[~2021-06-09  7:27 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-04 18:09 [PATCH 0/3] SoC identification support for RZ/G2L Lad Prabhakar
2021-06-04 18:09 ` [PATCH 1/3] dt-bindings: power: renesas,rzg2l-sysc: Add DT binding documentation for SYSC controller Lad Prabhakar
2021-06-09  7:19   ` Geert Uytterhoeven
2021-06-04 18:09 ` [PATCH 2/3] soc: renesas: Add support to read LSI DEVID register of RZ/G2{L,LC} SoC's Lad Prabhakar
2021-06-09  7:27   ` Geert Uytterhoeven [this message]
2021-06-09 15:49     ` Lad, Prabhakar
2021-06-09 15:57       ` Geert Uytterhoeven
2021-06-04 18:09 ` [PATCH 3/3] arm64: dts: renesas: r9a07g044: Add SYSC node to RZ/G2L SoC DTSI Lad Prabhakar
2021-06-09  7:28   ` Geert Uytterhoeven

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