[PATCH/RFC 00/15] arm64: renesas: Add-R-Car S4-8 Pin control support

[PATCH/RFC 00/15] arm64: renesas: Add-R-Car S4-8 Pin control support

[Geert Uytterhoeven]

	Hi all,

This patch series adds pin control support for the Renesas R-Car S4-8
Soc on the Spider board, and enables pin control for the serial console.
It is based on patches in the BSP by LUU HOAI, with many changes on top
(see the individual patches).

This series is marked as an RFC because of 2 reasons:
  1. PFC register banks 4-7 do not seem to be accessible as-is using
     either the Control Domain (0xffd9....) or Application Domain
     (0xdfd9....) addresses, so currently you cannot configure pins
     controlled by these banks.
     How to make the Control Domain release the bus guard, so the
     registers become accessible?
  2. It this has been tested only lightly with remote access.

For testing, this series and its dependencies can be found at[1].

Thanks for your comments!

[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/r8a779f0-pfc-v1

Geert Uytterhoeven (14):
  clk: renesas: r8a779f0: Add PFC clock
  pinctrl: renesas: Add PORT_GP_CFG_19 macros
  pinctrl: renesas: Initial R8A779F0 PFC support
  pinctrl: renesas: r8a779f0: Add SCIF pins, groups, and functions
  pinctrl: renesas: r8a779f0: Add I2C pins, groups, and functions
  pinctrl: renesas: r8a779f0: Add HSCIF pins, groups, and functions
  pinctrl: renesas: r8a779f0: Add INTC-EX pins, groups, and function
  pinctrl: renesas: r8a779f0: Add MMC pins, groups, and function
  pinctrl: renesas: r8a779f0: Add MSIOF pins, groups, and functions
  pinctrl: renesas: r8a779f0: Add PCIe pins, groups, and function
  pinctrl: renesas: r8a779f0: Add QSPI pins, groups, and functions
  pinctrl: renesas: r8a779f0: Add Ethernet pins, groups, and functions
  arm64: dts: renesas: r8a779f0: Add pinctrl device node
  arm64: dts: renesas: spider: Complete SCIF3 description

LUU HOAI (1):
  dt-bindings: pinctrl: renesas,pfc: Document r8a779f0 support

 .../bindings/pinctrl/renesas,pfc.yaml         |    1 +
 .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi |   23 +
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi     |    8 +
 drivers/clk/renesas/r8a779f0-cpg-mssr.c       |    1 +
 drivers/pinctrl/renesas/Kconfig               |    5 +
 drivers/pinctrl/renesas/Makefile              |    1 +
 drivers/pinctrl/renesas/core.c                |    6 +
 drivers/pinctrl/renesas/pfc-r8a779f0.c        | 3417 +++++++++++++++++
 drivers/pinctrl/renesas/sh_pfc.h              |   19 +-
 9 files changed, 3479 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pinctrl/renesas/pfc-r8a779f0.c

-- 
2.25.1

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

[PATCH/RFC 01/15] clk: renesas: r8a779f0: Add PFC clock

[Geert Uytterhoeven]

Add the module clock used by the Pin Function (PFC/GPIO) controller
on the Renesas R-Car S4-8 (R8A779F0) SoC.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index e48c5af7341454a7..16271b8c3ed8ea31 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -122,6 +122,7 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
 	DEF_MOD("sys-dmac0",	709,	R8A779F0_CLK_S0D3_PER),
 	DEF_MOD("sys-dmac1",	710,	R8A779F0_CLK_S0D3_PER),
 	DEF_MOD("wdt",		907,	R8A779F0_CLK_R),
+	DEF_MOD("pfc0",		915,	R8A779F0_CLK_CL16M),
 };
 
 static const unsigned int r8a779f0_crit_mod_clks[] __initconst = {
-- 
2.25.1

[PATCH/RFC 02/15] dt-bindings: pinctrl: renesas,pfc: Document r8a779f0 support

[Geert Uytterhoeven]

From: LUU HOAI <hoai.luu.ub@renesas.com>

Document Pin Function Controller (PFC) support for the Renesas R-Car
S4-8 (R8A779F0) SoC.

Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
index 8548e3639b7549da..2a57df75d832f14b 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml
@@ -44,6 +44,7 @@ properties:
       - renesas,pfc-r8a77990    # R-Car E3
       - renesas,pfc-r8a77995    # R-Car D3
       - renesas,pfc-r8a779a0    # R-Car V3U
+      - renesas,pfc-r8a779f0    # R-Car S4-8
       - renesas,pfc-sh73a0      # SH-Mobile AG5
 
   reg:
-- 
2.25.1

[PATCH/RFC 03/15] pinctrl: renesas: Add PORT_GP_CFG_19 macros

[Geert Uytterhoeven]

Add PORT_GP_CFG_19() and PORT_GP_19() helper macros, to be used by the
r8a779f0 subdriver.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to the BSP:
  - Rework PORT_GP_CFG_20() on top of the new PORT_GP_CFG_19().
---
 drivers/pinctrl/renesas/sh_pfc.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index fba4217acb3fa3f2..f9852702a697a089 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -525,9 +525,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
 	PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
 #define PORT_GP_18(bank, fn, sfx)	PORT_GP_CFG_18(bank, fn, sfx, 0)
 
-#define PORT_GP_CFG_20(bank, fn, sfx, cfg)				\
+#define PORT_GP_CFG_19(bank, fn, sfx, cfg)				\
 	PORT_GP_CFG_18(bank, fn, sfx, cfg),				\
-	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg),				\
+	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg)
+#define PORT_GP_19(bank, fn, sfx)	PORT_GP_CFG_19(bank, fn, sfx, 0)
+
+#define PORT_GP_CFG_20(bank, fn, sfx, cfg)				\
+	PORT_GP_CFG_19(bank, fn, sfx, cfg),				\
 	PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
 #define PORT_GP_20(bank, fn, sfx)	PORT_GP_CFG_20(bank, fn, sfx, 0)
 
-- 
2.25.1

[PATCH/RFC 05/15] pinctrl: renesas: r8a779f0: Add SCIF pins, groups, and functions

[Geert Uytterhoeven]

Add pins, groups, and functions for the Serial Communication Interfaces
with FIFO (SCIF) on the Renesas R-Car S4-8 (R8A779F0) SoC.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 147 +++++++++++++++++++++++++
 1 file changed, 147 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 1598aa6ebc34f8a8..ba0a84b0acd24fbe 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1242,10 +1242,157 @@ static const struct sh_pfc_pin pinmux_pins[] = {
 	PINMUX_GPIO_GP_ALL(),
 };
 
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+	/* RX0, TX0 */
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int scif0_data_mux[] = {
+	RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+	/* SCK0 */
+	RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scif0_clk_mux[] = {
+	SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+	/* RTS0#, CTS0# */
+	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+	RTS0_N_MARK, CTS0_N_MARK,
+};
+
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+	/* RX1, TX1 */
+	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+};
+static const unsigned int scif1_data_mux[] = {
+	RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+	/* SCK1 */
+	RCAR_GP_PIN(0, 14),
+};
+static const unsigned int scif1_clk_mux[] = {
+	SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+	/* RTS1#, CTS1# */
+	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+	RTS1_N_MARK, CTS1_N_MARK,
+};
+
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+	/* RX3, TX3 */
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+};
+static const unsigned int scif3_data_mux[] = {
+	RX3_MARK, TX3_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+	/* SCK3 */
+	RCAR_GP_PIN(0, 1),
+};
+static const unsigned int scif3_clk_mux[] = {
+	SCK3_MARK,
+};
+static const unsigned int scif3_ctrl_pins[] = {
+	/* RTS3#, CTS3# */
+	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
+};
+static const unsigned int scif3_ctrl_mux[] = {
+	RTS3_N_MARK, CTS3_N_MARK,
+};
+
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+	/* RX4, TX4 */
+	RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
+};
+static const unsigned int scif4_data_mux[] = {
+	RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+	/* SCK4 */
+	RCAR_GP_PIN(1, 5),
+};
+static const unsigned int scif4_clk_mux[] = {
+	SCK4_MARK,
+};
+static const unsigned int scif4_ctrl_pins[] = {
+	/* RTS4#, CTS4# */
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int scif4_ctrl_mux[] = {
+	RTS4_N_MARK, CTS4_N_MARK,
+};
+
+/* - SCIF Clock ------------------------------------------------------------- */
+static const unsigned int scif_clk_pins[] = {
+	/* SCIF_CLK */
+	RCAR_GP_PIN(0, 0),
+};
+static const unsigned int scif_clk_mux[] = {
+	SCIF_CLK_MARK,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(scif0_data),
+	SH_PFC_PIN_GROUP(scif0_clk),
+	SH_PFC_PIN_GROUP(scif0_ctrl),
+	SH_PFC_PIN_GROUP(scif1_data),
+	SH_PFC_PIN_GROUP(scif1_clk),
+	SH_PFC_PIN_GROUP(scif1_ctrl),
+	SH_PFC_PIN_GROUP(scif3_data),
+	SH_PFC_PIN_GROUP(scif3_clk),
+	SH_PFC_PIN_GROUP(scif3_ctrl),
+	SH_PFC_PIN_GROUP(scif4_data),
+	SH_PFC_PIN_GROUP(scif4_clk),
+	SH_PFC_PIN_GROUP(scif4_ctrl),
+	SH_PFC_PIN_GROUP(scif_clk),
+};
+
+static const char * const scif0_groups[] = {
+	"scif0_data",
+	"scif0_clk",
+	"scif0_ctrl",
+};
+
+static const char * const scif1_groups[] = {
+	"scif1_data",
+	"scif1_clk",
+	"scif1_ctrl",
+};
+
+static const char * const scif3_groups[] = {
+	"scif3_data",
+	"scif3_clk",
+	"scif3_ctrl",
+};
+
+static const char * const scif4_groups[] = {
+	"scif4_data",
+	"scif4_clk",
+	"scif4_ctrl",
+};
+
+static const char * const scif_clk_groups[] = {
+	"scif_clk",
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(scif0),
+	SH_PFC_FUNCTION(scif1),
+	SH_PFC_FUNCTION(scif3),
+	SH_PFC_FUNCTION(scif4),
+	SH_PFC_FUNCTION(scif_clk),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.25.1

[PATCH/RFC 06/15] pinctrl: renesas: r8a779f0: Add I2C pins, groups, and functions

[Geert Uytterhoeven]

Add pins, groups, and functions for the I2C Bus Interfaces (I2C) on the
Renesas R-Car S4-8 (R8A779F0) SoC.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 90 ++++++++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index ba0a84b0acd24fbe..a76355305367b0f0 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1242,6 +1242,60 @@ static const struct sh_pfc_pin pinmux_pins[] = {
 	PINMUX_GPIO_GP_ALL(),
 };
 
+/* - I2C0 ------------------------------------------------------------------- */
+static const unsigned int i2c0_pins[] = {
+	/* SDA0, SCL0 */
+	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
+};
+static const unsigned int i2c0_mux[] = {
+	SDA0_MARK, SCL0_MARK,
+};
+
+/* - I2C1 ------------------------------------------------------------------- */
+static const unsigned int i2c1_pins[] = {
+	/* SDA1, SCL1 */
+	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
+};
+static const unsigned int i2c1_mux[] = {
+	SDA1_MARK, SCL1_MARK,
+};
+
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_pins[] = {
+	/* SDA2, SCL2 */
+	RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4),
+};
+static const unsigned int i2c2_mux[] = {
+	SDA2_MARK, SCL2_MARK,
+};
+
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_pins[] = {
+	/* SDA3, SCL3 */
+	RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
+};
+static const unsigned int i2c3_mux[] = {
+	SDA3_MARK, SCL3_MARK,
+};
+
+/* - I2C4 ------------------------------------------------------------------- */
+static const unsigned int i2c4_pins[] = {
+	/* SDA4, SCL4 */
+	RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
+};
+static const unsigned int i2c4_mux[] = {
+	SDA4_MARK, SCL4_MARK,
+};
+
+/* - I2C5 ------------------------------------------------------------------- */
+static const unsigned int i2c5_pins[] = {
+	/* SDA5, SCL5 */
+	RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
+};
+static const unsigned int i2c5_mux[] = {
+	SDA5_MARK, SCL5_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX0, TX0 */
@@ -1344,6 +1398,12 @@ static const unsigned int scif_clk_mux[] = {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(i2c0),
+	SH_PFC_PIN_GROUP(i2c1),
+	SH_PFC_PIN_GROUP(i2c2),
+	SH_PFC_PIN_GROUP(i2c3),
+	SH_PFC_PIN_GROUP(i2c4),
+	SH_PFC_PIN_GROUP(i2c5),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1359,6 +1419,30 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scif_clk),
 };
 
+static const char * const i2c0_groups[] = {
+	"i2c0",
+};
+
+static const char * const i2c1_groups[] = {
+	"i2c1",
+};
+
+static const char * const i2c2_groups[] = {
+	"i2c2",
+};
+
+static const char * const i2c3_groups[] = {
+	"i2c3",
+};
+
+static const char * const i2c4_groups[] = {
+	"i2c4",
+};
+
+static const char * const i2c5_groups[] = {
+	"i2c5",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -1388,6 +1472,12 @@ static const char * const scif_clk_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(i2c0),
+	SH_PFC_FUNCTION(i2c1),
+	SH_PFC_FUNCTION(i2c2),
+	SH_PFC_FUNCTION(i2c3),
+	SH_PFC_FUNCTION(i2c4),
+	SH_PFC_FUNCTION(i2c5),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),
-- 
2.25.1

[PATCH/RFC 07/15] pinctrl: renesas: r8a779f0: Add HSCIF pins, groups, and functions

[Geert Uytterhoeven]

Add pins, groups, and functions for the High Speed Serial Communication
Interfaces with FIFO (HSCIF) on the Renesas R-Car S4-8 (R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to the BSP:
  - Add HSCIF[23] pin groups and functions.
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 132 +++++++++++++++++++++++++
 1 file changed, 132 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index a76355305367b0f0..71dbe7dae03b2463 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1242,6 +1242,98 @@ static const struct sh_pfc_pin pinmux_pins[] = {
 	PINMUX_GPIO_GP_ALL(),
 };
 
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+	/* HRX0, HTX0 */
+	RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
+};
+static const unsigned int hscif0_data_mux[] = {
+	HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+	/* HSCK0 */
+	RCAR_GP_PIN(0, 1),
+};
+static const unsigned int hscif0_clk_mux[] = {
+	HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+	/* HRTS0#, HCTS0# */
+	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+	HRTS0_N_MARK, HCTS0_N_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+	/* HRX1, HTX1 */
+	RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
+};
+static const unsigned int hscif1_data_mux[] = {
+	HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+	/* HSCK1 */
+	RCAR_GP_PIN(0, 8),
+};
+static const unsigned int hscif1_clk_mux[] = {
+	HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+	/* HRTS1#, HCTS1# */
+	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+	HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+	/* HRX2, HTX2 */
+	RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
+};
+static const unsigned int hscif2_data_mux[] = {
+	HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+	/* HSCK2 */
+	RCAR_GP_PIN(1, 0),
+};
+static const unsigned int hscif2_clk_mux[] = {
+	HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+	/* HRTS2#, HCTS2# */
+	RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+	HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+	/* HRX3, HTX3 */
+	RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
+};
+static const unsigned int hscif3_data_mux[] = {
+	HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+	/* HSCK3 */
+	RCAR_GP_PIN(0, 14),
+};
+static const unsigned int hscif3_clk_mux[] = {
+	HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+	/* HRTS3#, HCTS3# */
+	RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+	HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
 /* - I2C0 ------------------------------------------------------------------- */
 static const unsigned int i2c0_pins[] = {
 	/* SDA0, SCL0 */
@@ -1398,6 +1490,18 @@ static const unsigned int scif_clk_mux[] = {
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+	SH_PFC_PIN_GROUP(hscif0_data),
+	SH_PFC_PIN_GROUP(hscif0_clk),
+	SH_PFC_PIN_GROUP(hscif0_ctrl),
+	SH_PFC_PIN_GROUP(hscif1_data),
+	SH_PFC_PIN_GROUP(hscif1_clk),
+	SH_PFC_PIN_GROUP(hscif1_ctrl),
+	SH_PFC_PIN_GROUP(hscif2_data),
+	SH_PFC_PIN_GROUP(hscif2_clk),
+	SH_PFC_PIN_GROUP(hscif2_ctrl),
+	SH_PFC_PIN_GROUP(hscif3_data),
+	SH_PFC_PIN_GROUP(hscif3_clk),
+	SH_PFC_PIN_GROUP(hscif3_ctrl),
 	SH_PFC_PIN_GROUP(i2c0),
 	SH_PFC_PIN_GROUP(i2c1),
 	SH_PFC_PIN_GROUP(i2c2),
@@ -1419,6 +1523,30 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scif_clk),
 };
 
+static const char * const hscif0_groups[] = {
+	"hscif0_data",
+	"hscif0_clk",
+	"hscif0_ctrl",
+};
+
+static const char * const hscif1_groups[] = {
+	"hscif1_data",
+	"hscif1_clk",
+	"hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+	"hscif2_data",
+	"hscif2_clk",
+	"hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+	"hscif3_data",
+	"hscif3_clk",
+	"hscif3_ctrl",
+};
+
 static const char * const i2c0_groups[] = {
 	"i2c0",
 };
@@ -1472,6 +1600,10 @@ static const char * const scif_clk_groups[] = {
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
+	SH_PFC_FUNCTION(hscif0),
+	SH_PFC_FUNCTION(hscif1),
+	SH_PFC_FUNCTION(hscif2),
+	SH_PFC_FUNCTION(hscif3),
 	SH_PFC_FUNCTION(i2c0),
 	SH_PFC_FUNCTION(i2c1),
 	SH_PFC_FUNCTION(i2c2),
-- 
2.25.1

[PATCH/RFC 08/15] pinctrl: renesas: r8a779f0: Add INTC-EX pins, groups, and function

[Geert Uytterhoeven]

Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the Renesas R-Car S4-8 (R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to the BSP:
  - Add IRQ[45] pin groups.
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 61 ++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 71dbe7dae03b2463..a326e134216773ec 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1388,6 +1388,51 @@ static const unsigned int i2c5_mux[] = {
 	SDA5_MARK, SCL5_MARK,
 };
 
+
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+	/* IRQ0 */
+	RCAR_GP_PIN(0, 17),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+	IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+	/* IRQ1 */
+	RCAR_GP_PIN(0, 18),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+	IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+	/* IRQ2 */
+	RCAR_GP_PIN(0, 19),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+	IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+	/* IRQ3 */
+	RCAR_GP_PIN(0, 20),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+	IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+	/* IRQ4 */
+	RCAR_GP_PIN(0, 11),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+	IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+	/* IRQ5 */
+	RCAR_GP_PIN(0, 15),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+	IRQ5_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX0, TX0 */
@@ -1508,6 +1553,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(i2c3),
 	SH_PFC_PIN_GROUP(i2c4),
 	SH_PFC_PIN_GROUP(i2c5),
+	SH_PFC_PIN_GROUP(intc_ex_irq0),
+	SH_PFC_PIN_GROUP(intc_ex_irq1),
+	SH_PFC_PIN_GROUP(intc_ex_irq2),
+	SH_PFC_PIN_GROUP(intc_ex_irq3),
+	SH_PFC_PIN_GROUP(intc_ex_irq4),
+	SH_PFC_PIN_GROUP(intc_ex_irq5),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1571,6 +1622,15 @@ static const char * const i2c5_groups[] = {
 	"i2c5",
 };
 
+static const char * const intc_ex_groups[] = {
+	"intc_ex_irq0",
+	"intc_ex_irq1",
+	"intc_ex_irq2",
+	"intc_ex_irq3",
+	"intc_ex_irq4",
+	"intc_ex_irq5",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -1610,6 +1670,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(i2c3),
 	SH_PFC_FUNCTION(i2c4),
 	SH_PFC_FUNCTION(i2c5),
+	SH_PFC_FUNCTION(intc_ex),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),
-- 
2.25.1

[PATCH/RFC 09/15] pinctrl: renesas: r8a779f0: Add MMC pins, groups, and function

[Geert Uytterhoeven]

Add pins, groups, and function for the MMC interface on the Renesas
R-Car S4-8 (R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "[PATCH 00/60] pinctrl: renesas: Share more pin group
data"[1].

Changes compared to the BSP:
  - Share MMC pin group data.

[1] https://lore.kernel.org/r/cover.1640269757.git.geert+renesas@glider.be
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 61 ++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index a326e134216773ec..912c14c9a5823d34 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1433,6 +1433,49 @@ static const unsigned int intc_ex_irq5_mux[] = {
 	IRQ5_MARK,
 };
 
+/* - MMC -------------------------------------------------------------------- */
+static const unsigned int mmc_data_pins[] = {
+	/* MMC_SD_D[0:3], MMC_D[4:7] */
+	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+	RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
+	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
+	RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int mmc_data_mux[] = {
+	MMC_SD_D0_MARK, MMC_SD_D1_MARK,
+	MMC_SD_D2_MARK, MMC_SD_D3_MARK,
+	MMC_D4_MARK, MMC_D5_MARK,
+	MMC_D6_MARK, MMC_D7_MARK,
+};
+static const unsigned int mmc_ctrl_pins[] = {
+	/* MMC_SD_CLK, MMC_SD_CMD */
+	RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int mmc_ctrl_mux[] = {
+	MMC_SD_CLK_MARK, MMC_SD_CMD_MARK,
+};
+static const unsigned int mmc_cd_pins[] = {
+	/* SD_CD */
+	RCAR_GP_PIN(1, 23),
+};
+static const unsigned int mmc_cd_mux[] = {
+	SD_CD_MARK,
+};
+static const unsigned int mmc_wp_pins[] = {
+	/* SD_WP */
+	RCAR_GP_PIN(1, 24),
+};
+static const unsigned int mmc_wp_mux[] = {
+	SD_WP_MARK,
+};
+static const unsigned int mmc_ds_pins[] = {
+	/* MMC_DS */
+	RCAR_GP_PIN(1, 20),
+};
+static const unsigned int mmc_ds_mux[] = {
+	MMC_DS_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX0, TX0 */
@@ -1559,6 +1602,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(intc_ex_irq3),
 	SH_PFC_PIN_GROUP(intc_ex_irq4),
 	SH_PFC_PIN_GROUP(intc_ex_irq5),
+	BUS_DATA_PIN_GROUP(mmc_data, 1),
+	BUS_DATA_PIN_GROUP(mmc_data, 4),
+	BUS_DATA_PIN_GROUP(mmc_data, 8),
+	SH_PFC_PIN_GROUP(mmc_ctrl),
+	SH_PFC_PIN_GROUP(mmc_cd),
+	SH_PFC_PIN_GROUP(mmc_wp),
+	SH_PFC_PIN_GROUP(mmc_ds),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1631,6 +1681,16 @@ static const char * const intc_ex_groups[] = {
 	"intc_ex_irq5",
 };
 
+static const char * const mmc_groups[] = {
+	"mmc_data1",
+	"mmc_data4",
+	"mmc_data8",
+	"mmc_ctrl",
+	"mmc_cd",
+	"mmc_wp",
+	"mmc_ds",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -1671,6 +1731,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(i2c4),
 	SH_PFC_FUNCTION(i2c5),
 	SH_PFC_FUNCTION(intc_ex),
+	SH_PFC_FUNCTION(mmc),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),
-- 
2.25.1

[PATCH/RFC 10/15] pinctrl: renesas: r8a779f0: Add MSIOF pins, groups, and functions

[Geert Uytterhoeven]

Add pins, groups, and function for the Clock-Synchronized Serial
Interfaces with FIFO (MSIOF) on the Renesas R-Car S4-8 (R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to the BSP:
  - Add MSIOF[123] pin groups and functions.
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 240 +++++++++++++++++++++++++
 1 file changed, 240 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 912c14c9a5823d34..4c7370af9ca04aca 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1476,6 +1476,182 @@ static const unsigned int mmc_ds_mux[] = {
 	MMC_DS_MARK,
 };
 
+/* - MSIOF0 ----------------------------------------------------------------- */
+static const unsigned int msiof0_clk_pins[] = {
+	/* MSIOF0_SCK */
+	RCAR_GP_PIN(0, 14),
+};
+static const unsigned int msiof0_clk_mux[] = {
+	MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+	/* MSIOF0_SYNC */
+	RCAR_GP_PIN(0, 11),
+};
+static const unsigned int msiof0_sync_mux[] = {
+	MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+	/* MSIOF0_SS1 */
+	RCAR_GP_PIN(0, 15),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+	MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+	/* MSIOF0_SS2 */
+	RCAR_GP_PIN(0, 16),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+	MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+	/* MSIOF0_TXD */
+	RCAR_GP_PIN(0, 13),
+};
+static const unsigned int msiof0_txd_mux[] = {
+	MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+	/* MSIOF0_RXD */
+	RCAR_GP_PIN(0, 12),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+	MSIOF0_RXD_MARK,
+};
+
+/* - MSIOF1 ----------------------------------------------------------------- */
+static const unsigned int msiof1_clk_pins[] = {
+	/* MSIOF1_SCK */
+	RCAR_GP_PIN(0, 8),
+};
+static const unsigned int msiof1_clk_mux[] = {
+	MSIOF1_SCK_MARK,
+};
+static const unsigned int msiof1_sync_pins[] = {
+	/* MSIOF1_SYNC */
+	RCAR_GP_PIN(0, 10),
+};
+static const unsigned int msiof1_sync_mux[] = {
+	MSIOF1_SYNC_MARK,
+};
+static const unsigned int msiof1_ss1_pins[] = {
+	/* MSIOF1_SS1 */
+	RCAR_GP_PIN(0, 17),
+};
+static const unsigned int msiof1_ss1_mux[] = {
+	MSIOF1_SS1_MARK,
+};
+static const unsigned int msiof1_ss2_pins[] = {
+	/* MSIOF1_SS2 */
+	RCAR_GP_PIN(0, 18),
+};
+static const unsigned int msiof1_ss2_mux[] = {
+	MSIOF1_SS2_MARK,
+};
+static const unsigned int msiof1_txd_pins[] = {
+	/* MSIOF1_TXD */
+	RCAR_GP_PIN(0, 7),
+};
+static const unsigned int msiof1_txd_mux[] = {
+	MSIOF1_TXD_MARK,
+};
+static const unsigned int msiof1_rxd_pins[] = {
+	/* MSIOF1_RXD */
+	RCAR_GP_PIN(0, 6),
+};
+static const unsigned int msiof1_rxd_mux[] = {
+	MSIOF1_RXD_MARK,
+};
+
+/* - MSIOF2 ----------------------------------------------------------------- */
+static const unsigned int msiof2_clk_pins[] = {
+	/* MSIOF2_SCK */
+	RCAR_GP_PIN(1, 5),
+};
+static const unsigned int msiof2_clk_mux[] = {
+	MSIOF2_SCK_MARK,
+};
+static const unsigned int msiof2_sync_pins[] = {
+	/* MSIOF2_SYNC */
+	RCAR_GP_PIN(1, 4),
+};
+static const unsigned int msiof2_sync_mux[] = {
+	MSIOF2_SYNC_MARK,
+};
+static const unsigned int msiof2_ss1_pins[] = {
+	/* MSIOF2_SS1 */
+	RCAR_GP_PIN(1, 2),
+};
+static const unsigned int msiof2_ss1_mux[] = {
+	MSIOF2_SS1_MARK,
+};
+static const unsigned int msiof2_ss2_pins[] = {
+	/* MSIOF2_SS2 */
+	RCAR_GP_PIN(1, 3),
+};
+static const unsigned int msiof2_ss2_mux[] = {
+	MSIOF2_SS2_MARK,
+};
+static const unsigned int msiof2_txd_pins[] = {
+	/* MSIOF2_TXD */
+	RCAR_GP_PIN(1, 7),
+};
+static const unsigned int msiof2_txd_mux[] = {
+	MSIOF2_TXD_MARK,
+};
+static const unsigned int msiof2_rxd_pins[] = {
+	/* MSIOF2_RXD */
+	RCAR_GP_PIN(1, 6),
+};
+static const unsigned int msiof2_rxd_mux[] = {
+	MSIOF2_RXD_MARK,
+};
+
+/* - MSIOF3 ----------------------------------------------------------------- */
+static const unsigned int msiof3_clk_pins[] = {
+	/* MSIOF3_SCK */
+	RCAR_GP_PIN(0, 1),
+};
+static const unsigned int msiof3_clk_mux[] = {
+	MSIOF3_SCK_MARK,
+};
+static const unsigned int msiof3_sync_pins[] = {
+	/* MSIOF3_SYNC */
+	RCAR_GP_PIN(0, 9),
+};
+static const unsigned int msiof3_sync_mux[] = {
+	MSIOF3_SYNC_MARK,
+};
+static const unsigned int msiof3_ss1_pins[] = {
+	/* MSIOF3_SS1 */
+	RCAR_GP_PIN(0, 4),
+};
+static const unsigned int msiof3_ss1_mux[] = {
+	MSIOF3_SS1_MARK,
+};
+static const unsigned int msiof3_ss2_pins[] = {
+	/* MSIOF3_SS2 */
+	RCAR_GP_PIN(0, 5),
+};
+static const unsigned int msiof3_ss2_mux[] = {
+	MSIOF3_SS2_MARK,
+};
+static const unsigned int msiof3_txd_pins[] = {
+	/* MSIOF3_TXD */
+	RCAR_GP_PIN(0, 3),
+};
+static const unsigned int msiof3_txd_mux[] = {
+	MSIOF3_TXD_MARK,
+};
+static const unsigned int msiof3_rxd_pins[] = {
+	/* MSIOF3_RXD */
+	RCAR_GP_PIN(0, 2),
+};
+static const unsigned int msiof3_rxd_mux[] = {
+	MSIOF3_RXD_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX0, TX0 */
@@ -1609,6 +1785,30 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(mmc_cd),
 	SH_PFC_PIN_GROUP(mmc_wp),
 	SH_PFC_PIN_GROUP(mmc_ds),
+	SH_PFC_PIN_GROUP(msiof0_clk),
+	SH_PFC_PIN_GROUP(msiof0_sync),
+	SH_PFC_PIN_GROUP(msiof0_ss1),
+	SH_PFC_PIN_GROUP(msiof0_ss2),
+	SH_PFC_PIN_GROUP(msiof0_txd),
+	SH_PFC_PIN_GROUP(msiof0_rxd),
+	SH_PFC_PIN_GROUP(msiof1_clk),
+	SH_PFC_PIN_GROUP(msiof1_sync),
+	SH_PFC_PIN_GROUP(msiof1_ss1),
+	SH_PFC_PIN_GROUP(msiof1_ss2),
+	SH_PFC_PIN_GROUP(msiof1_txd),
+	SH_PFC_PIN_GROUP(msiof1_rxd),
+	SH_PFC_PIN_GROUP(msiof2_clk),
+	SH_PFC_PIN_GROUP(msiof2_sync),
+	SH_PFC_PIN_GROUP(msiof2_ss1),
+	SH_PFC_PIN_GROUP(msiof2_ss2),
+	SH_PFC_PIN_GROUP(msiof2_txd),
+	SH_PFC_PIN_GROUP(msiof2_rxd),
+	SH_PFC_PIN_GROUP(msiof3_clk),
+	SH_PFC_PIN_GROUP(msiof3_sync),
+	SH_PFC_PIN_GROUP(msiof3_ss1),
+	SH_PFC_PIN_GROUP(msiof3_ss2),
+	SH_PFC_PIN_GROUP(msiof3_txd),
+	SH_PFC_PIN_GROUP(msiof3_rxd),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1691,6 +1891,42 @@ static const char * const mmc_groups[] = {
 	"mmc_ds",
 };
 
+static const char * const msiof0_groups[] = {
+	"msiof0_clk",
+	"msiof0_sync",
+	"msiof0_ss1",
+	"msiof0_ss2",
+	"msiof0_txd",
+	"msiof0_rxd",
+};
+
+static const char * const msiof1_groups[] = {
+	"msiof1_clk",
+	"msiof1_sync",
+	"msiof1_ss1",
+	"msiof1_ss2",
+	"msiof1_txd",
+	"msiof1_rxd",
+};
+
+static const char * const msiof2_groups[] = {
+	"msiof2_clk",
+	"msiof2_sync",
+	"msiof2_ss1",
+	"msiof2_ss2",
+	"msiof2_txd",
+	"msiof2_rxd",
+};
+
+static const char * const msiof3_groups[] = {
+	"msiof3_clk",
+	"msiof3_sync",
+	"msiof3_ss1",
+	"msiof3_ss2",
+	"msiof3_txd",
+	"msiof3_rxd",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -1732,6 +1968,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(i2c5),
 	SH_PFC_FUNCTION(intc_ex),
 	SH_PFC_FUNCTION(mmc),
+	SH_PFC_FUNCTION(msiof0),
+	SH_PFC_FUNCTION(msiof1),
+	SH_PFC_FUNCTION(msiof2),
+	SH_PFC_FUNCTION(msiof3),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),
-- 
2.25.1

[PATCH/RFC 11/15] pinctrl: renesas: r8a779f0: Add PCIe pins, groups, and function

[Geert Uytterhoeven]

Add pins, groups, and function for the PCIe Controllers on the Renesas
R-Car S4-8 (R8A779F0) SoC.

Extracted from a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 27 ++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 4c7370af9ca04aca..8c294664bf4c28eb 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1652,6 +1652,25 @@ static const unsigned int msiof3_rxd_mux[] = {
 	MSIOF3_RXD_MARK,
 };
 
+/* - PCIE ------------------------------------------------------------------- */
+static const unsigned int pcie0_clkreq_n_pins[] = {
+	/* PCIE0_CLKREQ# */
+	RCAR_GP_PIN(2, 15),
+};
+
+static const unsigned int pcie0_clkreq_n_mux[] = {
+	PCIE0_CLKREQ_N_MARK,
+};
+
+static const unsigned int pcie1_clkreq_n_pins[] = {
+	/* PCIE1_CLKREQ# */
+	RCAR_GP_PIN(2, 16),
+};
+
+static const unsigned int pcie1_clkreq_n_mux[] = {
+	PCIE1_CLKREQ_N_MARK,
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX0, TX0 */
@@ -1809,6 +1828,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(msiof3_ss2),
 	SH_PFC_PIN_GROUP(msiof3_txd),
 	SH_PFC_PIN_GROUP(msiof3_rxd),
+	SH_PFC_PIN_GROUP(pcie0_clkreq_n),
+	SH_PFC_PIN_GROUP(pcie1_clkreq_n),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1927,6 +1948,11 @@ static const char * const msiof3_groups[] = {
 	"msiof3_rxd",
 };
 
+static const char * const pcie_groups[] = {
+	"pcie0_clkreq_n",
+	"pcie1_clkreq_n",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -1972,6 +1998,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(msiof1),
 	SH_PFC_FUNCTION(msiof2),
 	SH_PFC_FUNCTION(msiof3),
+	SH_PFC_FUNCTION(pcie),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),
-- 
2.25.1

[PATCH/RFC 12/15] pinctrl: renesas: r8a779f0: Add QSPI pins, groups, and functions

[Geert Uytterhoeven]

Add pins, groups, and functions for the Quad SPI Controllers on the
Renesas R-Car S4-8 (R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "[PATCH 00/60] pinctrl: renesas: Share more pin group
data"[1].

Changes compared to the BSP:
  - Share QSPI pin group data.

[1] https://lore.kernel.org/r/cover.1640269757.git.geert+renesas@glider.be
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 56 ++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 8c294664bf4c28eb..0ecb7ce7565e712c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1671,6 +1671,42 @@ static const unsigned int pcie1_clkreq_n_mux[] = {
 	PCIE1_CLKREQ_N_MARK,
 };
 
+/* - QSPI0 ------------------------------------------------------------------ */
+static const unsigned int qspi0_ctrl_pins[] = {
+	/* SPCLK, SSL */
+	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int qspi0_ctrl_mux[] = {
+	QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
+};
+static const unsigned int qspi0_data_pins[] = {
+	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
+	RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 12),
+	RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 14),
+};
+static const unsigned int qspi0_data_mux[] = {
+	QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
+	QSPI0_IO2_MARK, QSPI0_IO3_MARK
+};
+
+/* - QSPI1 ------------------------------------------------------------------ */
+static const unsigned int qspi1_ctrl_pins[] = {
+	/* SPCLK, SSL */
+	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 3),
+};
+static const unsigned int qspi1_ctrl_mux[] = {
+	QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
+};
+static const unsigned int qspi1_data_pins[] = {
+	/* MOSI_IO0, MISO_IO1, IO2, IO3 */
+	RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 5),
+	RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 4),
+};
+static const unsigned int qspi1_data_mux[] = {
+	QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
+	QSPI1_IO2_MARK, QSPI1_IO3_MARK
+};
+
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
 	/* RX0, TX0 */
@@ -1830,6 +1866,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(msiof3_rxd),
 	SH_PFC_PIN_GROUP(pcie0_clkreq_n),
 	SH_PFC_PIN_GROUP(pcie1_clkreq_n),
+	SH_PFC_PIN_GROUP(qspi0_ctrl),
+	BUS_DATA_PIN_GROUP(qspi0_data, 2),
+	BUS_DATA_PIN_GROUP(qspi0_data, 4),
+	SH_PFC_PIN_GROUP(qspi1_ctrl),
+	BUS_DATA_PIN_GROUP(qspi1_data, 2),
+	BUS_DATA_PIN_GROUP(qspi1_data, 4),
 	SH_PFC_PIN_GROUP(scif0_data),
 	SH_PFC_PIN_GROUP(scif0_clk),
 	SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -1953,6 +1995,18 @@ static const char * const pcie_groups[] = {
 	"pcie1_clkreq_n",
 };
 
+static const char * const qspi0_groups[] = {
+	"qspi0_ctrl",
+	"qspi0_data2",
+	"qspi0_data4",
+};
+
+static const char * const qspi1_groups[] = {
+	"qspi1_ctrl",
+	"qspi1_data2",
+	"qspi1_data4",
+};
+
 static const char * const scif0_groups[] = {
 	"scif0_data",
 	"scif0_clk",
@@ -1999,6 +2053,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(msiof2),
 	SH_PFC_FUNCTION(msiof3),
 	SH_PFC_FUNCTION(pcie),
+	SH_PFC_FUNCTION(qspi0),
+	SH_PFC_FUNCTION(qspi1),
 	SH_PFC_FUNCTION(scif0),
 	SH_PFC_FUNCTION(scif1),
 	SH_PFC_FUNCTION(scif3),
-- 
2.25.1

[PATCH/RFC 13/15] pinctrl: renesas: r8a779f0: Add Ethernet pins, groups, and functions

[Geert Uytterhoeven]

Add pins, groups, and functions for the Ethernet Time-Sensitive
Networking (TSN) interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes compared to the BSP:
  - Add B-suffixes to groups that can appear on multiple sets of pins,
  - Add missing A groups.
---
 drivers/pinctrl/renesas/pfc-r8a779f0.c | 288 +++++++++++++++++++++++++
 1 file changed, 288 insertions(+)

diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index 0ecb7ce7565e712c..3357f60b3074ee4e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1808,6 +1808,222 @@ static const unsigned int scif_clk_mux[] = {
 	SCIF_CLK_MARK,
 };
 
+/* - TSN0 ------------------------------------------------ */
+static const unsigned int tsn0_link_a_pins[] = {
+	/* TSN0_LINK_A */
+	RCAR_GP_PIN(0, 11),
+};
+static const unsigned int tsn0_link_a_mux[] = {
+	TSN0_LINK_A_MARK,
+};
+static const unsigned int tsn0_magic_a_pins[] = {
+	/* TSN0_MAGIC_A */
+	RCAR_GP_PIN(0, 17),
+};
+static const unsigned int tsn0_magic_a_mux[] = {
+	TSN0_MAGIC_A_MARK,
+};
+static const unsigned int tsn0_phy_int_a_pins[] = {
+	/* TSN0_PHY_INT_A */
+	RCAR_GP_PIN(0, 18),
+};
+static const unsigned int tsn0_phy_int_a_mux[] = {
+	TSN0_PHY_INT_A_MARK,
+};
+static const unsigned int tsn0_mdio_a_pins[] = {
+	/* TSN0_MDC_A, TSN0_MDIO_A */
+	RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int tsn0_mdio_a_mux[] = {
+	TSN0_MDC_A_MARK, TSN0_MDIO_A_MARK,
+};
+static const unsigned int tsn0_link_b_pins[] = {
+	/* TSN0_LINK_B */
+	RCAR_GP_PIN(3, 8),
+};
+static const unsigned int tsn0_link_b_mux[] = {
+	TSN0_LINK_B_MARK,
+};
+static const unsigned int tsn0_magic_b_pins[] = {
+	/* TSN0_MAGIC_B */
+	RCAR_GP_PIN(3, 12),
+};
+static const unsigned int tsn0_magic_b_mux[] = {
+	TSN0_MAGIC_B_MARK,
+};
+static const unsigned int tsn0_phy_int_b_pins[] = {
+	/* TSN0_PHY_INT_B */
+	RCAR_GP_PIN(3, 10),
+};
+static const unsigned int tsn0_phy_int_b_mux[] = {
+	TSN0_PHY_INT_B_MARK,
+};
+static const unsigned int tsn0_mdio_b_pins[] = {
+	/* TSN0_MDC_B, TSN0_MDIO_B */
+	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 2),
+};
+static const unsigned int tsn0_mdio_b_mux[] = {
+	TSN0_MDC_B_MARK, TSN0_MDIO_B_MARK,
+};
+static const unsigned int tsn0_avtp_pps_pins[] = {
+	/* TSN0_AVTP_PPS */
+	RCAR_GP_PIN(3, 16),
+};
+static const unsigned int tsn0_avtp_pps_mux[] = {
+	TSN0_AVTP_PPS_MARK,
+};
+static const unsigned int tsn0_avtp_capture_a_pins[] = {
+	/* TSN0_AVTP_CAPTURE_A */
+	RCAR_GP_PIN(0, 1),
+};
+static const unsigned int tsn0_avtp_capture_a_mux[] = {
+	TSN0_AVTP_CAPTURE_A_MARK,
+};
+static const unsigned int tsn0_avtp_match_a_pins[] = {
+	/* TSN0_AVTP_MATCH_A */
+	RCAR_GP_PIN(0, 2),
+};
+static const unsigned int tsn0_avtp_match_a_mux[] = {
+	TSN0_AVTP_MATCH_A_MARK,
+};
+static const unsigned int tsn0_avtp_capture_b_pins[] = {
+	/* TSN0_AVTP_CAPTURE_B */
+	RCAR_GP_PIN(3, 18),
+};
+static const unsigned int tsn0_avtp_capture_b_mux[] = {
+	TSN0_AVTP_CAPTURE_B_MARK,
+};
+static const unsigned int tsn0_avtp_match_b_pins[] = {
+	/* TSN0_AVTP_MATCH_B */
+	RCAR_GP_PIN(3, 17),
+};
+static const unsigned int tsn0_avtp_match_b_mux[] = {
+	TSN0_AVTP_MATCH_B_MARK,
+};
+
+/* - TSN1 ------------------------------------------------ */
+static const unsigned int tsn1_link_a_pins[] = {
+	/* TSN1_LINK_A */
+	RCAR_GP_PIN(0, 15),
+};
+static const unsigned int tsn1_link_a_mux[] = {
+	TSN1_LINK_A_MARK,
+};
+static const unsigned int tsn1_phy_int_a_pins[] = {
+	/* TSN1_PHY_INT_A */
+	RCAR_GP_PIN(0, 19),
+};
+static const unsigned int tsn1_phy_int_a_mux[] = {
+	TSN1_PHY_INT_A_MARK,
+};
+static const unsigned int tsn1_mdio_a_pins[] = {
+	/* TSN1_MDC_A, TSN1_MDIO_A */
+	RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
+};
+static const unsigned int tsn1_mdio_a_mux[] = {
+	TSN1_MDC_A_MARK, TSN1_MDIO_A_MARK,
+};
+static const unsigned int tsn1_link_b_pins[] = {
+	/* TSN1_LINK_B */
+	RCAR_GP_PIN(3, 6),
+};
+static const unsigned int tsn1_link_b_mux[] = {
+	TSN1_LINK_B_MARK,
+};
+static const unsigned int tsn1_phy_int_b_pins[] = {
+	/* TSN1_PHY_INT_B */
+	RCAR_GP_PIN(3, 11),
+};
+static const unsigned int tsn1_phy_int_b_mux[] = {
+	TSN1_PHY_INT_B_MARK,
+};
+static const unsigned int tsn1_mdio_b_pins[] = {
+	/* TSN1_MDC_B, TSN1_MDIO_B */
+	RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int tsn1_mdio_b_mux[] = {
+	TSN1_MDC_B_MARK, TSN1_MDIO_B_MARK,
+};
+static const unsigned int tsn1_avtp_pps_pins[] = {
+	/* TSN1_AVTP_PPS */
+	RCAR_GP_PIN(3, 13),
+};
+static const unsigned int tsn1_avtp_pps_mux[] = {
+	TSN0_AVTP_PPS_MARK,
+};
+static const unsigned int tsn1_avtp_capture_a_pins[] = {
+	/* TSN1_AVTP_CAPTURE_A */
+	RCAR_GP_PIN(0, 7),
+};
+static const unsigned int tsn1_avtp_capture_a_mux[] = {
+	TSN1_AVTP_CAPTURE_A_MARK,
+};
+static const unsigned int tsn1_avtp_match_a_pins[] = {
+	/* TSN1_AVTP_MATCH_A */
+	RCAR_GP_PIN(0, 6),
+};
+static const unsigned int tsn1_avtp_match_a_mux[] = {
+	TSN1_AVTP_MATCH_A_MARK,
+};
+static const unsigned int tsn1_avtp_capture_b_pins[] = {
+	/* TSN1_AVTP_CAPTURE_B */
+	RCAR_GP_PIN(3, 15),
+};
+static const unsigned int tsn1_avtp_capture_b_mux[] = {
+	TSN1_AVTP_CAPTURE_B_MARK,
+};
+static const unsigned int tsn1_avtp_match_b_pins[] = {
+	/* TSN1_AVTP_MATCH_B */
+	RCAR_GP_PIN(3, 14),
+};
+static const unsigned int tsn1_avtp_match_b_mux[] = {
+	TSN1_AVTP_MATCH_B_MARK,
+};
+
+/* - TSN2 ------------------------------------------------ */
+static const unsigned int tsn2_link_a_pins[] = {
+	/* TSN2_LINK_A */
+	RCAR_GP_PIN(0, 16),
+};
+static const unsigned int tsn2_link_a_mux[] = {
+	TSN2_LINK_A_MARK,
+};
+static const unsigned int tsn2_phy_int_a_pins[] = {
+	/* TSN2_PHY_INT_A */
+	RCAR_GP_PIN(0, 20),
+};
+static const unsigned int tsn2_phy_int_a_mux[] = {
+	TSN2_PHY_INT_A_MARK,
+};
+static const unsigned int tsn2_mdio_a_pins[] = {
+	/* TSN2_MDC_A, TSN2_MDIO_A */
+	RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
+};
+static const unsigned int tsn2_mdio_a_mux[] = {
+	TSN2_MDC_A_MARK, TSN2_MDIO_A_MARK,
+};
+static const unsigned int tsn2_link_b_pins[] = {
+	/* TSN2_LINK_B */
+	RCAR_GP_PIN(3, 7),
+};
+static const unsigned int tsn2_link_b_mux[] = {
+	TSN2_LINK_B_MARK,
+};
+static const unsigned int tsn2_phy_int_b_pins[] = {
+	/* TSN2_PHY_INT_B */
+	RCAR_GP_PIN(3, 9),
+};
+static const unsigned int tsn2_phy_int_b_mux[] = {
+	TSN2_PHY_INT_B_MARK,
+};
+static const unsigned int tsn2_mdio_b_pins[] = {
+	/* TSN2_MDC_B, TSN2_MDIO_B */
+	RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int tsn2_mdio_b_mux[] = {
+	TSN2_MDC_B_MARK, TSN2_MDIO_B_MARK,
+};
+
 static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(hscif0_data),
 	SH_PFC_PIN_GROUP(hscif0_clk),
@@ -1885,6 +2101,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
 	SH_PFC_PIN_GROUP(scif4_clk),
 	SH_PFC_PIN_GROUP(scif4_ctrl),
 	SH_PFC_PIN_GROUP(scif_clk),
+	SH_PFC_PIN_GROUP(tsn0_link_a),
+	SH_PFC_PIN_GROUP(tsn0_magic_a),
+	SH_PFC_PIN_GROUP(tsn0_phy_int_a),
+	SH_PFC_PIN_GROUP(tsn0_mdio_a),
+	SH_PFC_PIN_GROUP(tsn0_link_b),
+	SH_PFC_PIN_GROUP(tsn0_magic_b),
+	SH_PFC_PIN_GROUP(tsn0_phy_int_b),
+	SH_PFC_PIN_GROUP(tsn0_mdio_b),
+	SH_PFC_PIN_GROUP(tsn0_avtp_pps),
+	SH_PFC_PIN_GROUP(tsn0_avtp_capture_a),
+	SH_PFC_PIN_GROUP(tsn0_avtp_match_a),
+	SH_PFC_PIN_GROUP(tsn0_avtp_capture_b),
+	SH_PFC_PIN_GROUP(tsn0_avtp_match_b),
+	SH_PFC_PIN_GROUP(tsn1_link_a),
+	SH_PFC_PIN_GROUP(tsn1_phy_int_a),
+	SH_PFC_PIN_GROUP(tsn1_mdio_a),
+	SH_PFC_PIN_GROUP(tsn1_link_b),
+	SH_PFC_PIN_GROUP(tsn1_phy_int_b),
+	SH_PFC_PIN_GROUP(tsn1_mdio_b),
+	SH_PFC_PIN_GROUP(tsn1_avtp_pps),
+	SH_PFC_PIN_GROUP(tsn1_avtp_capture_a),
+	SH_PFC_PIN_GROUP(tsn1_avtp_match_a),
+	SH_PFC_PIN_GROUP(tsn1_avtp_capture_b),
+	SH_PFC_PIN_GROUP(tsn1_avtp_match_b),
+	SH_PFC_PIN_GROUP(tsn2_link_a),
+	SH_PFC_PIN_GROUP(tsn2_phy_int_a),
+	SH_PFC_PIN_GROUP(tsn2_mdio_a),
+	SH_PFC_PIN_GROUP(tsn2_link_b),
+	SH_PFC_PIN_GROUP(tsn2_phy_int_b),
+	SH_PFC_PIN_GROUP(tsn2_mdio_b),
 };
 
 static const char * const hscif0_groups[] = {
@@ -2035,6 +2281,45 @@ static const char * const scif_clk_groups[] = {
 	"scif_clk",
 };
 
+static const char * const tsn0_groups[] = {
+	"tsn0_link_a",
+	"tsn0_magic_a",
+	"tsn0_phy_int_a",
+	"tsn0_mdio_a",
+	"tsn0_link_b",
+	"tsn0_magic_b",
+	"tsn0_phy_int_b",
+	"tsn0_mdio_b",
+	"tsn0_avtp_pps",
+	"tsn0_avtp_capture_a",
+	"tsn0_avtp_match_a",
+	"tsn0_avtp_capture_b",
+	"tsn0_avtp_match_b",
+};
+
+static const char * const tsn1_groups[] = {
+	"tsn1_link_a",
+	"tsn1_phy_int_a",
+	"tsn1_mdio_a",
+	"tsn1_link_b",
+	"tsn1_phy_int_b",
+	"tsn1_mdio_b",
+	"tsn1_avtp_pps",
+	"tsn1_avtp_capture_a",
+	"tsn1_avtp_match_a",
+	"tsn1_avtp_capture_b",
+	"tsn1_avtp_match_b",
+};
+
+static const char * const tsn2_groups[] = {
+	"tsn2_link_a",
+	"tsn2_phy_int_a",
+	"tsn2_mdio_a",
+	"tsn2_link_b",
+	"tsn2_phy_int_b",
+	"tsn2_mdio_b",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(hscif0),
 	SH_PFC_FUNCTION(hscif1),
@@ -2060,6 +2345,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
 	SH_PFC_FUNCTION(scif3),
 	SH_PFC_FUNCTION(scif4),
 	SH_PFC_FUNCTION(scif_clk),
+	SH_PFC_FUNCTION(tsn0),
+	SH_PFC_FUNCTION(tsn1),
+	SH_PFC_FUNCTION(tsn2),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
-- 
2.25.1

[PATCH/RFC 14/15] arm64: dts: renesas: r8a779f0: Add pinctrl device node

[Geert Uytterhoeven]

Add a device node for the Pin Function Controller on the Renesas R-Car
S4-8 (R8A779F0) SoC.

Note that register banks 4-7 do not seem to be accessible as-is using
either the Control Domain (0xffd9....) or Application Domain
(0xdfd9....) addresses, so currently you cannot configure pins
controlled by these banks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
How to make the Control Domain release the bus guard, so the registers
become accessible?
---
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 0ac8c345558efc17..ada6ff380b203625 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -69,6 +69,14 @@ rwdt: watchdog@e6020000 {
 			status = "disabled";
 		};
 
+		pfc: pinctrl@e6050000 {
+			compatible = "renesas,pfc-r8a779f0";
+			reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
+			      <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>,
+			      <0 0xffd90000 0 0x16c>, <0 0xffd90800 0 0x16c>,
+			      <0 0xffd91000 0 0x16c>, <0 0xffd91800 0 0x16c>;
+		};
+
 		cpg: clock-controller@e6150000 {
 			compatible = "renesas,r8a779f0-cpg-mssr";
 			reg = <0 0xe6150000 0 0x4000>;
-- 
2.25.1

[PATCH/RFC 15/15] arm64: dts: renesas: spider: Complete SCIF3 description

[Geert Uytterhoeven]

Complete the description of the serial console by adding RTS/CTS, the
external clock crystal, and pin control.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index 3a90932fe85c8243..6e07c54148e716d7 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -31,11 +31,34 @@ &extalr_clk {
 	clock-frequency = <32768>;
 };
 
+&pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	scif3_pins: scif3 {
+		groups = "scif3_data", "scif3_ctrl";
+		function = "scif3";
+	};
+
+	scif_clk_pins: scif_clk {
+		groups = "scif_clk";
+		function = "scif_clk";
+	};
+};
+
 &rwdt {
 	timeout-sec = <60>;
 	status = "okay";
 };
 
 &scif3 {
+	pinctrl-0 = <&scif3_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
 	status = "okay";
 };
+
+&scif_clk {
+	clock-frequency = <24000000>;
+};
-- 
2.25.1

Re: [PATCH/RFC 00/15] arm64: renesas: Add-R-Car S4-8 Pin control support

[Geert Uytterhoeven]

On Wed, Jan 19, 2022 at 3:02 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> This patch series adds pin control support for the Renesas R-Car S4-8
> Soc on the Spider board, and enables pin control for the serial console.
> It is based on patches in the BSP by LUU HOAI, with many changes on top
> (see the individual patches).
>
> This series is marked as an RFC because of 2 reasons:
>   1. PFC register banks 4-7 do not seem to be accessible as-is using
>      either the Control Domain (0xffd9....) or Application Domain
>      (0xdfd9....) addresses, so currently you cannot configure pins
>      controlled by these banks.
>      How to make the Control Domain release the bus guard, so the
>      registers become accessible?
>   2. It this has been tested only lightly with remote access.
>
> For testing, this series and its dependencies can be found at[1].
>
> Thanks for your comments!
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/r8a779f0-pfc-v1

>   pinctrl: renesas: Initial R8A779F0 PFC support

Unfortunately 04/15 didn't make it to the list or lore (too large?),
so you have to grab it from git, or ask me for a copy in your personal
mailbox.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH/RFC 04/15] pinctrl: renesas: Initial R8A779F0 PFC support

[Geert Uytterhoeven]

On Wed, Jan 19, 2022 at 3:02 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> Add initial Pin Function Controller (PFC) support for the Renesas R-Car
> S4-8 (R8A779F0) SoC.
>
> Based on a larger patch in the BSP by LUU HOAI.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

I accidentally sent out an old version, lacking changes to I2C[45]:

  - Replace "PINMUX_IPSR_PHYS_NOFN(y, z)" by "PINMUX_IPSR_NOFN(GP1_x, y,
    z)", as I2C requires GPSR1[x] to be configured for peripheral mode,

> --- /dev/null
> +++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c

> +       /* GP1_08 = SCL4 */
> +       PINMUX_IPSR_NOGM(0, GP1_08,     SEL_I2C4_0),
> +       PINMUX_IPSR_PHYS_NOFN(SCL4,     SEL_I2C4_3),

      PINMUX_IPSR_NOGM(0,             GP1_08,         SEL_I2C4_0),
      PINMUX_IPSR_NOFN(GP1_08,        SCL4,           SEL_I2C4_3),

> +
> +       /* GP1_09 = SDA4 */
> +       PINMUX_IPSR_NOGM(0, GP1_09,     SEL_I2C4_0),
> +       PINMUX_IPSR_PHYS_NOFN(SDA4,     SEL_I2C4_3),

      PINMUX_IPSR_NOGM(0,             GP1_09,         SEL_I2C4_0),
      PINMUX_IPSR_NOFN(GP1_09,        SDA4,           SEL_I2C4_3),

> +
> +       /* GP1_10 = SCL5 */
> +       PINMUX_IPSR_NOGM(0, GP1_10,     SEL_I2C5_0),
> +       PINMUX_IPSR_PHYS_NOFN(SCL5,     SEL_I2C5_3),

      PINMUX_IPSR_NOGM(0,             GP1_10,         SEL_I2C5_0),
      PINMUX_IPSR_NOFN(GP1_10,        SCL5,           SEL_I2C5_3),

> +
> +       /* GP1_11 = SDA5 */
> +       PINMUX_IPSR_NOGM(0, GP1_11,     SEL_I2C5_0),
> +       PINMUX_IPSR_PHYS_NOFN(SDA5,     SEL_I2C5_3),

      PINMUX_IPSR_NOGM(0,             GP1_11,         SEL_I2C5_0),
      PINMUX_IPSR_NOFN(GP1_11,        SDA5,           SEL_I2C5_3),

> --- a/drivers/pinctrl/renesas/sh_pfc.h
> +++ b/drivers/pinctrl/renesas/sh_pfc.h

> @@ -436,6 +437,16 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
>  #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
>         PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
>
> +/*
> + * Describe a pinmux configuration in which a pin is physically multiplexed
> + * with other pins and has no representation in a Peripheral Function Select
> + * Register (IPSR)
> + *   - fn: Function name
> + *   - psel: Physical multiplexing selector
> + */
> +#define PINMUX_IPSR_PHYS_NOFN(fn, psel) \
> +       PINMUX_DATA(fn##_MARK, FN_##psel)

This should be dropped.

> +
>  /*
>   * Describe a pinmux configuration for a single-function pin with GPIO
>   * capability.

I will update my topic/r8a779f0-pfc-v1 branch accordingly, and make
sure the correct version will be included in today's renesas-drivers
release.

My apologies for the trouble.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH/RFC 01/15] clk: renesas: r8a779f0: Add PFC clock

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Wednesday, January 19, 2022 11:02 PM
> 
> Add the module clock used by the Pin Function (PFC/GPIO) controller
> on the Renesas R-Car S4-8 (R8A779F0) SoC.
> 
> Extracted from a larger patch in the BSP by LUU HOAI.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda

RE: [PATCH/RFC 02/15] dt-bindings: pinctrl: renesas,pfc: Document r8a779f0 support

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Wednesday, January 19, 2022 11:02 PM
> 
> From: LUU HOAI <hoai.luu.ub@renesas.com>
> 
> Document Pin Function Controller (PFC) support for the Renesas R-Car
> S4-8 (R8A779F0) SoC.
> 
> Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda

RE: [PATCH/RFC 03/15] pinctrl: renesas: Add PORT_GP_CFG_19 macros

[Yoshihiro Shimoda]

Hi Geert-san,

> From: Geert Uytterhoeven, Sent: Wednesday, January 19, 2022 11:02 PM
> 
> Add PORT_GP_CFG_19() and PORT_GP_19() helper macros, to be used by the
> r8a779f0 subdriver.
> 
> Based on a larger patch in the BSP by LUU HOAI.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thank you for the patch!

Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Best regards,
Yoshihiro Shimoda