* [PATCH 0/2] arm64: dts: renesas: r8a779g0: add PCIe support
@ 2024-02-29 12:07 Yoshihiro Shimoda
2024-02-29 12:07 ` [PATCH 1/2] arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2024-02-29 12:07 ` [PATCH 2/2] arm64: dts: renesas: white-hawk-cpu-common: Enable PCIe Host ch0 Yoshihiro Shimoda
0 siblings, 2 replies; 8+ messages in thread
From: Yoshihiro Shimoda @ 2024-02-29 12:07 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
This patch series adds PCIe support for R-Car V4H (r8a779g0).
Yoshihiro Shimoda (2):
arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes
arm64: dts: renesas: white-hawk-cpu-common: Enable PCIe Host ch0
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 134 ++++++++++++++++++
.../dts/renesas/white-hawk-cpu-common.dtsi | 18 +++
2 files changed, 152 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes
2024-02-29 12:07 [PATCH 0/2] arm64: dts: renesas: r8a779g0: add PCIe support Yoshihiro Shimoda
@ 2024-02-29 12:07 ` Yoshihiro Shimoda
2024-03-14 13:56 ` Geert Uytterhoeven
2024-02-29 12:07 ` [PATCH 2/2] arm64: dts: renesas: white-hawk-cpu-common: Enable PCIe Host ch0 Yoshihiro Shimoda
1 sibling, 1 reply; 8+ messages in thread
From: Yoshihiro Shimoda @ 2024-02-29 12:07 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Add PCIe Host and Endpoint nodes for R-Car V4H (R8A779G0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 134 ++++++++++++++++++++++
1 file changed, 134 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 9bc542bc6169..ac8290ca5cf1 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -175,6 +175,20 @@ extalr_clk: extalr {
clock-frequency = <0>;
};
+ pcie0_clkref: pcie0-clkref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ pcie1_clkref: pcie1-clkref {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
pmu_a76 {
compatible = "arm,cortex-a76-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -723,6 +737,126 @@ hscif3: serial@e66a0000 {
status = "disabled";
};
+ pciec0: pcie@e65d0000 {
+ compatible = "renesas,r8a779g0-pcie",
+ "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
+ <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
+ interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ reset-names = "pwr";
+ max-link-speed = <4>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
+ snps,enable-cdm-check;
+ status = "disabled";
+ };
+
+ pciec1: pcie@e65d8000 {
+ compatible = "renesas,r8a779g0-pcie",
+ "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
+ <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
+ <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
+ <0 0xee900000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
+ interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ reset-names = "pwr";
+ max-link-speed = <4>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
+ <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
+ snps,enable-cdm-check;
+ status = "disabled";
+ };
+
+ pciec0_ep: pcie-ep@e65d0000 {
+ compatible = "renesas,r8a779g0-pcie-ep",
+ "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
+ <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
+ interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ reset-names = "pwr";
+ max-link-speed = <4>;
+ num-lanes = <2>;
+ max-functions = /bits/ 8 <2>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@e65d8000 {
+ compatible = "renesas,r8a779g0-pcie-ep",
+ "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
+ <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
+ <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
+ <0 0xee900000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
+ interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ reset-names = "pwr";
+ max-link-speed = <4>;
+ num-lanes = <2>;
+ max-functions = /bits/ 8 <2>;
+ status = "disabled";
+ };
+
canfd: can@e6660000 {
compatible = "renesas,r8a779g0-canfd",
"renesas,rcar-gen4-canfd";
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: white-hawk-cpu-common: Enable PCIe Host ch0
2024-02-29 12:07 [PATCH 0/2] arm64: dts: renesas: r8a779g0: add PCIe support Yoshihiro Shimoda
2024-02-29 12:07 ` [PATCH 1/2] arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
@ 2024-02-29 12:07 ` Yoshihiro Shimoda
2024-03-14 14:08 ` Geert Uytterhoeven
1 sibling, 1 reply; 8+ messages in thread
From: Yoshihiro Shimoda @ 2024-02-29 12:07 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Enable PCIe Host controller channel 0 on R-Car V4H White Hawk boards.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
.../dts/renesas/white-hawk-cpu-common.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
index 8ac17370ff36..3fc9a541f777 100644
--- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
@@ -111,6 +111,12 @@ mini_dp_con_in: endpoint {
};
};
+ pcie_clk: clk-9fgv0841-pci {
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ #clock-cells = <0>;
+ };
+
reg_1p2v: regulator-1p2v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.2V";
@@ -277,6 +283,18 @@ &mmc0 {
status = "okay";
};
+&pcie0_clkref {
+ compatible = "gpio-gate-clock";
+ clocks = <&pcie_clk>;
+ enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>;
+ /delete-property/ clock-frequency;
+};
+
+&pciec0 {
+ reset-gpio = <&io_expander_a 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes
2024-02-29 12:07 ` [PATCH 1/2] arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
@ 2024-03-14 13:56 ` Geert Uytterhoeven
2024-04-25 7:20 ` Geert Uytterhoeven
0 siblings, 1 reply; 8+ messages in thread
From: Geert Uytterhoeven @ 2024-03-14 13:56 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: geert+renesas, magnus.damm, linux-renesas-soc
Hi Shimoda-san,
On Thu, Feb 29, 2024 at 1:07 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add PCIe Host and Endpoint nodes for R-Car V4H (R8A779G0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> @@ -723,6 +737,126 @@ hscif3: serial@e66a0000 {
> status = "disabled";
> };
>
> + pciec0: pcie@e65d0000 {
> + compatible = "renesas,r8a779g0-pcie",
> + "renesas,rcar-gen4-pcie";
> + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
> + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
> + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
> + <0 0xfe000000 0 0x400000>;
> + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
> + interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi", "dma", "sft_ce", "app";
> + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
> + clock-names = "core", "ref";
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + resets = <&cpg 624>;
> + reset-names = "pwr";
> + max-link-speed = <4>;
> + num-lanes = <2>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x00 0xff>;
> + device_type = "pci";
> + ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
> + <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
> + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
s/416/449 for all four lines.
> + snps,enable-cdm-check;
> + status = "disabled";
> + };
> +
> + pciec1: pcie@e65d8000 {
> + compatible = "renesas,r8a779g0-pcie",
> + "renesas,rcar-gen4-pcie";
> + reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
> + <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
> + <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
> + <0 0xee900000 0 0x400000>;
> + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
> + interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi", "dma", "sft_ce", "app";
> + clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
> + clock-names = "core", "ref";
> + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
> + resets = <&cpg 625>;
> + reset-names = "pwr";
> + max-link-speed = <4>;
> + num-lanes = <2>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x00 0xff>;
> + device_type = "pci";
> + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
> + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
> + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
s/423/456 for all four lines.
> + snps,enable-cdm-check;
> + status = "disabled";
> + };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: white-hawk-cpu-common: Enable PCIe Host ch0
2024-02-29 12:07 ` [PATCH 2/2] arm64: dts: renesas: white-hawk-cpu-common: Enable PCIe Host ch0 Yoshihiro Shimoda
@ 2024-03-14 14:08 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2024-03-14 14:08 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: magnus.damm, linux-renesas-soc
On Thu, Feb 29, 2024 at 1:07 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Enable PCIe Host controller channel 0 on R-Car V4H White Hawk boards.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes
2024-03-14 13:56 ` Geert Uytterhoeven
@ 2024-04-25 7:20 ` Geert Uytterhoeven
2024-04-25 7:34 ` Yoshihiro Shimoda
0 siblings, 1 reply; 8+ messages in thread
From: Geert Uytterhoeven @ 2024-04-25 7:20 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: magnus.damm, linux-renesas-soc
Hi Shimoda-san,
On Thu, Mar 14, 2024 at 2:56 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Thu, Feb 29, 2024 at 1:07 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Add PCIe Host and Endpoint nodes for R-Car V4H (R8A779G0).
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > @@ -723,6 +737,126 @@ hscif3: serial@e66a0000 {
> > status = "disabled";
> > };
> >
> > + pciec0: pcie@e65d0000 {
> > + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
>
> s/416/449 for all four lines.
>
> > + snps,enable-cdm-check;
> > + status = "disabled";
> > + };
> > +
> > + pciec1: pcie@e65d8000 {
> > + interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
>
> s/423/456 for all four lines.
>
> > + snps,enable-cdm-check;
> > + status = "disabled";
> > + };
Do you foresee more changes, and plan to repost, or can I fix the
interrupt numbers while applying this series?
Thank you!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH 1/2] arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes
2024-04-25 7:20 ` Geert Uytterhoeven
@ 2024-04-25 7:34 ` Yoshihiro Shimoda
2024-04-25 7:56 ` Geert Uytterhoeven
0 siblings, 1 reply; 8+ messages in thread
From: Yoshihiro Shimoda @ 2024-04-25 7:34 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: magnus.damm, linux-renesas-soc
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Thursday, April 25, 2024 4:21 PM
>
> Hi Shimoda-san,
>
> On Thu, Mar 14, 2024 at 2:56 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Thu, Feb 29, 2024 at 1:07 PM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > Add PCIe Host and Endpoint nodes for R-Car V4H (R8A779G0).
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> > > --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > > @@ -723,6 +737,126 @@ hscif3: serial@e66a0000 {
> > > status = "disabled";
> > > };
> > >
> > > + pciec0: pcie@e65d0000 {
>
> > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > > + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > > + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > > + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
> >
> > s/416/449 for all four lines.
> >
> > > + snps,enable-cdm-check;
> > > + status = "disabled";
> > > + };
> > > +
> > > + pciec1: pcie@e65d8000 {
>
> > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > > + <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > > + <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > > + <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
> >
> > s/423/456 for all four lines.
> >
> > > + snps,enable-cdm-check;
> > > + status = "disabled";
> > > + };
>
> Do you foresee more changes, and plan to repost, or can I fix the
> interrupt numbers while applying this series?
Thank you for asking me about this. I intended to repost a fixed patch after PCIe patch series
was merged into PCI subsystem. Otherwise, dtbs_check will detect missing the compatible
"renesas,r8a779g0-pcie" in the dt-binding doc. But, it's under review now [1].
[1] https://patchwork.kernel.org/project/linux-pci/list/?series=844512
Best regards,
Yoshihiro Shimoda
> Thank you!
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes
2024-04-25 7:34 ` Yoshihiro Shimoda
@ 2024-04-25 7:56 ` Geert Uytterhoeven
0 siblings, 0 replies; 8+ messages in thread
From: Geert Uytterhoeven @ 2024-04-25 7:56 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: magnus.damm, linux-renesas-soc
Hi Shimoda-san,
On Thu, Apr 25, 2024 at 9:35 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Geert Uytterhoeven, Sent: Thursday, April 25, 2024 4:21 PM
> > On Thu, Mar 14, 2024 at 2:56 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > On Thu, Feb 29, 2024 at 1:07 PM Yoshihiro Shimoda
> > > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > > Add PCIe Host and Endpoint nodes for R-Car V4H (R8A779G0).
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > > > --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
> > > > @@ -723,6 +737,126 @@ hscif3: serial@e66a0000 {
> > > > status = "disabled";
> > > > };
> > > >
> > > > + pciec0: pcie@e65d0000 {
> >
> > > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
> > >
> > > s/416/449 for all four lines.
> > >
> > > > + snps,enable-cdm-check;
> > > > + status = "disabled";
> > > > + };
> > > > +
> > > > + pciec1: pcie@e65d8000 {
> >
> > > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> > > > + <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
> > >
> > > s/423/456 for all four lines.
> > >
> > > > + snps,enable-cdm-check;
> > > > + status = "disabled";
> > > > + };
> >
> > Do you foresee more changes, and plan to repost, or can I fix the
> > interrupt numbers while applying this series?
>
> Thank you for asking me about this. I intended to repost a fixed patch after PCIe patch series
> was merged into PCI subsystem. Otherwise, dtbs_check will detect missing the compatible
> "renesas,r8a779g0-pcie" in the dt-binding doc. But, it's under review now [1].
>
> [1] https://patchwork.kernel.org/project/linux-pci/list/?series=844512
That's not a real blocker.
But I just realized the DTS (at least the second patch enabling PCIe on
White-Hawk) has a hard dependency on the driver changes, so it has to wait.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-04-25 7:56 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-29 12:07 [PATCH 0/2] arm64: dts: renesas: r8a779g0: add PCIe support Yoshihiro Shimoda
2024-02-29 12:07 ` [PATCH 1/2] arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2024-03-14 13:56 ` Geert Uytterhoeven
2024-04-25 7:20 ` Geert Uytterhoeven
2024-04-25 7:34 ` Yoshihiro Shimoda
2024-04-25 7:56 ` Geert Uytterhoeven
2024-02-29 12:07 ` [PATCH 2/2] arm64: dts: renesas: white-hawk-cpu-common: Enable PCIe Host ch0 Yoshihiro Shimoda
2024-03-14 14:08 ` Geert Uytterhoeven
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