* [RFC 1/5] dt-bindings: pwm: Add RZ/G2L GPT binding
2022-04-30 7:59 [RFC 0/5] Add support for RZ/G2L GPT Biju Das
@ 2022-04-30 7:59 ` Biju Das
2022-05-04 21:29 ` Rob Herring
2022-04-30 7:59 ` [RFC 2/5] pwm: Add support for RZ/G2L GPT Biju Das
` (3 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Biju Das @ 2022-04-30 7:59 UTC (permalink / raw)
To: Thierry Reding, Lee Jones, Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Uwe Kleine-König, linux-pwm, devicetree,
Geert Uytterhoeven, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad, linux-renesas-soc
Add device tree bindings for the RZ/G2L General PWM Timer (GPT).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 104 ++++++++++++++++++
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
new file mode 100644
index 000000000000..0e44c0fbe04a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L General PWM Timer (GPT)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-gpt # RZ/G2{L,LC}
+ - renesas,r9a07g054-gpt # RZ/V2L
+ - const: renesas,rzg2l-gpt
+
+ reg:
+ # base address and length of the registers block for the PWM.
+ maxItems: 1
+
+ '#pwm-cells':
+ # should be 2. See pwm.yaml in this directory for a description of
+ # the cells format.
+ const: 2
+
+ interrupts:
+ items:
+ - description: GTCCRA input capture/compare match
+ - description: GTCCRB input capture/compare
+ - description: GTCCRC compare match
+ - description: GTCCRD compare match
+ - description: GTCCRE compare match
+ - description: GTCCRF compare match
+ - description: GTADTRA compare match
+ - description: GTADTRB compare match
+ - description: GTCNT overflow/GTPR compare match
+ - description: GTCNT underflow
+
+ interrupt-names:
+ items:
+ - const: ccmpa
+ - const: ccmpb
+ - const: cmpc
+ - const: cmpd
+ - const: cmpe
+ - const: cmpf
+ - const: adtrga
+ - const: adtrgb
+ - const: ovf
+ - const: unf
+
+ clocks:
+ # clock phandle and specifier pair.
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+ - resets
+
+allOf:
+ - $ref: pwm.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gpt4: pwm@10048400 {
+ compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt";
+ reg = <0x10048400 0xa4>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg 523 R9A07G044_GPT_RST_C>;
+ #pwm-cells = <2>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [RFC 1/5] dt-bindings: pwm: Add RZ/G2L GPT binding
2022-04-30 7:59 ` [RFC 1/5] dt-bindings: pwm: Add RZ/G2L GPT binding Biju Das
@ 2022-05-04 21:29 ` Rob Herring
2022-05-05 10:42 ` Biju Das
0 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2022-05-04 21:29 UTC (permalink / raw)
To: Biju Das
Cc: Thierry Reding, Lee Jones, Krzysztof Kozlowski,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
On Sat, Apr 30, 2022 at 08:59:11AM +0100, Biju Das wrote:
> Add device tree bindings for the RZ/G2L General PWM Timer (GPT).
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 104 ++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
>
> diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> new file mode 100644
> index 000000000000..0e44c0fbe04a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L General PWM Timer (GPT)
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,r9a07g044-gpt # RZ/G2{L,LC}
> + - renesas,r9a07g054-gpt # RZ/V2L
> + - const: renesas,rzg2l-gpt
> +
> + reg:
> + # base address and length of the registers block for the PWM.
Yes, that's all 'reg', drop.
> + maxItems: 1
> +
> + '#pwm-cells':
> + # should be 2. See pwm.yaml in this directory for a description of
> + # the cells format.
2 cells the schema says already. The reference for the format is okay,
but move it to a 'description' entry.
> + const: 2
> +
> + interrupts:
> + items:
> + - description: GTCCRA input capture/compare match
> + - description: GTCCRB input capture/compare
> + - description: GTCCRC compare match
> + - description: GTCCRD compare match
> + - description: GTCCRE compare match
> + - description: GTCCRF compare match
> + - description: GTADTRA compare match
> + - description: GTADTRB compare match
> + - description: GTCNT overflow/GTPR compare match
> + - description: GTCNT underflow
> +
> + interrupt-names:
> + items:
> + - const: ccmpa
> + - const: ccmpb
> + - const: cmpc
> + - const: cmpd
> + - const: cmpe
> + - const: cmpf
> + - const: adtrga
> + - const: adtrgb
> + - const: ovf
> + - const: unf
> +
> + clocks:
> + # clock phandle and specifier pair.
That's all 'clocks', drop.
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - power-domains
> + - resets
> +
> +allOf:
> + - $ref: pwm.yaml#
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r9a07g044-cpg.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + gpt4: pwm@10048400 {
> + compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt";
> + reg = <0x10048400 0xa4>;
> + interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
> + "cmpe", "cmpf", "adtrga", "adtrgb",
> + "ovf", "unf";
> + clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
> + power-domains = <&cpg>;
> + resets = <&cpg 523 R9A07G044_GPT_RST_C>;
> + #pwm-cells = <2>;
> + };
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 8+ messages in thread* RE: [RFC 1/5] dt-bindings: pwm: Add RZ/G2L GPT binding
2022-05-04 21:29 ` Rob Herring
@ 2022-05-05 10:42 ` Biju Das
0 siblings, 0 replies; 8+ messages in thread
From: Biju Das @ 2022-05-05 10:42 UTC (permalink / raw)
To: Rob Herring
Cc: Thierry Reding, Lee Jones, Krzysztof Kozlowski,
Uwe Kleine-König, linux-pwm, devicetree, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [RFC 1/5] dt-bindings: pwm: Add RZ/G2L GPT binding
>
> On Sat, Apr 30, 2022 at 08:59:11AM +0100, Biju Das wrote:
> > Add device tree bindings for the RZ/G2L General PWM Timer (GPT).
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > .../bindings/pwm/renesas,rzg2l-gpt.yaml | 104 ++++++++++++++++++
> > 1 file changed, 104 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> > b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> > new file mode 100644
> > index 000000000000..0e44c0fbe04a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> > @@ -0,0 +1,104 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +
> > +title: Renesas RZ/G2L General PWM Timer (GPT)
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,r9a07g044-gpt # RZ/G2{L,LC}
> > + - renesas,r9a07g054-gpt # RZ/V2L
> > + - const: renesas,rzg2l-gpt
> > +
> > + reg:
> > + # base address and length of the registers block for the PWM.
>
> Yes, that's all 'reg', drop.
Agreed.
>
> > + maxItems: 1
> > +
> > + '#pwm-cells':
> > + # should be 2. See pwm.yaml in this directory for a description of
> > + # the cells format.
>
> 2 cells the schema says already. The reference for the format is okay, but
> move it to a 'description' entry.
Ok will add description entry.
>
> > + const: 2
> > +
> > + interrupts:
> > + items:
> > + - description: GTCCRA input capture/compare match
> > + - description: GTCCRB input capture/compare
> > + - description: GTCCRC compare match
> > + - description: GTCCRD compare match
> > + - description: GTCCRE compare match
> > + - description: GTCCRF compare match
> > + - description: GTADTRA compare match
> > + - description: GTADTRB compare match
> > + - description: GTCNT overflow/GTPR compare match
> > + - description: GTCNT underflow
> > +
> > + interrupt-names:
> > + items:
> > + - const: ccmpa
> > + - const: ccmpb
> > + - const: cmpc
> > + - const: cmpd
> > + - const: cmpe
> > + - const: cmpf
> > + - const: adtrga
> > + - const: adtrgb
> > + - const: ovf
> > + - const: unf
> > +
> > + clocks:
> > + # clock phandle and specifier pair.
>
> That's all 'clocks', drop.
OK will drop this.
Regards,
Biju
>
> > + maxItems: 1
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > + - power-domains
> > + - resets
> > +
> > +allOf:
> > + - $ref: pwm.yaml#
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + gpt4: pwm@10048400 {
> > + compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt";
> > + reg = <0x10048400 0xa4>;
> > + interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
> > + "cmpe", "cmpf", "adtrga", "adtrgb",
> > + "ovf", "unf";
> > + clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg 523 R9A07G044_GPT_RST_C>;
> > + #pwm-cells = <2>;
> > + };
> > --
> > 2.25.1
> >
> >
^ permalink raw reply [flat|nested] 8+ messages in thread
* [RFC 2/5] pwm: Add support for RZ/G2L GPT
2022-04-30 7:59 [RFC 0/5] Add support for RZ/G2L GPT Biju Das
2022-04-30 7:59 ` [RFC 1/5] dt-bindings: pwm: Add RZ/G2L GPT binding Biju Das
@ 2022-04-30 7:59 ` Biju Das
2022-04-30 7:59 ` [RFC 3/5] arm64: dts: renesas: r9a07g044: Add GPT support Biju Das
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Biju Das @ 2022-04-30 7:59 UTC (permalink / raw)
To: Thierry Reding, Lee Jones, Philipp Zabel
Cc: Biju Das, Uwe Kleine-König, linux-pwm, Geert Uytterhoeven,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad,
linux-renesas-soc
RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
(GPT32E). It supports the following functions
* 32 bits × 8 channels
* Up-counting or down-counting (saw waves) or up/down-counting
(triangle waves) for each counter.
* Clock sources independently selectable for each channel
* Two I/O pins per channel
* Two output compare/input capture registers per channel
* For the two output compare/input capture registers of each channel,
four registers are provided as buffer registers and are capable of
operating as comparison registers when buffering is not in use.
* In output compare operation, buffer switching can be at crests or
troughs, enabling the generation of laterally asymmetric PWM waveforms.
* Registers for setting up frame cycles in each channel (with capability
for generating interrupts at overflow or underflow)
* Generation of dead times in PWM operation
* Synchronous starting, stopping and clearing counters for arbitrary
channels
* Starting, stopping, clearing and up/down counters in response to input
level comparison
* Starting, clearing, stopping and up/down counters in response to a
maximum of four external triggers
* Output pin disable function by dead time error and detected
short-circuits between output pins
* A/D converter start triggers can be generated (GPT32E0 to GPT32E3)
* Enables the noise filter for input capture and external trigger
operation
This patch adds basic pwm support for RZ/G2L GPT driver by creating
separate logical channels for each IOs.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pwm/Kconfig | 11 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-rzg2l-gpt.c | 355 ++++++++++++++++++++++++++++++++++++
3 files changed, 367 insertions(+)
create mode 100644 drivers/pwm/pwm-rzg2l-gpt.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index 21e3b05a5153..d93b510f9ca8 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -471,6 +471,17 @@ config PWM_ROCKCHIP
Generic PWM framework driver for the PWM controller found on
Rockchip SoCs.
+config PWM_RZG2L_GPT
+ tristate "Renesas RZ/G2L General PWM Timer support"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ This driver exposes the General PWM Timer controller found in Renesas
+ RZ/G2L like chips through the PWM API.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-rzg2l-gpt.
+
config PWM_SAMSUNG
tristate "Samsung PWM support"
depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 708840b7fba8..bd213ae64074 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_PWM_RASPBERRYPI_POE) += pwm-raspberrypi-poe.o
obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
+obj-$(CONFIG_PWM_RZG2L_GPT) += pwm-rzg2l-gpt.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
new file mode 100644
index 000000000000..8895e17ff902
--- /dev/null
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -0,0 +1,355 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L General PWM Timer (GPT) driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/pwm.h>
+#include <linux/reset.h>
+#include <linux/units.h>
+
+#define GPT_IO_PER_CHANNEL 2
+
+#define GTPR_MAX_VALUE 0xFFFFFFFF
+#define GTCR 0x2c
+#define GTUDDTYC 0x30
+#define GTIOR 0x34
+#define GTBER 0x40
+#define GTCNT 0x48
+#define GTCCRA 0x4c
+#define GTCCRB 0x50
+#define GTPR 0x64
+
+#define GTCR_CST_MASK BIT(0)
+#define GTCR_MD_MASK GENMASK(18, 16)
+#define GTCR_TPCS_MASK GENMASK(26, 24)
+#define GTCR_MD_SAW_WAVE_PWM_MODE (0)
+
+#define GTUDDTYC_UP BIT(0)
+#define GTUDDTYC_UDF BIT(1)
+#define UP_COUNTING (GTUDDTYC_UP | GTUDDTYC_UDF)
+
+#define GTIOR_GTIOA_MASK GENMASK(4, 0)
+#define GTIOR_OAE_MASK BIT(8)
+#define GTIOR_GTIOB_MASK GENMASK(20, 16)
+#define GTIOR_OBE_MASK BIT(24)
+#define GTIOR_GTIOA 0x19
+#define GTIOR_OAE BIT(8)
+#define GTIOR_GTIOB (0x19 << 16)
+#define GTIOR_OBE BIT(24)
+#define GTIOR_GTIOA_OUT_HI_END_LO_CMP_MATCH (GTIOR_GTIOA | GTIOR_OAE)
+#define GTIOR_GTIOB_OUT_HI_END_LO_CMP_MATCH (GTIOR_GTIOB | GTIOR_OBE)
+
+struct phase {
+ u32 value;
+ u32 mask;
+ u32 duty_reg_offset;
+};
+
+static const struct phase phase_params[] = {
+ /* Setting for phase A */
+ {
+ GTIOR_GTIOA_OUT_HI_END_LO_CMP_MATCH,
+ GTIOR_GTIOA_MASK | GTIOR_OAE_MASK,
+ GTCCRA,
+ },
+
+ /* Setting for phase B */
+ {
+ GTIOR_GTIOB_OUT_HI_END_LO_CMP_MATCH,
+ GTIOR_GTIOB_MASK | GTIOR_OBE_MASK,
+ GTCCRB,
+ },
+};
+
+struct rzg2l_gpt_chip;
+
+struct gpt_pwm_device {
+ struct rzg2l_gpt_chip *pc;
+ const struct phase *ph;
+ unsigned int channel; /* IO channel number in the GPT */
+
+ enum pwm_polarity polarity;
+};
+
+struct rzg2l_gpt_chip {
+ struct pwm_chip chip;
+ void __iomem *mmio_base;
+ struct reset_control *rstc;
+ struct clk *clk;
+};
+
+static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)
+{
+ return container_of(chip, struct rzg2l_gpt_chip, chip);
+}
+
+static void rzg2l_gpt_write(struct rzg2l_gpt_chip *pc, u32 data,
+ unsigned int offset)
+{
+ iowrite32(data, pc->mmio_base + offset);
+}
+
+static void rzg2l_gpt_write_mask(struct rzg2l_gpt_chip *pc, u32 data, u32 mask,
+ unsigned int offset)
+{
+ u32 tmp;
+
+ tmp = ioread32(pc->mmio_base + offset);
+ tmp &= ~mask;
+ iowrite32(tmp | data, pc->mmio_base + offset);
+}
+
+static int rzg2l_calculate_prescale(struct rzg2l_gpt_chip *pc, int period_ns)
+{
+ unsigned long long c, clk_rate;
+ unsigned long period_cycles;
+ int prescale;
+ int i, prod;
+
+ clk_rate = clk_get_rate(pc->clk);
+ c = clk_rate * period_ns;
+ period_cycles = div_u64(c, NANO);
+
+ if (period_cycles < 1)
+ period_cycles = 1;
+
+ prescale = -1;
+ /* prescale 1, 4, 16, 64, 256 and 1024 */
+ for (i = 0, prod = 1; i < 6; i++) {
+ if ((period_cycles / GTPR_MAX_VALUE * prod) == 0) {
+ prescale = i;
+ break;
+ }
+
+ prod *= 4;
+ }
+
+ return prescale;
+}
+
+static unsigned long
+rzg2l_time_to_tick_number(struct rzg2l_gpt_chip *pc, int time_ns,
+ unsigned long prescale)
+{
+ unsigned long long c, clk_rate;
+ unsigned long period_cycles;
+ int i, prod;
+
+ clk_rate = clk_get_rate(pc->clk);
+ c = clk_rate * time_ns;
+ period_cycles = div_u64(c, NANO);
+
+ if (period_cycles < 1)
+ period_cycles = 1;
+
+ /* Divide by 1, 4, 16, 64, 256 and 1024 */
+ for (i = 0, prod = 1; i < prescale; i++)
+ prod *= 4;
+
+ return period_cycles / prod;
+}
+
+static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *_pwm)
+{
+ struct rzg2l_gpt_chip *pc = to_rzg2l_gpt_chip(chip);
+ struct gpt_pwm_device *pwm;
+
+ if (_pwm->hwpwm >= GPT_IO_PER_CHANNEL)
+ return -EINVAL;
+
+ pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
+ if (!pwm)
+ return -ENOMEM;
+
+ pwm->pc = pc;
+ pwm->channel = _pwm->hwpwm;
+ pwm->polarity = PWM_POLARITY_NORMAL;
+ pwm->ph = &phase_params[pwm->channel & 0x1];
+ pwm_set_chip_data(_pwm, pwm);
+
+ pm_runtime_get_sync(chip->dev);
+
+ return 0;
+}
+
+static void rzg2l_gpt_free(struct pwm_chip *chip, struct pwm_device *_pwm)
+{
+ struct gpt_pwm_device *pwm = pwm_get_chip_data(_pwm);
+
+ pm_runtime_put(chip->dev);
+ kfree(pwm);
+}
+
+static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *_pwm,
+ int duty_ns, int period_ns)
+{
+ struct gpt_pwm_device *pwm = pwm_get_chip_data(_pwm);
+ struct rzg2l_gpt_chip *pc = to_rzg2l_gpt_chip(chip);
+ unsigned long pv, dc;
+ int prescale;
+
+ if (duty_ns < 0 || period_ns < 0) {
+ dev_err(chip->dev, "ch=%d Set time negative\n", pwm->channel);
+ return -EINVAL;
+ }
+
+ prescale = rzg2l_calculate_prescale(pc, period_ns);
+ if (prescale < 0) {
+ dev_err(chip->dev, "ch=%d wrong prescale val\n", pwm->channel);
+ return -EINVAL;
+ }
+
+ pv = rzg2l_time_to_tick_number(pc, period_ns, prescale);
+ dc = rzg2l_time_to_tick_number(pc, duty_ns, prescale);
+ if (duty_ns == period_ns)
+ dc = pv;
+
+ /* GPT setting saw-wave up-counting */
+ rzg2l_gpt_write_mask(pc, GTCR_MD_SAW_WAVE_PWM_MODE, GTCR_MD_MASK, GTCR);
+ rzg2l_gpt_write_mask(pc, (prescale << 24), GTCR_TPCS_MASK, GTCR);
+ /* Set counting mode */
+ rzg2l_gpt_write(pc, UP_COUNTING, GTUDDTYC);
+ /* Set period */
+ rzg2l_gpt_write(pc, pv, GTPR);
+
+ /* Enable pin output */
+ rzg2l_gpt_write_mask(pc, pwm->ph->value, pwm->ph->mask, GTIOR);
+
+ /* Set duty cycle */
+ rzg2l_gpt_write(pc, dc, pwm->ph->duty_reg_offset);
+
+ /* Set initial value for counter */
+ rzg2l_gpt_write(pc, 0, GTCNT);
+ /* Set no buffer operation */
+ rzg2l_gpt_write(pc, 0, GTBER);
+
+ return 0;
+}
+
+static int rzg2l_gpt_enable(struct rzg2l_gpt_chip *pc)
+{
+ /* Start count */
+ rzg2l_gpt_write_mask(pc, 1, GTCR_CST_MASK, GTCR);
+
+ return 0;
+}
+
+static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *pc)
+{
+ /* Stop count */
+ rzg2l_gpt_write_mask(pc, 0, GTCR_CST_MASK, GTCR);
+}
+
+static int rzg2l_gpt_apply(struct pwm_chip *chip, struct pwm_device *pwm,
+ const struct pwm_state *state)
+{
+ struct rzg2l_gpt_chip *pc = to_rzg2l_gpt_chip(chip);
+ int ret;
+
+ if (!state->enabled) {
+ rzg2l_gpt_disable(pc);
+ return 0;
+ }
+
+ ret = rzg2l_gpt_config(chip, pwm, state->duty_cycle, state->period);
+ if (!ret)
+ ret = rzg2l_gpt_enable(pc);
+
+ return ret;
+}
+
+static const struct pwm_ops rzg2l_gpt_ops = {
+ .request = rzg2l_gpt_request,
+ .free = rzg2l_gpt_free,
+ .apply = rzg2l_gpt_apply,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id rzg2l_gpt_of_table[] = {
+ { .compatible = "renesas,rzg2l-gpt", },
+ { /* Sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table);
+
+static int rzg2l_gpt_probe(struct platform_device *pdev)
+{
+ struct rzg2l_gpt_chip *rzg2l_gpt;
+ int ret;
+
+ rzg2l_gpt = devm_kzalloc(&pdev->dev, sizeof(*rzg2l_gpt), GFP_KERNEL);
+ if (!rzg2l_gpt)
+ return -ENOMEM;
+
+ rzg2l_gpt->mmio_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rzg2l_gpt->mmio_base))
+ return PTR_ERR(rzg2l_gpt->mmio_base);
+
+ rzg2l_gpt->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(rzg2l_gpt->rstc))
+ return dev_err_probe(&pdev->dev, PTR_ERR(rzg2l_gpt->rstc),
+ "get reset failed\n");
+
+ rzg2l_gpt->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(rzg2l_gpt->clk))
+ return dev_err_probe(&pdev->dev, PTR_ERR(rzg2l_gpt->clk),
+ "cannot get clock\n");
+
+ platform_set_drvdata(pdev, rzg2l_gpt);
+
+ ret = reset_control_deassert(rzg2l_gpt->rstc);
+ if (ret) {
+ dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
+ ERR_PTR(ret));
+ return ret;
+ }
+
+ pm_runtime_enable(&pdev->dev);
+
+ rzg2l_gpt->chip.dev = &pdev->dev;
+ rzg2l_gpt->chip.ops = &rzg2l_gpt_ops;
+ rzg2l_gpt->chip.npwm = GPT_IO_PER_CHANNEL;
+
+ ret = pwmchip_add(&rzg2l_gpt->chip);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to register GPT chip: %d\n", ret);
+ pm_runtime_disable(&pdev->dev);
+ reset_control_assert(rzg2l_gpt->rstc);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rzg2l_gpt_remove(struct platform_device *pdev)
+{
+ struct rzg2l_gpt_chip *rzg2l_gpt = platform_get_drvdata(pdev);
+
+ pwmchip_remove(&rzg2l_gpt->chip);
+ pm_runtime_disable(&pdev->dev);
+ reset_control_assert(rzg2l_gpt->rstc);
+
+ return 0;
+}
+
+static struct platform_driver rzg2l_gpt_driver = {
+ .driver = {
+ .name = "pwm-rzg2l-gpt",
+ .of_match_table = of_match_ptr(rzg2l_gpt_of_table),
+ },
+ .probe = rzg2l_gpt_probe,
+ .remove = rzg2l_gpt_remove,
+};
+module_platform_driver(rzg2l_gpt_driver);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/G2L General PWM Timer (GPT) Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pwm-rzg2l-gpt");
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [RFC 3/5] arm64: dts: renesas: r9a07g044: Add GPT support
2022-04-30 7:59 [RFC 0/5] Add support for RZ/G2L GPT Biju Das
2022-04-30 7:59 ` [RFC 1/5] dt-bindings: pwm: Add RZ/G2L GPT binding Biju Das
2022-04-30 7:59 ` [RFC 2/5] pwm: Add support for RZ/G2L GPT Biju Das
@ 2022-04-30 7:59 ` Biju Das
2022-04-30 7:59 ` [RFC 4/5] arm64: dts: renesas: r9a07g054: " Biju Das
2022-04-30 7:59 ` [RFC 5/5] [HACK] PWM testing Biju Das
4 siblings, 0 replies; 8+ messages in thread
From: Biju Das @ 2022-04-30 7:59 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add GPT support by adding pwm nodes to RZ/G2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 192 +++++++++++++++++++++
1 file changed, 192 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 4f9a84d7af08..e5cbe941aead 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -168,6 +168,198 @@ soc: soc {
#size-cells = <2>;
ranges;
+ gpt0: pwm@10048000 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048000 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 222 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt1: pwm@10048100 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048100 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt2: pwm@10048200 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048200 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt3: pwm@10048300 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048300 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 259 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt4: pwm@10048400 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048400 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt5: pwm@10048500 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048500 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt6: pwm@10048600 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048600 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt7: pwm@10048700 {
+ compatible = "renesas,r9a07g044-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048700 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g044-ssi",
"renesas,rz-ssi";
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [RFC 4/5] arm64: dts: renesas: r9a07g054: Add GPT support
2022-04-30 7:59 [RFC 0/5] Add support for RZ/G2L GPT Biju Das
` (2 preceding siblings ...)
2022-04-30 7:59 ` [RFC 3/5] arm64: dts: renesas: r9a07g044: Add GPT support Biju Das
@ 2022-04-30 7:59 ` Biju Das
2022-04-30 7:59 ` [RFC 5/5] [HACK] PWM testing Biju Das
4 siblings, 0 replies; 8+ messages in thread
From: Biju Das @ 2022-04-30 7:59 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add GPT support by adding pwm nodes to RZ/V2L SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 192 +++++++++++++++++++++
1 file changed, 192 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 4313b9e3abed..4a1039572147 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -168,6 +168,198 @@ soc: soc {
#size-cells = <2>;
ranges;
+ gpt0: pwm@10048000 {
+ compatible = "renesas,r9a07g054-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048000 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 222 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
+ resets = <&cpg R9A07G054_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt1: pwm@10048100 {
+ compatible = "renesas,r9a07g054-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048100 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
+ resets = <&cpg R9A07G054_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt2: pwm@10048200 {
+ compatible = "renesas,r9a07g054-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048200 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
+ resets = <&cpg R9A07G054_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt3: pwm@10048300 {
+ compatible = "renesas,r9a07g054-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048300 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 259 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
+ resets = <&cpg R9A07G054_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt4: pwm@10048400 {
+ compatible = "renesas,r9a07g054-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048400 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
+ resets = <&cpg R9A07G054_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt5: pwm@10048500 {
+ compatible = "renesas,r9a07g054-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048500 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
+ resets = <&cpg R9A07G054_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt6: pwm@10048600 {
+ compatible = "renesas,r9a07g054-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048600 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
+ resets = <&cpg R9A07G054_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
+ gpt7: pwm@10048700 {
+ compatible = "renesas,r9a07g054-gpt",
+ "renesas,rzg2l-gpt";
+ reg = <0 0x10048700 0 0xa4>;
+ #pwm-cells = <2>;
+ interrupts = <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd",
+ "cmpe", "cmpf", "adtrga", "adtrgb",
+ "ovf", "unf";
+ clocks = <&cpg CPG_MOD R9A07G054_GPT_PCLK>;
+ resets = <&cpg R9A07G054_GPT_RST_C>;
+ power-domains = <&cpg>;
+ status = "disabled";
+ };
+
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g054-ssi",
"renesas,rz-ssi";
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [RFC 5/5] [HACK] PWM testing
2022-04-30 7:59 [RFC 0/5] Add support for RZ/G2L GPT Biju Das
` (3 preceding siblings ...)
2022-04-30 7:59 ` [RFC 4/5] arm64: dts: renesas: r9a07g054: " Biju Das
@ 2022-04-30 7:59 ` Biju Das
4 siblings, 0 replies; 8+ messages in thread
From: Biju Das @ 2022-04-30 7:59 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi | 5 +++++
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 14 ++++++++++++++
arch/arm64/configs/defconfig | 1 +
arch/arm64/configs/renesas_defconfig | 1 +
4 files changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
index 9085d8c76ce1..55442c359b74 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi
@@ -38,6 +38,11 @@ can1-stb-hog {
line-name = "can1_stb";
};
+ gpt4_pins: gpt {
+ pinmux = <RZG2L_PORT_PINMUX(43, 0, 2)>, /* GTIOC4A */
+ <RZG2L_PORT_PINMUX(43, 1, 2)>; /* GTIOC4B */
+ };
+
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
index aadc41515093..2f9212def887 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
@@ -16,6 +16,20 @@ aliases {
serial1 = &scif2;
i2c3 = &i2c3;
};
+#if 0
+ backlight {
+ compatible = "pwm-backlight";
+ pwms = <&gpt4 0 500000000>;
+ brightness-levels = <0 2 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ };
+#endif
+};
+
+&gpt4 {
+ pinctrl-0 = <&gpt4_pins>;
+ pinctrl-names = "default";
+ status = "okay";
};
&i2c3 {
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2836f3c5d361..b8c1b2115e36 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1139,6 +1139,7 @@ CONFIG_PWM_MTK_DISP=m
CONFIG_PWM_MEDIATEK=m
CONFIG_PWM_RCAR=m
CONFIG_PWM_RENESAS_TPU=m
+CONFIG_PWM_RZG2L_GPT=m
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SAMSUNG=y
CONFIG_PWM_SL28CPLD=m
diff --git a/arch/arm64/configs/renesas_defconfig b/arch/arm64/configs/renesas_defconfig
index 8702f71b2e20..f86f5ab472da 100644
--- a/arch/arm64/configs/renesas_defconfig
+++ b/arch/arm64/configs/renesas_defconfig
@@ -354,6 +354,7 @@ CONFIG_RZG2L_ADC=y
CONFIG_PWM=y
CONFIG_PWM_RCAR=y
CONFIG_PWM_RENESAS_TPU=y
+CONFIG_PWM_RZG2L_GPT=y
CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_PHY_RCAR_GEN3_PCIE=y
CONFIG_PHY_RCAR_GEN3_USB2=y
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread