* [PATCH v2 0/3] Add support for linking gpt with poeg
@ 2022-11-11 19:29 Biju Das
2022-11-11 19:29 ` [DO NOT APPLY PATCH 1/3] dt-bindings: pwm: Add RZ/G2L GPT binding Biju Das
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Biju Das @ 2022-11-11 19:29 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Uwe Kleine-König, linux-pwm, devicetree,
Geert Uytterhoeven, Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc
Renesas RZ/G2L gpt supports output pin disable function by dead time
error and detecting short-circuits between output pins. There are 4
poeg groups shared between gpt channels.
This patch adds support for linking poeg group with gpt channel, so that
gpt channel can control the output disable function through poeg module(port
output enable for gpt)
v1->v2:
* removed quotes from ref
* Added maxItems and minItems for renesas,poegs property
* Added enums for gpt index
* Replaced id->poeg-id as per poeg bindings in patch#3.
patch#1 is just added to avoid bot errors.
[1] https://lore.kernel.org/linux-renesas-soc/20221111162325.471963-2-biju.das.jz@bp.renesas.com/T/#u
Patch#3 depend upon [2]
[2] https://lore.kernel.org/linux-renesas-soc/20221111162325.471963-3-biju.das.jz@bp.renesas.com/T/#u
Biju Das (3):
dt-bindings: pwm: Add RZ/G2L GPT binding
dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
pwm: rzg2l-gpt: Add support for linking with poeg
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 401 ++++++++++++++++++
drivers/pwm/pwm-rzg2l-gpt.c | 69 +++
2 files changed, 470 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [DO NOT APPLY PATCH 1/3] dt-bindings: pwm: Add RZ/G2L GPT binding
2022-11-11 19:29 [PATCH v2 0/3] Add support for linking gpt with poeg Biju Das
@ 2022-11-11 19:29 ` Biju Das
2022-11-11 19:29 ` [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju Das
2022-11-11 19:29 ` [PATCH v2 3/3] pwm: rzg2l-gpt: Add support for linking with poeg Biju Das
2 siblings, 0 replies; 10+ messages in thread
From: Biju Das @ 2022-11-11 19:29 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Uwe Kleine-König, linux-pwm, devicetree,
Geert Uytterhoeven, Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc, Rob Herring
Add device tree bindings for the General PWM Timer (GPT).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
sending[1] to avoid bot error for the next patch.
[1] https://lore.kernel.org/linux-renesas-soc/20221111162325.471963-2-biju.das.jz@bp.renesas.com/T/#u
---
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 378 ++++++++++++++++++
1 file changed, 378 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
new file mode 100644
index 000000000000..620d5ae4ae30
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
@@ -0,0 +1,378 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/renesas,rzg2l-gpt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L General PWM Timer (GPT)
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+description: |
+ RZ/G2L General PWM Timer (GPT) composed of 8 channels with 32-bit timer
+ (GPT32E). It supports the following functions
+ * 32 bits × 8 channels.
+ * Up-counting or down-counting (saw waves) or up/down-counting
+ (triangle waves) for each counter.
+ * Clock sources independently selectable for each channel.
+ * Two I/O pins per channel.
+ * Two output compare/input capture registers per channel.
+ * For the two output compare/input capture registers of each channel,
+ four registers are provided as buffer registers and are capable of
+ operating as comparison registers when buffering is not in use.
+ * In output compare operation, buffer switching can be at crests or
+ troughs, enabling the generation of laterally asymmetric PWM waveforms.
+ * Registers for setting up frame cycles in each channel (with capability
+ for generating interrupts at overflow or underflow)
+ * Generation of dead times in PWM operation.
+ * Synchronous starting, stopping and clearing counters for arbitrary
+ channels.
+ * Starting, stopping, clearing and up/down counters in response to input
+ level comparison.
+ * Starting, clearing, stopping and up/down counters in response to a
+ maximum of four external triggers.
+ * Output pin disable function by dead time error and detected
+ short-circuits between output pins.
+ * A/D converter start triggers can be generated (GPT32E0 to GPT32E3)
+ * Enables the noise filter for input capture and external trigger
+ operation.
+
+ The below pwm channels are supported.
+ pwm0 - GPT32E0.GTIOC0A channel
+ pwm1 - GPT32E0.GTIOC0B channel
+ pwm2 - GPT32E1.GTIOC1A channel
+ pwm3 - GPT32E1.GTIOC1B channel
+ pwm4 - GPT32E2.GTIOC2A channel
+ pwm5 - GPT32E2.GTIOC2B channel
+ pwm6 - GPT32E3.GTIOC3A channel
+ pwm7 - GPT32E3.GTIOC3B channel
+ pwm8 - GPT32E4.GTIOC4A channel
+ pwm9 - GPT32E4.GTIOC4B channel
+ pwm10 - GPT32E5.GTIOC5A channel
+ pwm11 - GPT32E5.GTIOC5B channel
+ pwm12 - GPT32E6.GTIOC6A channel
+ pwm13 - GPT32E6.GTIOC6B channel
+ pwm14 - GPT32E7.GTIOC7A channel
+ pwm15 - GPT32E7.GTIOC7B channel
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r9a07g044-gpt # RZ/G2{L,LC}
+ - renesas,r9a07g054-gpt # RZ/V2L
+ - const: renesas,rzg2l-gpt
+
+ reg:
+ maxItems: 1
+
+ '#pwm-cells':
+ const: 2
+
+ interrupts:
+ items:
+ - description: GPT32E0.GTCCRA input capture/compare match
+ - description: GPT32E0.GTCCRB input capture/compare
+ - description: GPT32E0.GTCCRC compare match
+ - description: GPT32E0.GTCCRD compare match
+ - description: GPT32E0.GTCCRE compare match
+ - description: GPT32E0.GTCCRF compare match
+ - description: GPT32E0.GTADTRA compare match
+ - description: GPT32E0.GTADTRB compare match
+ - description: GPT32E0.GTCNT overflow/GTPR compare match
+ - description: GPT32E0.GTCNT underflow
+ - description: GPT32E1.GTCCRA input capture/compare match
+ - description: GPT32E1.GTCCRB input capture/compare
+ - description: GPT32E1.GTCCRC compare match
+ - description: GPT32E1.GTCCRD compare match
+ - description: GPT32E1.GTCCRE compare match
+ - description: GPT32E1.GTCCRF compare match
+ - description: GPT32E1.GTADTRA compare match
+ - description: GPT32E1.GTADTRB compare match
+ - description: GPT32E1.GTCNT overflow/GTPR compare match
+ - description: GPT32E1.GTCNT underflow
+ - description: GPT32E2.GTCCRA input capture/compare match
+ - description: GPT32E2.GTCCRB input capture/compare
+ - description: GPT32E2.GTCCRC compare match
+ - description: GPT32E2.GTCCRD compare match
+ - description: GPT32E2.GTCCRE compare match
+ - description: GPT32E2.GTCCRF compare match
+ - description: GPT32E2.GTADTRA compare match
+ - description: GPT32E2.GTADTRB compare match
+ - description: GPT32E2.GTCNT overflow/GTPR compare match
+ - description: GPT32E2.GTCNT underflow
+ - description: GPT32E3.GTCCRA input capture/compare match
+ - description: GPT32E3.GTCCRB input capture/compare
+ - description: GPT32E3.GTCCRC compare match
+ - description: GPT32E3.GTCCRD compare match
+ - description: GPT32E3.GTCCRE compare match
+ - description: GPT32E3.GTCCRF compare match
+ - description: GPT32E3.GTADTRA compare match
+ - description: GPT32E3.GTADTRB compare match
+ - description: GPT32E3.GTCNT overflow/GTPR compare match
+ - description: GPT32E3.GTCNT underflow
+ - description: GPT32E4.GTCCRA input capture/compare match
+ - description: GPT32E4.GTCCRB input capture/compare
+ - description: GPT32E4.GTCCRC compare match
+ - description: GPT32E4.GTCCRD compare match
+ - description: GPT32E4.GTCCRE compare match
+ - description: GPT32E4.GTCCRF compare match
+ - description: GPT32E4.GTADTRA compare match
+ - description: GPT32E4.GTADTRB compare match
+ - description: GPT32E4.GTCNT overflow/GTPR compare match
+ - description: GPT32E4.GTCNT underflow
+ - description: GPT32E5.GTCCRA input capture/compare match
+ - description: GPT32E5.GTCCRB input capture/compare
+ - description: GPT32E5.GTCCRC compare match
+ - description: GPT32E5.GTCCRD compare match
+ - description: GPT32E5.GTCCRE compare match
+ - description: GPT32E5.GTCCRF compare match
+ - description: GPT32E5.GTADTRA compare match
+ - description: GPT32E5.GTADTRB compare match
+ - description: GPT32E5.GTCNT overflow/GTPR compare match
+ - description: GPT32E5.GTCNT underflow
+ - description: GPT32E6.GTCCRA input capture/compare match
+ - description: GPT32E6.GTCCRB input capture/compare
+ - description: GPT32E6.GTCCRC compare match
+ - description: GPT32E6.GTCCRD compare match
+ - description: GPT32E6.GTCCRE compare match
+ - description: GPT32E6.GTCCRF compare match
+ - description: GPT32E6.GTADTRA compare match
+ - description: GPT32E6.GTADTRB compare match
+ - description: GPT32E6.GTCNT overflow/GTPR compare match
+ - description: GPT32E6.GTCNT underflow
+ - description: GPT32E7.GTCCRA input capture/compare match
+ - description: GPT32E7.GTCCRB input capture/compare
+ - description: GPT32E7.GTCCRC compare match
+ - description: GPT32E7.GTCCRD compare match
+ - description: GPT32E7.GTCCRE compare match
+ - description: GPT32E7.GTCCRF compare match
+ - description: GPT32E7.GTADTRA compare match
+ - description: GPT32E7.GTADTRB compare match
+ - description: GPT32E7.GTCNT overflow/GTPR compare match
+ - description: GPT32E7.GTCNT underflow
+
+ interrupt-names:
+ items:
+ - const: ccmpa0
+ - const: ccmpb0
+ - const: cmpc0
+ - const: cmpd0
+ - const: cmpe0
+ - const: cmpf0
+ - const: adtrga0
+ - const: adtrgb0
+ - const: ovf0
+ - const: unf0
+ - const: ccmpa1
+ - const: ccmpb1
+ - const: cmpc1
+ - const: cmpd1
+ - const: cmpe1
+ - const: cmpf1
+ - const: adtrga1
+ - const: adtrgb1
+ - const: ovf1
+ - const: unf1
+ - const: ccmpa2
+ - const: ccmpb2
+ - const: cmpc2
+ - const: cmpd2
+ - const: cmpe2
+ - const: cmpf2
+ - const: adtrga2
+ - const: adtrgb2
+ - const: ovf2
+ - const: unf2
+ - const: ccmpa3
+ - const: ccmpb3
+ - const: cmpc3
+ - const: cmpd3
+ - const: cmpe3
+ - const: cmpf3
+ - const: adtrga3
+ - const: adtrgb3
+ - const: ovf3
+ - const: unf3
+ - const: ccmpa4
+ - const: ccmpb4
+ - const: cmpc4
+ - const: cmpd4
+ - const: cmpe4
+ - const: cmpf4
+ - const: adtrga4
+ - const: adtrgb4
+ - const: ovf4
+ - const: unf4
+ - const: ccmpa5
+ - const: ccmpb5
+ - const: cmpc5
+ - const: cmpd5
+ - const: cmpe5
+ - const: cmpf5
+ - const: adtrga5
+ - const: adtrgb5
+ - const: ovf5
+ - const: unf5
+ - const: ccmpa6
+ - const: ccmpb6
+ - const: cmpc6
+ - const: cmpd6
+ - const: cmpe6
+ - const: cmpf6
+ - const: adtrga6
+ - const: adtrgb6
+ - const: ovf6
+ - const: unf6
+ - const: ccmpa7
+ - const: ccmpb7
+ - const: cmpc7
+ - const: cmpd7
+ - const: cmpe7
+ - const: cmpf7
+ - const: adtrga7
+ - const: adtrgb7
+ - const: ovf7
+ - const: unf7
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - power-domains
+ - resets
+
+allOf:
+ - $ref: pwm.yaml#
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gpt: pwm@10048000 {
+ compatible = "renesas,r9a07g044-gpt", "renesas,rzg2l-gpt";
+ reg = <0x10048000 0x800>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 221 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 222 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 225 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 226 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 227 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 237 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 257 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 258 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 259 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 273 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 274 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 275 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 276 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 278 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 284 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ccmpa0", "ccmpb0", "cmpc0", "cmpd0",
+ "cmpe0", "cmpf0", "adtrga0", "adtrgb0",
+ "ovf0", "unf0",
+ "ccmpa1", "ccmpb1", "cmpc1", "cmpd1",
+ "cmpe1", "cmpf1", "adtrga1", "adtrgb1",
+ "ovf1", "unf1",
+ "ccmpa2", "ccmpb2", "cmpc2", "cmpd2",
+ "cmpe2", "cmpf2", "adtrga2", "adtrgb2",
+ "ovf2", "unf2",
+ "ccmpa3", "ccmpb3", "cmpc3", "cmpd3",
+ "cmpe3", "cmpf3", "adtrga3", "adtrgb3",
+ "ovf3", "unf3",
+ "ccmpa4", "ccmpb4", "cmpc4", "cmpd4",
+ "cmpe4", "cmpf4", "adtrga4", "adtrgb4",
+ "ovf4", "unf4",
+ "ccmpa5", "ccmpb5", "cmpc5", "cmpd5",
+ "cmpe5", "cmpf5", "adtrga5", "adtrgb5",
+ "ovf5", "unf5",
+ "ccmpa6", "ccmpb6", "cmpc6", "cmpd6",
+ "cmpe6", "cmpf6", "adtrga6", "adtrgb6",
+ "ovf6", "unf6",
+ "ccmpa7", "ccmpb7", "cmpc7", "cmpd7",
+ "cmpe7", "cmpf7", "adtrga7", "adtrgb7",
+ "ovf7", "unf7";
+ clocks = <&cpg CPG_MOD R9A07G044_GPT_PCLK>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_GPT_RST_C>;
+ #pwm-cells = <2>;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
2022-11-11 19:29 [PATCH v2 0/3] Add support for linking gpt with poeg Biju Das
2022-11-11 19:29 ` [DO NOT APPLY PATCH 1/3] dt-bindings: pwm: Add RZ/G2L GPT binding Biju Das
@ 2022-11-11 19:29 ` Biju Das
2022-11-12 0:10 ` Rob Herring
2022-11-15 1:46 ` Rob Herring
2022-11-11 19:29 ` [PATCH v2 3/3] pwm: rzg2l-gpt: Add support for linking with poeg Biju Das
2 siblings, 2 replies; 10+ messages in thread
From: Biju Das @ 2022-11-11 19:29 UTC (permalink / raw)
To: Thierry Reding, Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Uwe Kleine-König, linux-pwm, devicetree,
Geert Uytterhoeven, Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc
RZ/G2L GPT IP supports output pin disable function by dead time
error and detecting short-circuits between output pins.
Add documentation for the optional property renesas,poegs to
link a pair of GPT IOs with POEG.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* removed quotes from ref
* Added maxItems and minItems for renesas,poegs property
* Added enums for gpt index
---
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
index 620d5ae4ae30..5219032c60ee 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
@@ -245,6 +245,28 @@ properties:
resets:
maxItems: 1
+ renesas,poegs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ maxItems: 8
+ minItems: 1
+ items:
+ - description: phandle to POEG instance that serves the output disable
+ - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
+ description: |
+ An index identifying pair of GPT channels.
+ <0> : GPT channels 0 and 1
+ <1> : GPT channels 2 and 3
+ <2> : GPT channels 4 and 5
+ <3> : GPT channels 6 and 7
+ <4> : GPT channels 8 and 9
+ <5> : GPT channels 10 and 11
+ <6> : GPT channels 12 and 13
+ <7> : GPT channels 14 and 15
+ description:
+ A list of phandle and channel index pair tuples to the POEGs that handle the
+ output disable for the GPT channels.
+
required:
- compatible
- reg
@@ -375,4 +397,5 @@ examples:
power-domains = <&cpg>;
resets = <&cpg R9A07G044_GPT_RST_C>;
#pwm-cells = <2>;
+ renesas,poegs = <&poeggd 4>;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v2 3/3] pwm: rzg2l-gpt: Add support for linking with poeg
2022-11-11 19:29 [PATCH v2 0/3] Add support for linking gpt with poeg Biju Das
2022-11-11 19:29 ` [DO NOT APPLY PATCH 1/3] dt-bindings: pwm: Add RZ/G2L GPT binding Biju Das
2022-11-11 19:29 ` [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju Das
@ 2022-11-11 19:29 ` Biju Das
2022-11-28 13:01 ` Uwe Kleine-König
2 siblings, 1 reply; 10+ messages in thread
From: Biju Das @ 2022-11-11 19:29 UTC (permalink / raw)
To: Thierry Reding
Cc: Biju Das, Uwe Kleine-König, linux-pwm, Geert Uytterhoeven,
Chris Paterson, Prabhakar Mahadev Lad, linux-renesas-soc
This patch add support for linking poeg group with gpt, so that
gpt can control the output disable function.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
* Replaced id->poeg-id as per poeg bindings.
This patch depend upon [1]
[1] https://lore.kernel.org/linux-renesas-soc/20221111162325.471963-3-biju.das.jz@bp.renesas.com/T/#u
---
drivers/pwm/pwm-rzg2l-gpt.c | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index 3f9325e958b8..e16f976c3dcb 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -31,6 +31,7 @@
#define RZG2L_GTCR 0x2c
#define RZG2L_GTUDDTYC 0x30
#define RZG2L_GTIOR 0x34
+#define RZG2L_GTINTAD 0x38
#define RZG2L_GTBER 0x40
#define RZG2L_GTCNT 0x48
#define RZG2L_GTCCRA 0x4c
@@ -48,9 +49,15 @@
#define RZG2L_UP_COUNTING (RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF)
#define RZG2L_GTIOR_GTIOA GENMASK(4, 0)
+#define RZG2L_GTIOR_OADF GENMASK(10, 9)
#define RZG2L_GTIOR_GTIOB GENMASK(20, 16)
+#define RZG2L_GTIOR_OBDF GENMASK(26, 25)
#define RZG2L_GTIOR_OAE BIT(8)
#define RZG2L_GTIOR_OBE BIT(24)
+#define RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE BIT(9)
+#define RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE BIT(25)
+#define RZG2L_GTIOR_PIN_DISABLE_SETTING \
+ (RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE | RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE)
#define RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE 0x07
#define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE 0x1b
@@ -64,12 +71,16 @@
#define RZG2L_GTIOR_GTIOB_OUT_LO_END_TOGGLE_CMP_MATCH \
(FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE)
+#define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24)
+
#define RZG2L_GTCCR(i) (0x4c + 4 * (i))
#define RZG2L_MAX_HW_CHANNELS (8)
#define RZG2L_CHANNELS_PER_IO (2)
#define RZG2L_MAX_PWM_CHANNELS (RZG2L_MAX_HW_CHANNELS * RZG2L_CHANNELS_PER_IO)
+#define RZG2L_MAX_POEG_GROUPS (4)
+
#define RZG2L_IS_IOB(a) ((a) & 0x1)
#define RZG2L_GET_CH_INDEX(a) ((a) / 2)
@@ -85,6 +96,7 @@ struct rzg2l_gpt_chip {
u32 state_period[RZG2L_MAX_HW_CHANNELS];
u32 user_count[RZG2L_MAX_HW_CHANNELS];
u8 prescale[RZG2L_MAX_HW_CHANNELS];
+ DECLARE_BITMAP(poeg_gpt_link, RZG2L_MAX_POEG_GROUPS * RZG2L_MAX_HW_CHANNELS);
};
static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)
@@ -438,6 +450,62 @@ static void rzg2l_gpt_reset_assert_pm_disable(void *data)
reset_control_assert(rzg2l_gpt->rstc);
}
+static void rzg2l_gpt_parse_properties(struct platform_device *pdev,
+ struct rzg2l_gpt_chip *rzg2l_gpt)
+{
+ struct of_phandle_args of_args;
+ unsigned int i;
+ u32 poeg_grp;
+ int cells;
+ u32 offs;
+ int ret;
+
+ cells = of_property_count_u32_elems(pdev->dev.of_node, "renesas,poegs");
+ if (cells == -EINVAL)
+ return;
+
+ cells >>= 1;
+ for (i = 0; i < cells; i++) {
+ ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
+ "renesas,poegs", 1, i,
+ &of_args);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Failed to parse 'renesas,poegs' property\n");
+ return;
+ }
+
+ if (of_args.args[0] >= RZG2L_MAX_HW_CHANNELS) {
+ dev_err(&pdev->dev,
+ "Invalid channel %d > 7\n", of_args.args[0]);
+ return;
+ }
+
+ if (!of_device_is_available(of_args.np)) {
+ /* It's fine to have a phandle to a non-enabled poeg. */
+ of_node_put(of_args.np);
+ continue;
+ }
+
+ if (!of_property_read_u32(of_args.np, "renesas,poeg-id", &poeg_grp)) {
+ offs = RZG2L_GET_CH_OFFS(of_args.args[0]);
+
+ set_bit(poeg_grp * RZG2L_MAX_HW_CHANNELS + of_args.args[0],
+ rzg2l_gpt->poeg_gpt_link);
+
+ rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD,
+ RZG2L_GTINTAD_GRP_MASK,
+ poeg_grp << 24);
+
+ rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR,
+ RZG2L_GTIOR_OBDF | RZG2L_GTIOR_OADF,
+ RZG2L_GTIOR_PIN_DISABLE_SETTING);
+ }
+
+ of_node_put(of_args.np);
+ }
+}
+
static int rzg2l_gpt_probe(struct platform_device *pdev)
{
DECLARE_BITMAP(ch_en_bits, RZG2L_MAX_PWM_CHANNELS);
@@ -480,6 +548,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
if (ret < 0)
goto clk_disable;
+ rzg2l_gpt_parse_properties(pdev, rzg2l_gpt);
mutex_init(&rzg2l_gpt->lock);
platform_set_drvdata(pdev, rzg2l_gpt);
bitmap_zero(ch_en_bits, RZG2L_MAX_PWM_CHANNELS);
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
2022-11-11 19:29 ` [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju Das
@ 2022-11-12 0:10 ` Rob Herring
2022-11-12 9:33 ` Biju Das
2022-11-15 1:46 ` Rob Herring
1 sibling, 1 reply; 10+ messages in thread
From: Rob Herring @ 2022-11-12 0:10 UTC (permalink / raw)
To: Biju Das
Cc: Chris Paterson, linux-renesas-soc, Uwe Kleine-König,
Geert Uytterhoeven, devicetree, Prabhakar Mahadev Lad,
Rob Herring, Thierry Reding, linux-pwm, Krzysztof Kozlowski
On Fri, 11 Nov 2022 19:29:41 +0000, Biju Das wrote:
> RZ/G2L GPT IP supports output pin disable function by dead time
> error and detecting short-circuits between output pins.
>
> Add documentation for the optional property renesas,poegs to
> link a pair of GPT IOs with POEG.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
> * removed quotes from ref
> * Added maxItems and minItems for renesas,poegs property
> * Added enums for gpt index
> ---
> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml: properties:renesas,poegs:items: 'oneOf' conditional failed, one must be fixed:
{'maxItems': 8, 'minItems': 1, 'items': [{'description': 'phandle to POEG instance that serves the output disable'}, {'enum': [0, 1, 2, 3, 4, 5, 6, 7], 'description': 'An index identifying pair of GPT channels.\n <0> : GPT channels 0 and 1\n <1> : GPT channels 2 and 3\n <2> : GPT channels 4 and 5\n <3> : GPT channels 6 and 7\n <4> : GPT channels 8 and 9\n <5> : GPT channels 10 and 11\n <6> : GPT channels 12 and 13\n <7> : GPT channels 14 and 15\n'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
{'maxItems': 8, 'minItems': 1, 'items': [{'description': 'phandle to POEG instance that serves the output disable'}, {'enum': [0, 1, 2, 3, 4, 5, 6, 7], 'description': 'An index identifying pair of GPT channels.\n <0> : GPT channels 0 and 1\n <1> : GPT channels 2 and 3\n <2> : GPT channels 4 and 5\n <3> : GPT channels 6 and 7\n <4> : GPT channels 8 and 9\n <5> : GPT channels 10 and 11\n <6> : GPT channels 12 and 13\n <7> : GPT channels 14 and 15\n'}]} is not of type 'array'
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
2022-11-12 0:10 ` Rob Herring
@ 2022-11-12 9:33 ` Biju Das
0 siblings, 0 replies; 10+ messages in thread
From: Biju Das @ 2022-11-12 9:33 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Chris Paterson, linux-renesas-soc, Uwe Kleine-König,
Geert Uytterhoeven, devicetree, Prabhakar Mahadev Lad,
Rob Herring, Thierry Reding, linux-pwm, Krzysztof Kozlowski
Hi Rob and Krzysztof Kozlowski,
> Subject: Re: [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document
> renesas,poegs property
>
>
> On Fri, 11 Nov 2022 19:29:41 +0000, Biju Das wrote:
> > RZ/G2L GPT IP supports output pin disable function by dead time error
> > and detecting short-circuits between output pins.
> >
> > Add documentation for the optional property renesas,poegs to link a
> > pair of GPT IOs with POEG.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> > * removed quotes from ref
> > * Added maxItems and minItems for renesas,poegs property
> > * Added enums for gpt index
> > ---
> > .../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 +++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-
> ci/linux/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml:
> properties:renesas,poegs:items: 'oneOf' conditional failed, one must be
> fixed:
> {'maxItems': 8, 'minItems': 1, 'items': [{'description': 'phandle to
> POEG instance that serves the output disable'}, {'enum': [0, 1, 2, 3, 4, 5,
> 6, 7], 'description': 'An index identifying pair of GPT channels.\n <0> :
> GPT channels 0 and 1\n <1> : GPT channels 2 and 3\n <2> : GPT channels 4
> and 5\n <3> : GPT channels 6 and 7\n <4> : GPT channels 8 and 9\n <5> :
> GPT channels 10 and 11\n <6> : GPT channels 12 and 13\n <7> : GPT channels
> 14 and 15\n'}]} should not be valid under {'required': ['maxItems']}
> hint: "maxItems" is not needed with an "items" list
> {'maxItems': 8, 'minItems': 1, 'items': [{'description': 'phandle to
> POEG instance that serves the output disable'}, {'enum': [0, 1, 2, 3, 4, 5,
> 6, 7], 'description': 'An index identifying pair of GPT channels.\n <0> :
> GPT channels 0 and 1\n <1> : GPT channels 2 and 3\n <2> : GPT channels 4
> and 5\n <3> : GPT channels 6 and 7\n <4> : GPT channels 8 and 9\n <5> :
> GPT channels 10 and 11\n <6> : GPT channels 12 and 13\n <7> : GPT channels
> 14 and 15\n'}]} is not of type 'array'
> from schema $id:
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above error(s),
> then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
I am able to reproduce the issue reported by bot[1]. Looks like we should not add maxItems for Items.
The check is passing, if we just add minItems for Items.
Please let me know shall I drop maxItems and just add minItems with an "items" list?
Or
Drop both from "items" list.
[1]
~/dt-binding-check.sh Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
bindings file ### Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml ####
checking bindings
LINT Documentation/devicetree/bindings
CHKDT Documentation/devicetree/bindings/processed-schema.json
/home/biju/renesas-devel/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml: properties:renesas,poegs:items: 'oneOf' conditional failed, one must be fixed:
{'maxItems': 8, 'minItems': 1, 'items': [{'description': 'phandle to POEG instance that serves the output disable'}, {'enum': [0, 1, 2, 3, 4, 5, 6, 7], 'description': 'An index identifying pair of GPT channels.\n <0> : GPT channels 0 and 1\n <1> : GPT channels 2 and 3\n <2> : GPT channels 4 and 5\n <3> : GPT channels 6 and 7\n <4> : GPT channels 8 and 9\n <5> : GPT channels 10 and 11\n <6> : GPT channels 12 and 13\n <7> : GPT channels 14 and 15\n'}]} should not be valid under {'required': ['maxItems']}
hint: "maxItems" is not needed with an "items" list
{'maxItems': 8, 'minItems': 1, 'items': [{'description': 'phandle to POEG instance that serves the output disable'}, {'enum': [0, 1, 2, 3, 4, 5, 6, 7], 'description': 'An index identifying pair of GPT channels.\n <0> : GPT channels 0 and 1\n <1> : GPT channels 2 and 3\n <2> : GPT channels 4 and 5\n <3> : GPT channels 6 and 7\n <4> : GPT channels 8 and 9\n <5> : GPT channels 10 and 11\n <6> : GPT channels 12 and 13\n <7> : GPT channels 14 and 15\n'}]} is not of type 'array'
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
SCHEMA Documentation/devicetree/bindings/processed-schema.json
DTC_CHK Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.example.dtb
Cheers,
Biju
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
2022-11-11 19:29 ` [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju Das
2022-11-12 0:10 ` Rob Herring
@ 2022-11-15 1:46 ` Rob Herring
2022-11-15 7:02 ` Biju Das
1 sibling, 1 reply; 10+ messages in thread
From: Rob Herring @ 2022-11-15 1:46 UTC (permalink / raw)
To: Biju Das
Cc: Thierry Reding, Krzysztof Kozlowski, Uwe Kleine-König,
linux-pwm, devicetree, Geert Uytterhoeven, Chris Paterson,
Prabhakar Mahadev Lad, linux-renesas-soc
On Fri, Nov 11, 2022 at 07:29:41PM +0000, Biju Das wrote:
> RZ/G2L GPT IP supports output pin disable function by dead time
> error and detecting short-circuits between output pins.
>
> Add documentation for the optional property renesas,poegs to
> link a pair of GPT IOs with POEG.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
> * removed quotes from ref
> * Added maxItems and minItems for renesas,poegs property
> * Added enums for gpt index
> ---
> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 +++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> index 620d5ae4ae30..5219032c60ee 100644
> --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> @@ -245,6 +245,28 @@ properties:
> resets:
> maxItems: 1
>
> + renesas,poegs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + maxItems: 8
> + minItems: 1
I think you want these moved up a level with the 1st 'items'. It's 1-8
tuples, right?
> + items:
> + - description: phandle to POEG instance that serves the output disable
> + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
> + description: |
> + An index identifying pair of GPT channels.
> + <0> : GPT channels 0 and 1
> + <1> : GPT channels 2 and 3
> + <2> : GPT channels 4 and 5
> + <3> : GPT channels 6 and 7
> + <4> : GPT channels 8 and 9
> + <5> : GPT channels 10 and 11
> + <6> : GPT channels 12 and 13
> + <7> : GPT channels 14 and 15
> + description:
> + A list of phandle and channel index pair tuples to the POEGs that handle the
> + output disable for the GPT channels.
> +
> required:
> - compatible
> - reg
> @@ -375,4 +397,5 @@ examples:
> power-domains = <&cpg>;
> resets = <&cpg R9A07G044_GPT_RST_C>;
> #pwm-cells = <2>;
> + renesas,poegs = <&poeggd 4>;
> };
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property
2022-11-15 1:46 ` Rob Herring
@ 2022-11-15 7:02 ` Biju Das
0 siblings, 0 replies; 10+ messages in thread
From: Biju Das @ 2022-11-15 7:02 UTC (permalink / raw)
To: Rob Herring
Cc: Thierry Reding, Krzysztof Kozlowski, Uwe Kleine-König,
linux-pwm, devicetree, Geert Uytterhoeven, Chris Paterson,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Rob,
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 15 November 2022 01:46
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Thierry Reding <thierry.reding@gmail.com>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Uwe Kleine-König <u.kleine-
> koenig@pengutronix.de>; linux-pwm@vger.kernel.org;
> devicetree@vger.kernel.org; Geert Uytterhoeven
> <geert+renesas@glider.be>; Chris Paterson
> <Chris.Paterson2@renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>; linux-renesas-
> soc@vger.kernel.org
> Subject: Re: [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document
> renesas,poegs property
>
> On Fri, Nov 11, 2022 at 07:29:41PM +0000, Biju Das wrote:
> > RZ/G2L GPT IP supports output pin disable function by dead time
> error
> > and detecting short-circuits between output pins.
> >
> > Add documentation for the optional property renesas,poegs to link a
> > pair of GPT IOs with POEG.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> > * removed quotes from ref
> > * Added maxItems and minItems for renesas,poegs property
> > * Added enums for gpt index
> > ---
> > .../bindings/pwm/renesas,rzg2l-gpt.yaml | 23
> +++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> > b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> > index 620d5ae4ae30..5219032c60ee 100644
> > --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> > +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> > @@ -245,6 +245,28 @@ properties:
> > resets:
> > maxItems: 1
> >
> > + renesas,poegs:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + items:
> > + maxItems: 8
> > + minItems: 1
>
> I think you want these moved up a level with the 1st 'items'. It's 1-8
> tuples, right?
Yes, I want something like below, so that a gpt channel can be linked to a poeggroup.
renesas,poegs = <&poegga 0>, <&poeggb 1>, <&poegga 2>, <&poeggd 4>, <&poeggb 5>;
Thanks, I moved this up a level and the checks are now passing.
renesas,poegs:
+ maxItems: 8
+ minItems: 1
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- maxItems: 8
- minItems: 1
Cheers,
Biju
>
> > + items:
> > + - description: phandle to POEG instance that serves the
> output disable
> > + - enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
> > + description: |
> > + An index identifying pair of GPT channels.
> > + <0> : GPT channels 0 and 1
> > + <1> : GPT channels 2 and 3
> > + <2> : GPT channels 4 and 5
> > + <3> : GPT channels 6 and 7
> > + <4> : GPT channels 8 and 9
> > + <5> : GPT channels 10 and 11
> > + <6> : GPT channels 12 and 13
> > + <7> : GPT channels 14 and 15
> > + description:
> > + A list of phandle and channel index pair tuples to the POEGs
> that handle the
> > + output disable for the GPT channels.
> > +
> > required:
> > - compatible
> > - reg
> > @@ -375,4 +397,5 @@ examples:
> > power-domains = <&cpg>;
> > resets = <&cpg R9A07G044_GPT_RST_C>;
> > #pwm-cells = <2>;
> > + renesas,poegs = <&poeggd 4>;
> > };
> > --
> > 2.25.1
> >
> >
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] pwm: rzg2l-gpt: Add support for linking with poeg
2022-11-11 19:29 ` [PATCH v2 3/3] pwm: rzg2l-gpt: Add support for linking with poeg Biju Das
@ 2022-11-28 13:01 ` Uwe Kleine-König
2022-11-28 13:46 ` Biju Das
0 siblings, 1 reply; 10+ messages in thread
From: Uwe Kleine-König @ 2022-11-28 13:01 UTC (permalink / raw)
To: Biju Das
Cc: Thierry Reding, linux-pwm, Geert Uytterhoeven, Chris Paterson,
Prabhakar Mahadev Lad, linux-renesas-soc
[-- Attachment #1: Type: text/plain, Size: 5054 bytes --]
On Fri, Nov 11, 2022 at 07:29:42PM +0000, Biju Das wrote:
> This patch add support for linking poeg group with gpt, so that
> gpt can control the output disable function.
Without knowing what a "gpt" and a "poeg" is, I don't understand the
purpose of this patch. Why do I want the gpt to be able to control the
output disable function and what is this?
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
> * Replaced id->poeg-id as per poeg bindings.
> This patch depend upon [1]
> [1] https://lore.kernel.org/linux-renesas-soc/20221111162325.471963-3-biju.das.jz@bp.renesas.com/T/#u
> ---
> drivers/pwm/pwm-rzg2l-gpt.c | 69 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
> index 3f9325e958b8..e16f976c3dcb 100644
> --- a/drivers/pwm/pwm-rzg2l-gpt.c
> +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> @@ -31,6 +31,7 @@
> #define RZG2L_GTCR 0x2c
> #define RZG2L_GTUDDTYC 0x30
> #define RZG2L_GTIOR 0x34
> +#define RZG2L_GTINTAD 0x38
> #define RZG2L_GTBER 0x40
> #define RZG2L_GTCNT 0x48
> #define RZG2L_GTCCRA 0x4c
> @@ -48,9 +49,15 @@
> #define RZG2L_UP_COUNTING (RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF)
>
> #define RZG2L_GTIOR_GTIOA GENMASK(4, 0)
> +#define RZG2L_GTIOR_OADF GENMASK(10, 9)
> #define RZG2L_GTIOR_GTIOB GENMASK(20, 16)
> +#define RZG2L_GTIOR_OBDF GENMASK(26, 25)
> #define RZG2L_GTIOR_OAE BIT(8)
> #define RZG2L_GTIOR_OBE BIT(24)
> +#define RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE BIT(9)
> +#define RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE BIT(25)
> +#define RZG2L_GTIOR_PIN_DISABLE_SETTING \
> + (RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE | RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE)
>
> #define RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE 0x07
> #define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE 0x1b
> @@ -64,12 +71,16 @@
> #define RZG2L_GTIOR_GTIOB_OUT_LO_END_TOGGLE_CMP_MATCH \
> (FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE) | RZG2L_GTIOR_OBE)
>
> +#define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24)
> +
> #define RZG2L_GTCCR(i) (0x4c + 4 * (i))
>
> #define RZG2L_MAX_HW_CHANNELS (8)
> #define RZG2L_CHANNELS_PER_IO (2)
> #define RZG2L_MAX_PWM_CHANNELS (RZG2L_MAX_HW_CHANNELS * RZG2L_CHANNELS_PER_IO)
>
> +#define RZG2L_MAX_POEG_GROUPS (4)
> +
> #define RZG2L_IS_IOB(a) ((a) & 0x1)
> #define RZG2L_GET_CH_INDEX(a) ((a) / 2)
>
> @@ -85,6 +96,7 @@ struct rzg2l_gpt_chip {
> u32 state_period[RZG2L_MAX_HW_CHANNELS];
> u32 user_count[RZG2L_MAX_HW_CHANNELS];
> u8 prescale[RZG2L_MAX_HW_CHANNELS];
> + DECLARE_BITMAP(poeg_gpt_link, RZG2L_MAX_POEG_GROUPS * RZG2L_MAX_HW_CHANNELS);
> };
>
> static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *chip)
> @@ -438,6 +450,62 @@ static void rzg2l_gpt_reset_assert_pm_disable(void *data)
> reset_control_assert(rzg2l_gpt->rstc);
> }
>
> +static void rzg2l_gpt_parse_properties(struct platform_device *pdev,
> + struct rzg2l_gpt_chip *rzg2l_gpt)
> +{
> + struct of_phandle_args of_args;
> + unsigned int i;
> + u32 poeg_grp;
> + int cells;
> + u32 offs;
> + int ret;
> +
> + cells = of_property_count_u32_elems(pdev->dev.of_node, "renesas,poegs");
> + if (cells == -EINVAL)
> + return;
> +
> + cells >>= 1;
> + for (i = 0; i < cells; i++) {
> + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
> + "renesas,poegs", 1, i,
> + &of_args);
> + if (ret) {
> + dev_err(&pdev->dev,
> + "Failed to parse 'renesas,poegs' property\n");
> + return;
> + }
> +
> + if (of_args.args[0] >= RZG2L_MAX_HW_CHANNELS) {
> + dev_err(&pdev->dev,
> + "Invalid channel %d > 7\n", of_args.args[0]);
> + return;
> + }
> +
> + if (!of_device_is_available(of_args.np)) {
> + /* It's fine to have a phandle to a non-enabled poeg. */
> + of_node_put(of_args.np);
> + continue;
> + }
> +
> + if (!of_property_read_u32(of_args.np, "renesas,poeg-id", &poeg_grp)) {
> + offs = RZG2L_GET_CH_OFFS(of_args.args[0]);
> +
> + set_bit(poeg_grp * RZG2L_MAX_HW_CHANNELS + of_args.args[0],
> + rzg2l_gpt->poeg_gpt_link);
You might want to check if poeg_grp * RZG2L_MAX_HW_CHANNELS +
of_args.args[0] is less than 32 (i.e. the length of the poeg_gpt_link
bitmap). Also ensure that poeg_grp is withing bounds.
> + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD,
> + RZG2L_GTINTAD_GRP_MASK,
> + poeg_grp << 24);
> +
> + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR,
> + RZG2L_GTIOR_OBDF | RZG2L_GTIOR_OADF,
> + RZG2L_GTIOR_PIN_DISABLE_SETTING);
> + }
> +
> + of_node_put(of_args.np);
> + }
> +}
> +
> static int rzg2l_gpt_probe(struct platform_device *pdev)
> {
> DECLARE_BITMAP(ch_en_bits, RZG2L_MAX_PWM_CHANNELS);
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [PATCH v2 3/3] pwm: rzg2l-gpt: Add support for linking with poeg
2022-11-28 13:01 ` Uwe Kleine-König
@ 2022-11-28 13:46 ` Biju Das
0 siblings, 0 replies; 10+ messages in thread
From: Biju Das @ 2022-11-28 13:46 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Thierry Reding, linux-pwm, Geert Uytterhoeven, Chris Paterson,
Prabhakar Mahadev Lad, linux-renesas-soc
Hi Uwe,
> Subject: Re: [PATCH v2 3/3] pwm: rzg2l-gpt: Add support for linking with
> poeg
>
> On Fri, Nov 11, 2022 at 07:29:42PM +0000, Biju Das wrote:
> > This patch add support for linking poeg group with gpt, so that gpt
> > can control the output disable function.
>
> Without knowing what a "gpt" and a "poeg" is, I don't understand the
> purpose of this patch. Why do I want the gpt to be able to control the
> output disable function and what is this?
gpt is General PWM Timer (GPT)
poeg is Port Output Enable for GPT (POEG)
gpt detects "dead time error and short-circuits between output pins"
and send Output disable request to poeg
poeg performs "Output-disable request from the GPT" and informs application.
There are 4 poeg groups shared to all the gpt hw channels.
gpt needs to configure a poeg group for the following poeg operations
1) Output-disable through Input level detection based on external pins
2) Output-disable request from the GPT
3) Output-disable through register setting.
For Output-disable request from the GPT, it needs to configure the type of protection
a) Dead Time Error Output Disable Request Enable
b) Same Time Output Level High Disable Request Enable
c) Same Time Output Level Low Disable Request Enable
The code flow for Output-disable request from the GPT is something like below
1) gpt detects a short circuit and send out-put disable request in the form
of interrupt to poeg.
2) poeg gets this disable request interrupt, Output is disabled, and it stops the Output-Disable state internally
to avoid IRQ storm and informs the application
3) Once Output-Disable request is raised, the interrupt processing in application software should identify and
solve the cause of request. After that, the status to be issued should be cleared followed by the release of
Output-Disable state.
>
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> > * Replaced id->poeg-id as per poeg bindings.
> > This patch depend upon [1]
> > [1]
> > https://lore.kernel.org/linux-renesas-soc/20221111162325.471963-3-biju
> > .das.jz@bp.renesas.com/T/#u
> > ---
> > drivers/pwm/pwm-rzg2l-gpt.c | 69
> > +++++++++++++++++++++++++++++++++++++
> > 1 file changed, 69 insertions(+)
> >
> > diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
> > index 3f9325e958b8..e16f976c3dcb 100644
> > --- a/drivers/pwm/pwm-rzg2l-gpt.c
> > +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> > @@ -31,6 +31,7 @@
> > #define RZG2L_GTCR 0x2c
> > #define RZG2L_GTUDDTYC 0x30
> > #define RZG2L_GTIOR 0x34
> > +#define RZG2L_GTINTAD 0x38
> > #define RZG2L_GTBER 0x40
> > #define RZG2L_GTCNT 0x48
> > #define RZG2L_GTCCRA 0x4c
> > @@ -48,9 +49,15 @@
> > #define RZG2L_UP_COUNTING (RZG2L_GTUDDTYC_UP | RZG2L_GTUDDTYC_UDF)
> >
> > #define RZG2L_GTIOR_GTIOA GENMASK(4, 0)
> > +#define RZG2L_GTIOR_OADF GENMASK(10, 9)
> > #define RZG2L_GTIOR_GTIOB GENMASK(20, 16)
> > +#define RZG2L_GTIOR_OBDF GENMASK(26, 25)
> > #define RZG2L_GTIOR_OAE BIT(8)
> > #define RZG2L_GTIOR_OBE BIT(24)
> > +#define RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE BIT(9)
> > +#define RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE BIT(25)
> > +#define RZG2L_GTIOR_PIN_DISABLE_SETTING \
> > + (RZG2L_GTIOR_OADF_HIGH_IMP_ON_OUT_DISABLE |
> > +RZG2L_GTIOR_OBDF_HIGH_IMP_ON_OUT_DISABLE)
> >
> > #define RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE 0x07
> > #define RZG2L_INIT_OUT_HI_OUT_HI_END_TOGGLE 0x1b
> > @@ -64,12 +71,16 @@
> > #define RZG2L_GTIOR_GTIOB_OUT_LO_END_TOGGLE_CMP_MATCH \
> > (FIELD_PREP(RZG2L_GTIOR_GTIOB, RZG2L_INIT_OUT_LO_OUT_LO_END_TOGGLE)
> > | RZG2L_GTIOR_OBE)
> >
> > +#define RZG2L_GTINTAD_GRP_MASK GENMASK(25, 24)
> > +
> > #define RZG2L_GTCCR(i) (0x4c + 4 * (i))
> >
> > #define RZG2L_MAX_HW_CHANNELS (8)
> > #define RZG2L_CHANNELS_PER_IO (2)
> > #define RZG2L_MAX_PWM_CHANNELS (RZG2L_MAX_HW_CHANNELS *
> RZG2L_CHANNELS_PER_IO)
> >
> > +#define RZG2L_MAX_POEG_GROUPS (4)
> > +
> > #define RZG2L_IS_IOB(a) ((a) & 0x1)
> > #define RZG2L_GET_CH_INDEX(a) ((a) / 2)
> >
> > @@ -85,6 +96,7 @@ struct rzg2l_gpt_chip {
> > u32 state_period[RZG2L_MAX_HW_CHANNELS];
> > u32 user_count[RZG2L_MAX_HW_CHANNELS];
> > u8 prescale[RZG2L_MAX_HW_CHANNELS];
> > + DECLARE_BITMAP(poeg_gpt_link, RZG2L_MAX_POEG_GROUPS *
> > +RZG2L_MAX_HW_CHANNELS);
> > };
> >
> > static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct
> > pwm_chip *chip) @@ -438,6 +450,62 @@ static void
> rzg2l_gpt_reset_assert_pm_disable(void *data)
> > reset_control_assert(rzg2l_gpt->rstc);
> > }
> >
> > +static void rzg2l_gpt_parse_properties(struct platform_device *pdev,
> > + struct rzg2l_gpt_chip *rzg2l_gpt) {
> > + struct of_phandle_args of_args;
> > + unsigned int i;
> > + u32 poeg_grp;
> > + int cells;
> > + u32 offs;
> > + int ret;
> > +
> > + cells = of_property_count_u32_elems(pdev->dev.of_node,
> "renesas,poegs");
> > + if (cells == -EINVAL)
> > + return;
> > +
> > + cells >>= 1;
> > + for (i = 0; i < cells; i++) {
> > + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
> > + "renesas,poegs", 1, i,
> > + &of_args);
> > + if (ret) {
> > + dev_err(&pdev->dev,
> > + "Failed to parse 'renesas,poegs' property\n");
> > + return;
> > + }
> > +
> > + if (of_args.args[0] >= RZG2L_MAX_HW_CHANNELS) {
> > + dev_err(&pdev->dev,
> > + "Invalid channel %d > 7\n", of_args.args[0]);
> > + return;
> > + }
> > +
> > + if (!of_device_is_available(of_args.np)) {
> > + /* It's fine to have a phandle to a non-enabled poeg.
> */
> > + of_node_put(of_args.np);
> > + continue;
> > + }
> > +
> > + if (!of_property_read_u32(of_args.np, "renesas,poeg-id",
> &poeg_grp)) {
> > + offs = RZG2L_GET_CH_OFFS(of_args.args[0]);
> > +
> > + set_bit(poeg_grp * RZG2L_MAX_HW_CHANNELS +
> of_args.args[0],
> > + rzg2l_gpt->poeg_gpt_link);
>
> You might want to check if poeg_grp * RZG2L_MAX_HW_CHANNELS +
> of_args.args[0] is less than 32 (i.e. the length of the poeg_gpt_link
> bitmap). Also ensure that poeg_grp is withing bounds.
OK will handle this in next version.
Cheers,
Biju
>
> > + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTINTAD,
> > + RZG2L_GTINTAD_GRP_MASK,
> > + poeg_grp << 24);
> > +
> > + rzg2l_gpt_modify(rzg2l_gpt, offs + RZG2L_GTIOR,
> > + RZG2L_GTIOR_OBDF | RZG2L_GTIOR_OADF,
> > + RZG2L_GTIOR_PIN_DISABLE_SETTING);
> > + }
> > +
> > + of_node_put(of_args.np);
> > + }
> > +}
> > +
> > static int rzg2l_gpt_probe(struct platform_device *pdev) {
> > DECLARE_BITMAP(ch_en_bits, RZG2L_MAX_PWM_CHANNELS);
>
> |
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-11-28 13:46 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-11 19:29 [PATCH v2 0/3] Add support for linking gpt with poeg Biju Das
2022-11-11 19:29 ` [DO NOT APPLY PATCH 1/3] dt-bindings: pwm: Add RZ/G2L GPT binding Biju Das
2022-11-11 19:29 ` [PATCH v2 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property Biju Das
2022-11-12 0:10 ` Rob Herring
2022-11-12 9:33 ` Biju Das
2022-11-15 1:46 ` Rob Herring
2022-11-15 7:02 ` Biju Das
2022-11-11 19:29 ` [PATCH v2 3/3] pwm: rzg2l-gpt: Add support for linking with poeg Biju Das
2022-11-28 13:01 ` Uwe Kleine-König
2022-11-28 13:46 ` Biju Das
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