* [PATCH v2 0/4] clk: renesas: cpg-mssr: add support for V3U
@ 2020-09-09 13:13 Yoshihiro Shimoda
2020-09-09 13:13 ` [PATCH v2 1/4] dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions Yoshihiro Shimoda
` (3 more replies)
0 siblings, 4 replies; 13+ messages in thread
From: Yoshihiro Shimoda @ 2020-09-09 13:13 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
This patch series is like incremental patches from the following
series.
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=344457
And, this patch series fix patch 7/14 and 12/14 of
the previous patch series. In other words, I don't include
the patch 6/14 because it already got Reviewed-by [1].
https://patchwork.kernel.org/patch/11760285/
Changes from v1:
- Fix subject in the patch 1.
- Remove unused/unexist definitions in the patch 1.
- Fix the SPDX in the patch 1.
- Use enum instead of bool flag, so I made additional new patches as
patch 2 and 3.
- Remove z clocks handling in the patch 4.
- Use share PLL[23][01] clock types in the patch 4.
- Fix alignment of r8a779a0_core_clks in the patch 4.
- Use rcar-gen3-cpg.h in the patch 4.
- Remove r8a779a0_crit_mod_clks in the patch 4.
- Fix .num_hw_mod_clks in the patch 4.
Yoshihiro Shimoda (4):
dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean
flag
clk: renesas: cpg-mssr: add register pointers into struct
cpg_mssr_priv
clk: renesas: cpg-mssr: Add support for R-Car V3U
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r7s9210-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 281 ++++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 100 +++++----
drivers/clk/renesas/renesas-cpg-mssr.h | 9 +-
include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 55 +++++
7 files changed, 413 insertions(+), 40 deletions(-)
create mode 100644 drivers/clk/renesas/r8a779a0-cpg-mssr.c
create mode 100644 include/dt-bindings/clock/r8a779a0-cpg-mssr.h
--
2.7.4
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v2 1/4] dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
2020-09-09 13:13 [PATCH v2 0/4] clk: renesas: cpg-mssr: add support for V3U Yoshihiro Shimoda
@ 2020-09-09 13:13 ` Yoshihiro Shimoda
2020-09-10 12:56 ` Geert Uytterhoeven
2020-09-09 13:13 ` [PATCH v2 2/4] clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag Yoshihiro Shimoda
` (2 subsequent siblings)
3 siblings, 1 reply; 13+ messages in thread
From: Yoshihiro Shimoda @ 2020-09-09 13:13 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
V3U (R8A779A0) SoC.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 55 +++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 include/dt-bindings/clock/r8a779a0-cpg-mssr.h
diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
new file mode 100644
index 0000000..f1d737c
--- /dev/null
+++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a779A0 CPG Core Clocks */
+#define R8A779A0_CLK_Z0 0
+#define R8A779A0_CLK_ZX 1
+#define R8A779A0_CLK_Z1 2
+#define R8A779A0_CLK_ZR 3
+#define R8A779A0_CLK_ZS 4
+#define R8A779A0_CLK_ZT 5
+#define R8A779A0_CLK_ZTR 6
+#define R8A779A0_CLK_S1D1 7
+#define R8A779A0_CLK_S1D2 8
+#define R8A779A0_CLK_S1D4 9
+#define R8A779A0_CLK_S1D8 10
+#define R8A779A0_CLK_S1D12 11
+#define R8A779A0_CLK_S3D1 12
+#define R8A779A0_CLK_S3D2 13
+#define R8A779A0_CLK_S3D4 14
+#define R8A779A0_CLK_LB 15
+#define R8A779A0_CLK_CP 16
+#define R8A779A0_CLK_CL 17
+#define R8A779A0_CLK_CL16MCK 18
+#define R8A779A0_CLK_ZB30 19
+#define R8A779A0_CLK_ZB30D2 20
+#define R8A779A0_CLK_ZB30D4 21
+#define R8A779A0_CLK_ZB31 22
+#define R8A779A0_CLK_ZB31D2 23
+#define R8A779A0_CLK_ZB31D4 24
+#define R8A779A0_CLK_SD0H 25
+#define R8A779A0_CLK_SD0 26
+#define R8A779A0_CLK_RPC 27
+#define R8A779A0_CLK_RPCD2 28
+#define R8A779A0_CLK_MSO 29
+#define R8A779A0_CLK_CANFD 30
+#define R8A779A0_CLK_CSI0 31
+#define R8A779A0_CLK_FRAY 32
+#define R8A779A0_CLK_DSI 33
+#define R8A779A0_CLK_VIP 34
+#define R8A779A0_CLK_ADGH 35
+#define R8A779A0_CLK_CNNDSP 36
+#define R8A779A0_CLK_ICU 37
+#define R8A779A0_CLK_ICUD2 38
+#define R8A779A0_CLK_VCBUS 39
+#define R8A779A0_CLK_CBFUSA 40
+#define R8A779A0_CLK_R 41
+#define R8A779A0_CLK_OSC 42
+
+#endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 2/4] clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
2020-09-09 13:13 [PATCH v2 0/4] clk: renesas: cpg-mssr: add support for V3U Yoshihiro Shimoda
2020-09-09 13:13 ` [PATCH v2 1/4] dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions Yoshihiro Shimoda
@ 2020-09-09 13:13 ` Yoshihiro Shimoda
2020-09-10 13:06 ` Geert Uytterhoeven
2020-09-09 13:13 ` [PATCH v2 3/4] clk: renesas: cpg-mssr: add register pointers into struct cpg_mssr_priv Yoshihiro Shimoda
2020-09-09 13:13 ` [PATCH v2 4/4] clk: renesas: cpg-mssr: Add support for R-Car V3U Yoshihiro Shimoda
3 siblings, 1 reply; 13+ messages in thread
From: Yoshihiro Shimoda @ 2020-09-09 13:13 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Geert suggested defining multiple registers layout variants using
an enum [1] to support further devices like R-Car V3U. So, use enum
clk_reg_layout instead of a boolean .stbyctrl flag. No behavior change.
[1]
https://lore.kernel.org/linux-renesas-soc/CAMuHMdVAgN69p9FFnQdO4iHk2CHkeNaVui2Q-FOY6_BFVjQ-Nw@mail.gmail.com/
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 2 +-
drivers/clk/renesas/renesas-cpg-mssr.c | 27 ++++++++++++++-------------
drivers/clk/renesas/renesas-cpg-mssr.h | 7 ++++++-
3 files changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 443bff0..a85227c 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -214,7 +214,7 @@ const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
.cpg_clk_register = rza2_cpg_clk_register,
/* RZ/A2 has Standby Control Registers */
- .stbyctrl = true,
+ .reg_layout = CLK_REG_LAYOUT_RZ_A,
};
static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 5a306d2..1b289c8 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -111,12 +111,12 @@ static const u16 srcr[] = {
* @rcdev: Optional reset controller entity
* @dev: CPG/MSSR device
* @base: CPG/MSSR register block base address
+ * @reg_layout: CPG/MSSR register layout
* @rmw_lock: protects RMW register accesses
* @np: Device node in DT for this CPG/MSSR module
* @num_core_clks: Number of Core Clocks in clks[]
* @num_mod_clks: Number of Module Clocks in clks[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
- * @stbyctrl: This device has Standby Control Registers
* @notifiers: Notifier chain to save/restore clock state for system resume
* @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
* @smstpcr_saved[].val: Saved values of SMSTPCR[]
@@ -128,13 +128,13 @@ struct cpg_mssr_priv {
#endif
struct device *dev;
void __iomem *base;
+ enum clk_reg_layout reg_layout;
spinlock_t rmw_lock;
struct device_node *np;
unsigned int num_core_clks;
unsigned int num_mod_clks;
unsigned int last_dt_core_clk;
- bool stbyctrl;
struct raw_notifier_head notifiers;
struct {
@@ -177,7 +177,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
enable ? "ON" : "OFF");
spin_lock_irqsave(&priv->rmw_lock, flags);
- if (priv->stbyctrl) {
+ if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
value = readb(priv->base + STBCR(reg));
if (enable)
value &= ~bitmask;
@@ -199,7 +199,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
spin_unlock_irqrestore(&priv->rmw_lock, flags);
- if (!enable || priv->stbyctrl)
+ if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
return 0;
for (i = 1000; i > 0; --i) {
@@ -233,7 +233,7 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
struct cpg_mssr_priv *priv = clock->priv;
u32 value;
- if (priv->stbyctrl)
+ if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
value = readb(priv->base + STBCR(clock->index / 32));
else
value = readl(priv->base + MSTPSR(clock->index / 32));
@@ -272,7 +272,7 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
case CPG_MOD:
type = "module";
- if (priv->stbyctrl) {
+ if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
idx = MOD_CLK_PACK_10(clkidx);
range_check = 7 - (clkidx % 10);
} else {
@@ -825,7 +825,8 @@ static int cpg_mssr_suspend_noirq(struct device *dev)
/* Save module registers with bits under our control */
for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
if (priv->smstpcr_saved[reg].mask)
- priv->smstpcr_saved[reg].val = priv->stbyctrl ?
+ priv->smstpcr_saved[reg].val =
+ priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
readb(priv->base + STBCR(reg)) :
readl(priv->base + SMSTPCR(reg));
}
@@ -855,7 +856,7 @@ static int cpg_mssr_resume_noirq(struct device *dev)
if (!mask)
continue;
- if (priv->stbyctrl)
+ if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
oldval = readb(priv->base + STBCR(reg));
else
oldval = readl(priv->base + SMSTPCR(reg));
@@ -864,7 +865,7 @@ static int cpg_mssr_resume_noirq(struct device *dev)
if (newval == oldval)
continue;
- if (priv->stbyctrl) {
+ if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
writeb(newval, priv->base + STBCR(reg));
/* dummy read to ensure write has completed */
readb(priv->base + STBCR(reg));
@@ -887,8 +888,8 @@ static int cpg_mssr_resume_noirq(struct device *dev)
if (!i)
dev_warn(dev, "Failed to enable %s%u[0x%x]\n",
- priv->stbyctrl ? "STB" : "SMSTP", reg,
- oldval & mask);
+ priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
+ "STB" : "SMSTP", reg, oldval & mask);
}
return 0;
@@ -937,7 +938,7 @@ static int __init cpg_mssr_common_init(struct device *dev,
priv->num_mod_clks = info->num_hw_mod_clks;
priv->last_dt_core_clk = info->last_dt_core_clk;
RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
- priv->stbyctrl = info->stbyctrl;
+ priv->reg_layout = info->reg_layout;
for (i = 0; i < nclks; i++)
priv->clks[i] = ERR_PTR(-ENOENT);
@@ -1015,7 +1016,7 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
return error;
/* Reset Controller not supported for Standby Control SoCs */
- if (info->stbyctrl)
+ if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
return 0;
error = cpg_mssr_reset_controller_register(priv);
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 1cc5694..5b65c78 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -85,6 +85,11 @@ struct mssr_mod_clk {
struct device_node;
+enum clk_reg_layout {
+ CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
+ CLK_REG_LAYOUT_RZ_A,
+};
+
/**
* SoC-specific CPG/MSSR Description
*
@@ -130,7 +135,7 @@ struct cpg_mssr_info {
unsigned int num_core_clks;
unsigned int last_dt_core_clk;
unsigned int num_total_core_clks;
- bool stbyctrl;
+ enum clk_reg_layout reg_layout;
/* Module Clocks */
const struct mssr_mod_clk *mod_clks;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 3/4] clk: renesas: cpg-mssr: add register pointers into struct cpg_mssr_priv
2020-09-09 13:13 [PATCH v2 0/4] clk: renesas: cpg-mssr: add support for V3U Yoshihiro Shimoda
2020-09-09 13:13 ` [PATCH v2 1/4] dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions Yoshihiro Shimoda
2020-09-09 13:13 ` [PATCH v2 2/4] clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag Yoshihiro Shimoda
@ 2020-09-09 13:13 ` Yoshihiro Shimoda
2020-09-10 13:11 ` Geert Uytterhoeven
2020-09-09 13:13 ` [PATCH v2 4/4] clk: renesas: cpg-mssr: Add support for R-Car V3U Yoshihiro Shimoda
3 siblings, 1 reply; 13+ messages in thread
From: Yoshihiro Shimoda @ 2020-09-09 13:13 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
To support other register layout in the future, add register pointers
of control_regs and status_regs into struct cpg_mssr_priv. After that,
we can remove unused macros like MSTPSR(). No behavior changes.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/clk/renesas/renesas-cpg-mssr.c | 56 ++++++++++++++++++----------------
1 file changed, 30 insertions(+), 26 deletions(-)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 1b289c8..b3a84cd 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -57,9 +57,6 @@ static const u16 mstpsr[] = {
0x9A0, 0x9A4, 0x9A8, 0x9AC,
};
-#define MSTPSR(i) mstpsr[i]
-
-
/*
* System Module Stop Control Register offsets
*/
@@ -69,8 +66,6 @@ static const u16 smstpcr[] = {
0x990, 0x994, 0x998, 0x99C,
};
-#define SMSTPCR(i) smstpcr[i]
-
/*
* Standby Control Register offsets (RZ/A)
* Base address is FRQCR register
@@ -81,8 +76,6 @@ static const u16 stbcr[] = {
0x424, 0x428, 0x42C,
};
-#define STBCR(i) stbcr[i]
-
/*
* Software Reset Register offsets
*/
@@ -137,6 +130,8 @@ struct cpg_mssr_priv {
unsigned int last_dt_core_clk;
struct raw_notifier_head notifiers;
+ const u16 *status_regs;
+ const u16 *control_regs;
struct {
u32 mask;
u32 val;
@@ -178,23 +173,23 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
spin_lock_irqsave(&priv->rmw_lock, flags);
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
- value = readb(priv->base + STBCR(reg));
+ value = readb(priv->base + priv->control_regs[reg]);
if (enable)
value &= ~bitmask;
else
value |= bitmask;
- writeb(value, priv->base + STBCR(reg));
+ writeb(value, priv->base + priv->control_regs[reg]);
/* dummy read to ensure write has completed */
- readb(priv->base + STBCR(reg));
- barrier_data(priv->base + STBCR(reg));
+ readb(priv->base + priv->control_regs[reg]);
+ barrier_data(priv->base + priv->control_regs[reg]);
} else {
- value = readl(priv->base + SMSTPCR(reg));
+ value = readl(priv->base + priv->control_regs[reg]);
if (enable)
value &= ~bitmask;
else
value |= bitmask;
- writel(value, priv->base + SMSTPCR(reg));
+ writel(value, priv->base + priv->control_regs[reg]);
}
spin_unlock_irqrestore(&priv->rmw_lock, flags);
@@ -203,14 +198,14 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
return 0;
for (i = 1000; i > 0; --i) {
- if (!(readl(priv->base + MSTPSR(reg)) & bitmask))
+ if (!(readl(priv->base + priv->status_regs[reg]) & bitmask))
break;
cpu_relax();
}
if (!i) {
dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
- priv->base + SMSTPCR(reg), bit);
+ priv->base + priv->control_regs[reg], bit);
return -ETIMEDOUT;
}
@@ -234,9 +229,9 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
u32 value;
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
- value = readb(priv->base + STBCR(clock->index / 32));
+ value = readb(priv->base + priv->control_regs[clock->index / 32]);
else
- value = readl(priv->base + MSTPSR(clock->index / 32));
+ value = readl(priv->base + priv->status_regs[clock->index / 32]);
return !(value & BIT(clock->index % 32));
}
@@ -827,8 +822,8 @@ static int cpg_mssr_suspend_noirq(struct device *dev)
if (priv->smstpcr_saved[reg].mask)
priv->smstpcr_saved[reg].val =
priv->reg_layout == CLK_REG_LAYOUT_RZ_A ?
- readb(priv->base + STBCR(reg)) :
- readl(priv->base + SMSTPCR(reg));
+ readb(priv->base + priv->control_regs[reg]) :
+ readl(priv->base + priv->control_regs[reg]);
}
/* Save core clocks */
@@ -857,22 +852,22 @@ static int cpg_mssr_resume_noirq(struct device *dev)
continue;
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
- oldval = readb(priv->base + STBCR(reg));
+ oldval = readb(priv->base + priv->control_regs[reg]);
else
- oldval = readl(priv->base + SMSTPCR(reg));
+ oldval = readl(priv->base + priv->control_regs[reg]);
newval = oldval & ~mask;
newval |= priv->smstpcr_saved[reg].val & mask;
if (newval == oldval)
continue;
if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
- writeb(newval, priv->base + STBCR(reg));
+ writeb(newval, priv->base + priv->control_regs[reg]);
/* dummy read to ensure write has completed */
- readb(priv->base + STBCR(reg));
- barrier_data(priv->base + STBCR(reg));
+ readb(priv->base + priv->control_regs[reg]);
+ barrier_data(priv->base + priv->control_regs[reg]);
continue;
} else
- writel(newval, priv->base + SMSTPCR(reg));
+ writel(newval, priv->base + priv->control_regs[reg]);
/* Wait until enabled clocks are really enabled */
mask &= ~priv->smstpcr_saved[reg].val;
@@ -880,7 +875,7 @@ static int cpg_mssr_resume_noirq(struct device *dev)
continue;
for (i = 1000; i > 0; --i) {
- oldval = readl(priv->base + MSTPSR(reg));
+ oldval = readl(priv->base + priv->status_regs[reg]);
if (!(oldval & mask))
break;
cpu_relax();
@@ -939,6 +934,15 @@ static int __init cpg_mssr_common_init(struct device *dev,
priv->last_dt_core_clk = info->last_dt_core_clk;
RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
priv->reg_layout = info->reg_layout;
+ if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
+ priv->status_regs = mstpsr;
+ priv->control_regs = smstpcr;
+ } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
+ priv->control_regs = stbcr;
+ } else {
+ error = -EINVAL;
+ goto out_err;
+ }
for (i = 0; i < nclks; i++)
priv->clks[i] = ERR_PTR(-ENOENT);
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH v2 4/4] clk: renesas: cpg-mssr: Add support for R-Car V3U
2020-09-09 13:13 [PATCH v2 0/4] clk: renesas: cpg-mssr: add support for V3U Yoshihiro Shimoda
` (2 preceding siblings ...)
2020-09-09 13:13 ` [PATCH v2 3/4] clk: renesas: cpg-mssr: add register pointers into struct cpg_mssr_priv Yoshihiro Shimoda
@ 2020-09-09 13:13 ` Yoshihiro Shimoda
2020-09-10 13:19 ` Geert Uytterhoeven
3 siblings, 1 reply; 13+ messages in thread
From: Yoshihiro Shimoda @ 2020-09-09 13:13 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Initial support for R-Car V3U (r8a779a0), including core, module
clocks and register access, because register specification differs
from R-Car Gen2/3.
Inspired by patches in the BSP by LUU HOAI.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/clk/renesas/Kconfig | 5 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 281 ++++++++++++++++++++++++++++++++
drivers/clk/renesas/renesas-cpg-mssr.c | 21 ++-
drivers/clk/renesas/renesas-cpg-mssr.h | 2 +
5 files changed, 309 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/renesas/r8a779a0-cpg-mssr.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 28e8730..37d59c2 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -30,6 +30,7 @@ config CLK_RENESAS
select CLK_R8A77980 if ARCH_R8A77980
select CLK_R8A77990 if ARCH_R8A77990
select CLK_R8A77995 if ARCH_R8A77995
+ select CLK_R8A779A0 if ARCH_R8A779A0
select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_SH73A0 if ARCH_SH73A0
@@ -145,6 +146,10 @@ config CLK_R8A77995
bool "R-Car D3 clock support" if COMPILE_TEST
select CLK_RCAR_GEN3_CPG
+config CLK_R8A779A0
+ bool "R-Car V3U clock support" if COMPILE_TEST
+ select CLK_RENESAS_CPG_MSSR
+
config CLK_R9A06G032
bool "Renesas R9A06G032 clock driver"
help
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index c7c03ab..c803912 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77990) += r8a77990-cpg-mssr.o
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
new file mode 100644
index 0000000..061f5a4
--- /dev/null
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a779a0 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ * Based on r8a7795-cpg-mssr.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include <linux/bug.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/soc/renesas/rcar-rst.h>
+
+#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum rcar_r8a779a0_clk_types {
+ CLK_TYPE_R8A779A0_MAIN = CLK_TYPE_CUSTOM,
+ CLK_TYPE_R8A779A0_PLL1,
+ CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */
+ CLK_TYPE_R8A779A0_PLL5,
+ CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */
+ CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */
+};
+
+struct rcar_r8a779a0_cpg_pll_config {
+ u8 extal_div;
+ u8 pll1_mult;
+ u8 pll1_div;
+ u8 pll5_mult;
+ u8 pll5_div;
+ u8 osc_prediv;
+};
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL1,
+ CLK_PLL20,
+ CLK_PLL21,
+ CLK_PLL30,
+ CLK_PLL31,
+ CLK_PLL5,
+ CLK_PLL1_DIV2,
+ CLK_PLL20_DIV2,
+ CLK_PLL21_DIV2,
+ CLK_PLL30_DIV2,
+ CLK_PLL31_DIV2,
+ CLK_PLL5_DIV2,
+ CLK_PLL5_DIV4,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RPCSRC,
+ CLK_OCO,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+#define DEF_PLL(_name, _id, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \
+ .offset = _offset)
+
+#define CPG_PLL20CR 0x0834
+#define CPG_PLL21CR 0x0838
+#define CPG_PLL30CR 0x083c
+#define CPG_PLL31CR 0x0840
+
+static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
+ DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
+ DEF_PLL(".pll20", CLK_PLL20, CPG_PLL20CR),
+ DEF_PLL(".pll21", CLK_PLL21, CPG_PLL21CR),
+ DEF_PLL(".pll30", CLK_PLL30, CPG_PLL30CR),
+ DEF_PLL(".pll31", CLK_PLL31, CPG_PLL31CR),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll20_div2", CLK_PLL20_DIV2, CLK_PLL20, 2, 1),
+ DEF_FIXED(".pll21_div2", CLK_PLL21_DIV2, CLK_PLL21, 2, 1),
+ DEF_FIXED(".pll30_div2", CLK_PLL30_DIV2, CLK_PLL30, 2, 1),
+ DEF_FIXED(".pll31_div2", CLK_PLL31_DIV2, CLK_PLL31, 2, 1),
+ DEF_FIXED(".pll5_div2", CLK_PLL5_DIV2, CLK_PLL5, 2, 1),
+ DEF_FIXED(".pll5_div4", CLK_PLL5_DIV4, CLK_PLL5_DIV2, 2, 1),
+ DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1),
+ DEF_RATE(".oco", CLK_OCO, 32768),
+
+ /* Core Clock Outputs */
+ DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1),
+ DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1),
+ DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1),
+ DEF_FIXED("s1d4", R8A779A0_CLK_S1D4, CLK_S1, 4, 1),
+ DEF_FIXED("s1d8", R8A779A0_CLK_S1D8, CLK_S1, 8, 1),
+ DEF_FIXED("s1d12", R8A779A0_CLK_S1D12, CLK_S1, 12, 1),
+ DEF_FIXED("s3d1", R8A779A0_CLK_S3D1, CLK_S3, 1, 1),
+ DEF_FIXED("s3d2", R8A779A0_CLK_S3D2, CLK_S3, 2, 1),
+ DEF_FIXED("s3d4", R8A779A0_CLK_S3D4, CLK_S3, 4, 1),
+ DEF_FIXED("zs", R8A779A0_CLK_ZS, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1),
+ DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1),
+ DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1),
+ DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1),
+ DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1),
+ DEF_FIXED("icu", R8A779A0_CLK_ICU, CLK_PLL5_DIV4, 2, 1),
+ DEF_FIXED("icud2", R8A779A0_CLK_ICUD2, CLK_PLL5_DIV4, 4, 1),
+ DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1),
+ DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_MAIN, 2, 1),
+
+ DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
+ DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
+ DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
+
+ DEF_GEN3_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8),
+ DEF_GEN3_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
+};
+
+static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
+ DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8),
+ DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8),
+ DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8),
+ DEF_MOD("scif4", 705, R8A779A0_CLK_S1D8),
+};
+
+static spinlock_t cpg_lock;
+
+static const struct rcar_r8a779a0_cpg_pll_config *cpg_pll_config __initdata;
+static unsigned int cpg_clk_extalr __initdata;
+static u32 cpg_mode __initdata;
+
+struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev,
+ const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
+ struct clk **clks, void __iomem *base,
+ struct raw_notifier_head *notifiers)
+{
+ const struct clk *parent;
+ unsigned int mult = 1;
+ unsigned int div = 1;
+ u32 value;
+
+ parent = clks[core->parent & 0xffff]; /* some types use high bits */
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+
+ switch (core->type) {
+ case CLK_TYPE_R8A779A0_MAIN:
+ div = cpg_pll_config->extal_div;
+ break;
+
+ case CLK_TYPE_R8A779A0_PLL1:
+ mult = cpg_pll_config->pll1_mult;
+ div = cpg_pll_config->pll1_div;
+ break;
+
+ case CLK_TYPE_R8A779A0_PLL2X_3X:
+ value = readl(base + core->offset);
+ mult = (((value >> 24) & 0x7f) + 1) * 2;
+ break;
+
+ case CLK_TYPE_R8A779A0_PLL5:
+ mult = cpg_pll_config->pll5_mult;
+ div = cpg_pll_config->pll5_div;
+ break;
+
+ case CLK_TYPE_R8A779A0_MDSEL:
+ /*
+ * Clock selectable between two parents and two fixed dividers
+ * using a mode pin
+ */
+ if (cpg_mode & BIT(core->offset)) {
+ div = core->div & 0xffff;
+ } else {
+ parent = clks[core->parent >> 16];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+ div = core->div >> 16;
+ }
+ mult = 1;
+ break;
+
+ case CLK_TYPE_R8A779A0_OSC:
+ /*
+ * Clock combining OSC EXTAL predivider and a fixed divider
+ */
+ div = cpg_pll_config->osc_prediv * core->div;
+ break;
+
+ default:
+ return ERR_PTR(-EINVAL);
+ }
+
+ return clk_register_fixed_factor(NULL, core->name,
+ __clk_get_name(parent), 0, mult, div);
+}
+
+/*
+ * CPG Clock Data
+ */
+/*
+ * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 PLL6 OSC
+ * 14 13 (MHz) 21 31
+ * --------------------------------------------------------
+ * 0 0 16.66 x 1 x128 x216 x128 x144 x192 x128 /16
+ * 0 1 20 x 1 x106 x180 x106 x120 x160 x106 /19
+ * 1 0 Prohibited setting
+ * 1 1 33.33 / 2 x128 x216 x128 x144 x192 x128 /32
+ */
+#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
+ (((md) & BIT(13)) >> 13))
+
+static const struct rcar_r8a779a0_cpg_pll_config cpg_pll_configs[4] = {
+ /* EXTAL div PLL1 mult/div PLL5 mult/div OSC prediv */
+ { 1, 128, 1, 192, 1, 16, },
+ { 1, 106, 1, 160, 1, 19, },
+ { 0, 0, 0, 0, 0, 0, },
+ { 2, 128, 1, 192, 1, 32, },
+};
+
+static int __init r8a779a0_cpg_mssr_init(struct device *dev)
+{
+ int error;
+
+ error = rcar_rst_read_mode_pins(&cpg_mode);
+ if (error)
+ return error;
+
+ cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+ cpg_clk_extalr = CLK_EXTALR;
+ spin_lock_init(&cpg_lock);
+
+ return 0;
+}
+
+const struct cpg_mssr_info r8a779a0_cpg_mssr_info __initconst = {
+ /* Core Clocks */
+ .core_clks = r8a779a0_core_clks,
+ .num_core_clks = ARRAY_SIZE(r8a779a0_core_clks),
+ .last_dt_core_clk = LAST_DT_CORE_CLK,
+ .num_total_core_clks = MOD_CLK_BASE,
+
+ /* Module Clocks */
+ .mod_clks = r8a779a0_mod_clks,
+ .num_mod_clks = ARRAY_SIZE(r8a779a0_mod_clks),
+ .num_hw_mod_clks = 15 * 32,
+
+ /* Callbacks */
+ .init = r8a779a0_cpg_mssr_init,
+ .cpg_clk_register = rcar_r8a779a0_cpg_clk_register,
+
+ .reg_layout = CLK_REG_LAYOUT_RCAR_V3U,
+};
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index b3a84cd..a26ed2e 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -57,6 +57,11 @@ static const u16 mstpsr[] = {
0x9A0, 0x9A4, 0x9A8, 0x9AC,
};
+static const u16 mstpsr_for_v3u[] = {
+ 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
+ 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
+};
+
/*
* System Module Stop Control Register offsets
*/
@@ -66,6 +71,11 @@ static const u16 smstpcr[] = {
0x990, 0x994, 0x998, 0x99C,
};
+static const u16 mstpcr_for_v3u[] = {
+ 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
+ 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
+};
+
/*
* Standby Control Register offsets (RZ/A)
* Base address is FRQCR register
@@ -135,7 +145,7 @@ struct cpg_mssr_priv {
struct {
u32 mask;
u32 val;
- } smstpcr_saved[ARRAY_SIZE(smstpcr)];
+ } smstpcr_saved[ARRAY_SIZE(mstpsr_for_v3u)];
struct clk *clks[];
};
@@ -799,6 +809,12 @@ static const struct of_device_id cpg_mssr_match[] = {
.data = &r8a77995_cpg_mssr_info,
},
#endif
+#ifdef CONFIG_CLK_R8A779A0
+ {
+ .compatible = "renesas,r8a779a0-cpg-mssr",
+ .data = &r8a779a0_cpg_mssr_info,
+ },
+#endif
{ /* sentinel */ }
};
@@ -939,6 +955,9 @@ static int __init cpg_mssr_common_init(struct device *dev,
priv->control_regs = smstpcr;
} else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
priv->control_regs = stbcr;
+ } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
+ priv->status_regs = mstpsr_for_v3u;
+ priv->control_regs = mstpcr_for_v3u;
} else {
error = -EINVAL;
goto out_err;
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 5b65c78..ff7a21f 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -88,6 +88,7 @@ struct device_node;
enum clk_reg_layout {
CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
CLK_REG_LAYOUT_RZ_A,
+ CLK_REG_LAYOUT_RCAR_V3U,
};
/**
@@ -179,6 +180,7 @@ extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
+extern const struct cpg_mssr_info r8a779a0_cpg_mssr_info;
void __init cpg_mssr_early_init(struct device_node *np,
const struct cpg_mssr_info *info);
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions
2020-09-09 13:13 ` [PATCH v2 1/4] dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions Yoshihiro Shimoda
@ 2020-09-10 12:56 ` Geert Uytterhoeven
0 siblings, 0 replies; 13+ messages in thread
From: Geert Uytterhoeven @ 2020-09-10 12:56 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: Magnus Damm, Linux-Renesas
Hi Shimoda-san,
On Wed, Sep 9, 2020 at 3:13 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car
> V3U (R8A779A0) SoC.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for the update!
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v5.10.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/4] clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
2020-09-09 13:13 ` [PATCH v2 2/4] clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag Yoshihiro Shimoda
@ 2020-09-10 13:06 ` Geert Uytterhoeven
2020-09-10 13:06 ` Geert Uytterhoeven
0 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2020-09-10 13:06 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: Magnus Damm, Linux-Renesas
Hi Shimoda-san,
On Wed, Sep 9, 2020 at 3:13 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Geert suggested defining multiple registers layout variants using
> an enum [1] to support further devices like R-Car V3U. So, use enum
> clk_reg_layout instead of a boolean .stbyctrl flag. No behavior change.
>
> [1]
> https://lore.kernel.org/linux-renesas-soc/CAMuHMdVAgN69p9FFnQdO4iHk2CHkeNaVui2Q-FOY6_BFVjQ-Nw@mail.gmail.com/
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> --- a/drivers/clk/renesas/renesas-cpg-mssr.h
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.h
> @@ -130,7 +135,7 @@ struct cpg_mssr_info {
> unsigned int num_core_clks;
> unsigned int last_dt_core_clk;
> unsigned int num_total_core_clks;
> - bool stbyctrl;
> + enum clk_reg_layout reg_layout;
Seems like you forgot to update the struct's kerneldoc for this rename?
>
> /* Module Clocks */
> const struct mssr_mod_clk *mod_clks;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 2/4] clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
2020-09-10 13:06 ` Geert Uytterhoeven
@ 2020-09-10 13:06 ` Geert Uytterhoeven
2020-09-11 0:35 ` Yoshihiro Shimoda
0 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2020-09-10 13:06 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: Magnus Damm, Linux-Renesas
On Thu, Sep 10, 2020 at 3:06 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Wed, Sep 9, 2020 at 3:13 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Geert suggested defining multiple registers layout variants using
> > an enum [1] to support further devices like R-Car V3U. So, use enum
> > clk_reg_layout instead of a boolean .stbyctrl flag. No behavior change.
> >
> > [1]
> > https://lore.kernel.org/linux-renesas-soc/CAMuHMdVAgN69p9FFnQdO4iHk2CHkeNaVui2Q-FOY6_BFVjQ-Nw@mail.gmail.com/
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> > --- a/drivers/clk/renesas/renesas-cpg-mssr.h
> > +++ b/drivers/clk/renesas/renesas-cpg-mssr.h
>
> > @@ -130,7 +135,7 @@ struct cpg_mssr_info {
> > unsigned int num_core_clks;
> > unsigned int last_dt_core_clk;
> > unsigned int num_total_core_clks;
> > - bool stbyctrl;
> > + enum clk_reg_layout reg_layout;
>
> Seems like you forgot to update the struct's kerneldoc for this rename?
With that fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 3/4] clk: renesas: cpg-mssr: add register pointers into struct cpg_mssr_priv
2020-09-09 13:13 ` [PATCH v2 3/4] clk: renesas: cpg-mssr: add register pointers into struct cpg_mssr_priv Yoshihiro Shimoda
@ 2020-09-10 13:11 ` Geert Uytterhoeven
2020-09-11 4:16 ` Yoshihiro Shimoda
0 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2020-09-10 13:11 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: Magnus Damm, Linux-Renesas
Hi Shimoda-san,
On Wed, Sep 9, 2020 at 3:13 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> To support other register layout in the future, add register pointers
> of control_regs and status_regs into struct cpg_mssr_priv. After that,
> we can remove unused macros like MSTPSR(). No behavior changes.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -137,6 +130,8 @@ struct cpg_mssr_priv {
> unsigned int last_dt_core_clk;
>
> struct raw_notifier_head notifiers;
> + const u16 *status_regs;
> + const u16 *control_regs;
Please add new fields to the struct's kerneldoc comments above.
Note that you need to use a similar dispatching for the Software Reset
and Software Reset Clearing Registers, as their offsets differ from
previous SoCs.
The reset looks good to me, thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v2 4/4] clk: renesas: cpg-mssr: Add support for R-Car V3U
2020-09-09 13:13 ` [PATCH v2 4/4] clk: renesas: cpg-mssr: Add support for R-Car V3U Yoshihiro Shimoda
@ 2020-09-10 13:19 ` Geert Uytterhoeven
2020-09-11 4:41 ` Yoshihiro Shimoda
0 siblings, 1 reply; 13+ messages in thread
From: Geert Uytterhoeven @ 2020-09-10 13:19 UTC (permalink / raw)
To: Yoshihiro Shimoda; +Cc: Magnus Damm, Linux-Renesas
Hi Shimoda-san,
On Wed, Sep 9, 2020 at 3:13 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Initial support for R-Car V3U (r8a779a0), including core, module
> clocks and register access, because register specification differs
> from R-Car Gen2/3.
>
> Inspired by patches in the BSP by LUU HOAI.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks for the update!
> --- /dev/null
> +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> +#define CPG_PLL20CR 0x0834
> +#define CPG_PLL21CR 0x0838
> +#define CPG_PLL30CR 0x083c
> +#define CPG_PLL31CR 0x0840
> +
> +static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
> + /* External Clock Inputs */
> + DEF_INPUT("extal", CLK_EXTAL),
> + DEF_INPUT("extalr", CLK_EXTALR),
> +
> + /* Internal Core Clocks */
> + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
> + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
> + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
> + DEF_PLL(".pll20", CLK_PLL20, CPG_PLL20CR),
> + DEF_PLL(".pll21", CLK_PLL21, CPG_PLL21CR),
> + DEF_PLL(".pll30", CLK_PLL30, CPG_PLL30CR),
> + DEF_PLL(".pll31", CLK_PLL31, CPG_PLL31CR),
Given the users of the DEF_GEN3_SD() and DEF_DIV6P1() just hardcode the
register offsets, and the CPG_PLL*CR are used in a single place only,
perhaps it makes sense to hardcode the offsets here, too, and drop the
defines?
[...]
> + DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
> + DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
> + DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
> +/*
> + * CPG Clock Data
> + */
> +/*
> + * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 PLL6 OSC
> + * 14 13 (MHz) 21 31
> + * --------------------------------------------------------
> + * 0 0 16.66 x 1 x128 x216 x128 x144 x192 x128 /16
> + * 0 1 20 x 1 x106 x180 x106 x120 x160 x106 /19
> + * 1 0 Prohibited setting
> + * 1 1 33.33 / 2 x128 x216 x128 x144 x192 x128 /32
Please drop the PLL6 column, as PLL6 doesn't really exist.
> + */
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -57,6 +57,11 @@ static const u16 mstpsr[] = {
> 0x9A0, 0x9A4, 0x9A8, 0x9AC,
> };
>
> +static const u16 mstpsr_for_v3u[] = {
> + 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
> + 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
> +};
> +
> /*
> * System Module Stop Control Register offsets
> */
> @@ -66,6 +71,11 @@ static const u16 smstpcr[] = {
> 0x990, 0x994, 0x998, 0x99C,
> };
>
> +static const u16 mstpcr_for_v3u[] = {
> + 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
> + 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
> +};
> @@ -939,6 +955,9 @@ static int __init cpg_mssr_common_init(struct device *dev,
> priv->control_regs = smstpcr;
> } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
> priv->control_regs = stbcr;
> + } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
> + priv->status_regs = mstpsr_for_v3u;
> + priv->control_regs = mstpcr_for_v3u;
Missing arrays for V3U-specific srcr and srstclr.
> } else {
> error = -EINVAL;
> goto out_err;
The rest looks good to me!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 2/4] clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
2020-09-10 13:06 ` Geert Uytterhoeven
@ 2020-09-11 0:35 ` Yoshihiro Shimoda
0 siblings, 0 replies; 13+ messages in thread
From: Yoshihiro Shimoda @ 2020-09-11 0:35 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Magnus Damm, Linux-Renesas
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Thursday, September 10, 2020 10:07 PM
>
> On Thu, Sep 10, 2020 at 3:06 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, Sep 9, 2020 at 3:13 PM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > Geert suggested defining multiple registers layout variants using
> > > an enum [1] to support further devices like R-Car V3U. So, use enum
> > > clk_reg_layout instead of a boolean .stbyctrl flag. No behavior change.
> > >
> > > [1]
> > > https://lore.kernel.org/linux-renesas-soc/CAMuHMdVAgN69p9FFnQdO4iHk2CHkeNaVui2Q-FOY6_BFVjQ-Nw@mail.gmail.com/
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > > --- a/drivers/clk/renesas/renesas-cpg-mssr.h
> > > +++ b/drivers/clk/renesas/renesas-cpg-mssr.h
> >
> > > @@ -130,7 +135,7 @@ struct cpg_mssr_info {
> > > unsigned int num_core_clks;
> > > unsigned int last_dt_core_clk;
> > > unsigned int num_total_core_clks;
> > > - bool stbyctrl;
> > > + enum clk_reg_layout reg_layout;
> >
> > Seems like you forgot to update the struct's kerneldoc for this rename?
Oops. I'll update it.
> With that fixed:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thank you for your review!
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 3/4] clk: renesas: cpg-mssr: add register pointers into struct cpg_mssr_priv
2020-09-10 13:11 ` Geert Uytterhoeven
@ 2020-09-11 4:16 ` Yoshihiro Shimoda
0 siblings, 0 replies; 13+ messages in thread
From: Yoshihiro Shimoda @ 2020-09-11 4:16 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Magnus Damm, Linux-Renesas
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Thursday, September 10, 2020 10:11 PM
>
> Hi Shimoda-san,
>
> On Wed, Sep 9, 2020 at 3:13 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > To support other register layout in the future, add register pointers
> > of control_regs and status_regs into struct cpg_mssr_priv. After that,
> > we can remove unused macros like MSTPSR(). No behavior changes.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> > +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
>
> > @@ -137,6 +130,8 @@ struct cpg_mssr_priv {
> > unsigned int last_dt_core_clk;
> >
> > struct raw_notifier_head notifiers;
> > + const u16 *status_regs;
> > + const u16 *control_regs;
>
> Please add new fields to the struct's kerneldoc comments above.
Oops. I'll add such comments.
> Note that you need to use a similar dispatching for the Software Reset
> and Software Reset Clearing Registers, as their offsets differ from
> previous SoCs.
Indeed. I'll add these pointers.
> The reset looks good to me, thanks!
Thank you for your review!
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v2 4/4] clk: renesas: cpg-mssr: Add support for R-Car V3U
2020-09-10 13:19 ` Geert Uytterhoeven
@ 2020-09-11 4:41 ` Yoshihiro Shimoda
0 siblings, 0 replies; 13+ messages in thread
From: Yoshihiro Shimoda @ 2020-09-11 4:41 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: Magnus Damm, Linux-Renesas
Hi Geert-san,
Thank you for your review!
> From: Geert Uytterhoeven, Sent: Thursday, September 10, 2020 10:20 PM
>
> Hi Shimoda-san,
>
> On Wed, Sep 9, 2020 at 3:13 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > Initial support for R-Car V3U (r8a779a0), including core, module
> > clocks and register access, because register specification differs
> > from R-Car Gen2/3.
> >
> > Inspired by patches in the BSP by LUU HOAI.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Thanks for the update!
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
>
> > +#define CPG_PLL20CR 0x0834
> > +#define CPG_PLL21CR 0x0838
> > +#define CPG_PLL30CR 0x083c
> > +#define CPG_PLL31CR 0x0840
> > +
> > +static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
> > + /* External Clock Inputs */
> > + DEF_INPUT("extal", CLK_EXTAL),
> > + DEF_INPUT("extalr", CLK_EXTALR),
> > +
> > + /* Internal Core Clocks */
> > + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL),
> > + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN),
> > + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN),
> > + DEF_PLL(".pll20", CLK_PLL20, CPG_PLL20CR),
> > + DEF_PLL(".pll21", CLK_PLL21, CPG_PLL21CR),
> > + DEF_PLL(".pll30", CLK_PLL30, CPG_PLL30CR),
> > + DEF_PLL(".pll31", CLK_PLL31, CPG_PLL31CR),
>
> Given the users of the DEF_GEN3_SD() and DEF_DIV6P1() just hardcode the
> register offsets, and the CPG_PLL*CR are used in a single place only,
> perhaps it makes sense to hardcode the offsets here, too, and drop the
> defines?
I see. I'll fix it.
> [...]
>
> > + DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c),
> > + DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
> > + DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880),
>
> > +/*
> > + * CPG Clock Data
> > + */
> > +/*
> > + * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 PLL6 OSC
> > + * 14 13 (MHz) 21 31
> > + * --------------------------------------------------------
> > + * 0 0 16.66 x 1 x128 x216 x128 x144 x192 x128 /16
> > + * 0 1 20 x 1 x106 x180 x106 x120 x160 x106 /19
> > + * 1 0 Prohibited setting
> > + * 1 1 33.33 / 2 x128 x216 x128 x144 x192 x128 /32
>
> Please drop the PLL6 column, as PLL6 doesn't really exist.
Oops. I'll drop it.
> > + */
>
> > --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> > +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> > @@ -57,6 +57,11 @@ static const u16 mstpsr[] = {
> > 0x9A0, 0x9A4, 0x9A8, 0x9AC,
> > };
> >
> > +static const u16 mstpsr_for_v3u[] = {
> > + 0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
> > + 0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38,
> > +};
> > +
> > /*
> > * System Module Stop Control Register offsets
> > */
> > @@ -66,6 +71,11 @@ static const u16 smstpcr[] = {
> > 0x990, 0x994, 0x998, 0x99C,
> > };
> >
> > +static const u16 mstpcr_for_v3u[] = {
> > + 0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
> > + 0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38,
> > +};
>
> > @@ -939,6 +955,9 @@ static int __init cpg_mssr_common_init(struct device *dev,
> > priv->control_regs = smstpcr;
> > } else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
> > priv->control_regs = stbcr;
> > + } else if (priv->reg_layout == CLK_REG_LAYOUT_RCAR_V3U) {
> > + priv->status_regs = mstpsr_for_v3u;
> > + priv->control_regs = mstpcr_for_v3u;
>
> Missing arrays for V3U-specific srcr and srstclr.
I'll add these registers.
> > } else {
> > error = -EINVAL;
> > goto out_err;
>
> The rest looks good to me!
Thanks!
Best regards,
Yoshihiro Shimoda
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2020-09-11 4:41 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-09 13:13 [PATCH v2 0/4] clk: renesas: cpg-mssr: add support for V3U Yoshihiro Shimoda
2020-09-09 13:13 ` [PATCH v2 1/4] dt-bindings: clock: Add r8a779a0 CPG Core Clock Definitions Yoshihiro Shimoda
2020-09-10 12:56 ` Geert Uytterhoeven
2020-09-09 13:13 ` [PATCH v2 2/4] clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag Yoshihiro Shimoda
2020-09-10 13:06 ` Geert Uytterhoeven
2020-09-10 13:06 ` Geert Uytterhoeven
2020-09-11 0:35 ` Yoshihiro Shimoda
2020-09-09 13:13 ` [PATCH v2 3/4] clk: renesas: cpg-mssr: add register pointers into struct cpg_mssr_priv Yoshihiro Shimoda
2020-09-10 13:11 ` Geert Uytterhoeven
2020-09-11 4:16 ` Yoshihiro Shimoda
2020-09-09 13:13 ` [PATCH v2 4/4] clk: renesas: cpg-mssr: Add support for R-Car V3U Yoshihiro Shimoda
2020-09-10 13:19 ` Geert Uytterhoeven
2020-09-11 4:41 ` Yoshihiro Shimoda
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