* [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support
@ 2023-09-22 6:53 Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
` (15 more replies)
0 siblings, 16 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Add R-Car S4-8 (R-Car Gen4) PCIe controller for both host and endpoint modes.
To support them, modify PCIe DesignWare common codes.
Changes from v20 + squash patches:
https://lore.kernel.org/linux-pci/20230825093219.2685912-1-yoshihiro.shimoda.uh@renesas.com/
https://lore.kernel.org/linux-pci/20230901131711.2861283-1-yoshihiro.shimoda.uh@renesas.com/
- Based on the latest pci.git / next branch.
- Cherry-picked almost all patches from the pci.git / controller/rcar branch
for squashing.
- But, drop the following patches which are related to INTx.
eb185e1e628a PCI: designware-ep: Add INTx IRQs support
5d0e51f85b23 PCI: dwc: Add outbound MSG TLPs support
4758bef61cc2 PCI: dwc: Change arguments of dw_pcie_prog_outbound_atu()
44938b13046b PCI: Add INTx Mechanism Messages macros
- Add a new macro T_PVPERL in the patch 12/16.
- Merge pcie-rcar-gen4-{ep,host}-drv.c and pcie-rcar-gen4.h files into
pcie-rcar-gen4.c.
- Add CONFIG_PCIE_RCAR_GEN4_HOST config.
- Fix some comments.
- Change return type of rcar_gen4_pcie_speed_change().
- Add registers' full names as comments.
- Rename function names of rcar_gen4_{add,remove}_pcie_ep() to
rcar_gen4_{add,remove}_dw_pcie_ep() for consistency.
Yoshihiro Shimoda (16):
PCI: dwc: endpoint: Add multiple PFs support for dbi2
PCI: dwc: Add dw_pcie_link_set_max_link_width()
PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling
PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
PCI: dwc: Add EDMA_UNROLL capability flag
PCI: dwc: Expose dw_pcie_ep_exit() to module
PCI: dwc: Expose dw_pcie_write_dbi2() to module
PCI: dwc: endpoint: Introduce .pre_init() and .deinit()
dt-bindings: PCI: dwc: Update maxItems of reg and reg-names
dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint
PCI: add T_PVPERL macro
PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe Endpoint support
MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4
misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller
.../bindings/pci/rcar-gen4-pci-ep.yaml | 115 ++++
.../bindings/pci/rcar-gen4-pci-host.yaml | 127 +++++
.../bindings/pci/snps,dw-pcie-common.yaml | 4 +-
.../bindings/pci/snps,dw-pcie-ep.yaml | 4 +-
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 4 +-
MAINTAINERS | 1 +
drivers/misc/pci_endpoint_test.c | 4 +
drivers/pci/controller/dwc/Kconfig | 25 +
drivers/pci/controller/dwc/Makefile | 1 +
.../pci/controller/dwc/pcie-designware-ep.c | 45 +-
drivers/pci/controller/dwc/pcie-designware.c | 102 ++--
drivers/pci/controller/dwc/pcie-designware.h | 8 +-
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 510 ++++++++++++++++++
drivers/pci/controller/dwc/pcie-tegra194.c | 6 -
drivers/pci/pci.h | 3 +
15 files changed, 890 insertions(+), 69 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
--
2.25.1
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v21 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-10-10 11:12 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 02/16] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
` (14 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
for DWC") added .func_conf_select() to get the configuration space of
different PFs and assumed that the offsets between dbi and dbi2 would
be the same.
However, Renesas R-Car Gen4 PCIe controllers have different offsets of
function 1: dbi (+0x1000) and dbi2 (+0x800). To get the offset for dbi2,
add .get_dbi2_offset() and dw_pcie_ep_get_dbi2_offset().
Note:
- .func_conf_select() should be renamed later.
- dw_pcie_ep_get_dbi2_offset() will call .func_conf_select()
if .get_dbi2_offset() doesn't exist for backward compatibility.
- dw_pcie_writeX_{dbi/dbi2} APIs accepted the func_no argument,
so that these offset calculations are contained in the API
definitions itself as it should.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-6-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
---
.../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index f9182f8d552f..851538ddec0a 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -52,21 +52,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
return func_offset;
}
+static unsigned int dw_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep, u8 func_no)
+{
+ unsigned int dbi2_offset = 0;
+
+ if (ep->ops->get_dbi2_offset)
+ dbi2_offset = ep->ops->get_dbi2_offset(ep, func_no);
+ else if (ep->ops->func_conf_select) /* for backward compatibility */
+ dbi2_offset = ep->ops->func_conf_select(ep, func_no);
+
+ return dbi2_offset;
+}
+
static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
enum pci_barno bar, int flags)
{
- u32 reg;
- unsigned int func_offset = 0;
+ unsigned int func_offset, dbi2_offset;
struct dw_pcie_ep *ep = &pci->ep;
+ u32 reg, reg_dbi2;
func_offset = dw_pcie_ep_func_select(ep, func_no);
+ dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
+ reg_dbi2 = dbi2_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writel_dbi2(pci, reg, 0x0);
+ dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
dw_pcie_writel_dbi(pci, reg, 0x0);
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
+ dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
dw_pcie_writel_dbi(pci, reg + 4, 0x0);
}
dw_pcie_dbi_ro_wr_dis(pci);
@@ -228,16 +242,18 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
{
struct dw_pcie_ep *ep = epc_get_drvdata(epc);
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ unsigned int func_offset, dbi2_offset;
enum pci_barno bar = epf_bar->barno;
size_t size = epf_bar->size;
int flags = epf_bar->flags;
- unsigned int func_offset = 0;
+ u32 reg, reg_dbi2;
int ret, type;
- u32 reg;
func_offset = dw_pcie_ep_func_select(ep, func_no);
+ dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
+ reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + dbi2_offset;
if (!(flags & PCI_BASE_ADDRESS_SPACE))
type = PCIE_ATU_TYPE_MEM;
@@ -253,11 +269,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
dw_pcie_dbi_ro_wr_en(pci);
- dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
+ dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
dw_pcie_writel_dbi(pci, reg, flags);
if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
- dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
+ dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
dw_pcie_writel_dbi(pci, reg + 4, 0);
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index ef0b2efa9f93..6189884b4efa 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -341,6 +341,7 @@ struct dw_pcie_ep_ops {
* driver.
*/
unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
+ unsigned int (*get_dbi2_offset)(struct dw_pcie_ep *ep, u8 func_no);
};
struct dw_pcie_ep_func {
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 02/16] PCI: dwc: Add dw_pcie_link_set_max_link_width()
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 03/16] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
` (13 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin
This is a preparation before adding the Max-Link-width capability
setup which would in its turn complete the max-link-width setup
procedure defined by Synopsys in the HW-manual.
Seeing there is a max-link-speed setup method defined in the DW PCIe
core driver it would be good to have a similar function for the link
width setup.
That's why we need to define a dedicated function first from already
implemented but incomplete link-width setting up code.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-7-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 86 ++++++++++----------
1 file changed, 41 insertions(+), 45 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 1c1c7348972b..da4aba4aee62 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -732,6 +732,46 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
}
+static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
+{
+ u32 lwsc, plc;
+
+ if (!num_lanes)
+ return;
+
+ /* Set the number of lanes */
+ plc = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
+ plc &= ~PORT_LINK_FAST_LINK_MODE;
+ plc &= ~PORT_LINK_MODE_MASK;
+
+ /* Set link width speed control register */
+ lwsc = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ lwsc &= ~PORT_LOGIC_LINK_WIDTH_MASK;
+ switch (num_lanes) {
+ case 1:
+ plc |= PORT_LINK_MODE_1_LANES;
+ lwsc |= PORT_LOGIC_LINK_WIDTH_1_LANES;
+ break;
+ case 2:
+ plc |= PORT_LINK_MODE_2_LANES;
+ lwsc |= PORT_LOGIC_LINK_WIDTH_2_LANES;
+ break;
+ case 4:
+ plc |= PORT_LINK_MODE_4_LANES;
+ lwsc |= PORT_LOGIC_LINK_WIDTH_4_LANES;
+ break;
+ case 8:
+ plc |= PORT_LINK_MODE_8_LANES;
+ lwsc |= PORT_LOGIC_LINK_WIDTH_8_LANES;
+ break;
+ default:
+ dev_err(pci->dev, "num-lanes %u: invalid value\n", num_lanes);
+ return;
+ }
+ dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
+ dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
+}
+
void dw_pcie_iatu_detect(struct dw_pcie *pci)
{
int max_region, ob, ib;
@@ -1013,49 +1053,5 @@ void dw_pcie_setup(struct dw_pcie *pci)
val |= PORT_LINK_DLL_LINK_EN;
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
- if (!pci->num_lanes) {
- dev_dbg(pci->dev, "Using h/w default number of lanes\n");
- return;
- }
-
- /* Set the number of lanes */
- val &= ~PORT_LINK_FAST_LINK_MODE;
- val &= ~PORT_LINK_MODE_MASK;
- switch (pci->num_lanes) {
- case 1:
- val |= PORT_LINK_MODE_1_LANES;
- break;
- case 2:
- val |= PORT_LINK_MODE_2_LANES;
- break;
- case 4:
- val |= PORT_LINK_MODE_4_LANES;
- break;
- case 8:
- val |= PORT_LINK_MODE_8_LANES;
- break;
- default:
- dev_err(pci->dev, "num-lanes %u: invalid value\n", pci->num_lanes);
- return;
- }
- dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
-
- /* Set link width speed control register */
- val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
- val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
- switch (pci->num_lanes) {
- case 1:
- val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
- break;
- case 2:
- val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
- break;
- case 4:
- val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
- break;
- case 8:
- val |= PORT_LOGIC_LINK_WIDTH_8_LANES;
- break;
- }
- dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+ dw_pcie_link_set_max_link_width(pci, pci->num_lanes);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 03/16] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 02/16] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-10-10 11:14 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 04/16] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
` (12 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin
Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
field there is another one which needs to be updated.
It's LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
the very least the maximum link-width capability CSR won't expose the
actual maximum capability.
[1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 4.60a, March 2015, p.1032
[2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 4.70a, March 2016, p.1065
[3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 4.90a, March 2016, p.1057
...
[X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
Version 5.40a, March 2019, p.1396
[X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
Version 5.40a, March 2019, p.1266
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-8-yoshihiro.shimoda.uh@renesas.com
Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index da4aba4aee62..2b60d20dfdf5 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -734,7 +734,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
{
- u32 lwsc, plc;
+ u32 lnkcap, lwsc, plc;
+ u8 cap;
if (!num_lanes)
return;
@@ -770,6 +771,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
}
dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
+
+ cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+ lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
+ lnkcap &= ~PCI_EXP_LNKCAP_MLW;
+ lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
+ dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
}
void dw_pcie_iatu_detect(struct dw_pcie *pci)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 04/16] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (2 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 03/16] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 05/16] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
` (11 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin, Manivannan Sadhasivam,
Thierry Reding, Jonathan Hunter
dw_pcie_setup() is already setting PCI_EXP_LNKCAP_MLW to pcie->num_lanes
in the PCI_EXP_LNKCAP register for programming maximum link width.
Hence, remove the redundant setting here.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-9-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
---
drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 4bba31502ce1..2debdf1a0b52 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -917,12 +917,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
AMBA_ERROR_RESPONSE_CRS_SHIFT);
dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
- /* Configure Max lane width from DT */
- val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
- val &= ~PCI_EXP_LNKCAP_MLW;
- val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
- dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
-
/* Clear Slot Clock Configuration bit if SRNS configuration */
if (pcie->enable_srns) {
val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 05/16] PCI: dwc: Add EDMA_UNROLL capability flag
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (3 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 04/16] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 06/16] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
` (10 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin, Manivannan Sadhasivam
Renesas R-Car Gen4 PCIe controllers have an unexpected register value in
the eDMA CTRL register.
So, add a new capability flag "EDMA_UNROLL" which would force the unrolled
eDMA mapping for the problematic device.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-10-yoshihiro.shimoda.uh@renesas.com
Suggested-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-designware.c | 8 +++++++-
drivers/pci/controller/dwc/pcie-designware.h | 5 +++--
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 2b60d20dfdf5..1f900be94556 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -887,8 +887,14 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci)
* Indirect eDMA CSRs access has been completely removed since v5.40a
* thus no space is now reserved for the eDMA channels viewport and
* former DMA CTRL register is no longer fixed to FFs.
+ *
+ * Note that Renesas R-Car S4-8's PCIe controllers for unknown reason
+ * have zeros in the eDMA CTRL register even though the HW-manual
+ * explicitly states there must FFs if the unrolled mapping is enabled.
+ * For such cases the low-level drivers are supposed to manually
+ * activate the unrolled mapping to bypass the auto-detection procedure.
*/
- if (dw_pcie_ver_is_ge(pci, 540A))
+ if (dw_pcie_ver_is_ge(pci, 540A) || dw_pcie_cap_is(pci, EDMA_UNROLL))
val = 0xFFFFFFFF;
else
val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 6189884b4efa..e10f7e18b13a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -51,8 +51,9 @@
/* DWC PCIe controller capabilities */
#define DW_PCIE_CAP_REQ_RES 0
-#define DW_PCIE_CAP_IATU_UNROLL 1
-#define DW_PCIE_CAP_CDM_CHECK 2
+#define DW_PCIE_CAP_EDMA_UNROLL 1
+#define DW_PCIE_CAP_IATU_UNROLL 2
+#define DW_PCIE_CAP_CDM_CHECK 3
#define dw_pcie_cap_is(_pci, _cap) \
test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 06/16] PCI: dwc: Expose dw_pcie_ep_exit() to module
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (4 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 05/16] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 07/16] PCI: dwc: Expose dw_pcie_write_dbi2() " Yoshihiro Shimoda
` (9 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin, Manivannan Sadhasivam
Since no PCIe controller drivers call this, this change is not required
for now. But, Renesas R-Car Gen4 PCIe controller driver will call this
and if the controller driver is built as a kernel module, the following
build error happens:
ERROR: modpost: "dw_pcie_ep_exit" [drivers/pci/controller/dwc/pcie-rcar-gen4-ep-drv.ko] undefined!
So, expose dw_pcie_ep_exit() for it.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-11-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 851538ddec0a..a8bcbc57ef86 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -638,6 +638,7 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
pci_epc_mem_exit(epc);
}
+EXPORT_SYMBOL_GPL(dw_pcie_ep_exit);
static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 07/16] PCI: dwc: Expose dw_pcie_write_dbi2() to module
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (5 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 06/16] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-10-10 11:15 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 08/16] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Yoshihiro Shimoda
` (8 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin
Since no PCIe controller drivers call this, this change is not required
for now. But, Renesas R-Car Gen4 PCIe controller driver will call this
and if the controller driver is built as a kernel module, the following
build error happens:
ERROR: modpost: "dw_pcie_write_dbi2" [drivers/pci/controller/dwc/pcie-rcar-gen4-host-drv.ko] undefined!
So, expose dw_pcie_write_dbi2() for it.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-12-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 1f900be94556..250cf7f40b85 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -365,6 +365,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
if (ret)
dev_err(pci->dev, "write DBI address failed\n");
}
+EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2);
static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir,
u32 index)
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 08/16] PCI: dwc: endpoint: Introduce .pre_init() and .deinit()
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (6 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 07/16] PCI: dwc: Expose dw_pcie_write_dbi2() " Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-10-10 11:17 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 09/16] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
` (7 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin
Renesas R-Car Gen4 PCIe controllers require vendor-specific
initialization before .init().
To use dw->dbi and dw->num-lanes in the initialization code,
introduce .pre_init() into struct dw_pcie_ep_ops. While at it,
also introduce .deinit() to disable the controller by using
vendor-specific de-initialization.
Note that the ep_init in the struct dw_pcie_ep_ops should be
renamed to init later.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-13-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/pcie-designware-ep.c | 12 +++++++++++-
drivers/pci/controller/dwc/pcie-designware.h | 2 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index a8bcbc57ef86..d34a5e87ad18 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -637,6 +637,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
epc->mem->window.page_size);
pci_epc_mem_exit(epc);
+
+ if (ep->ops->deinit)
+ ep->ops->deinit(ep);
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_exit);
@@ -740,6 +743,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ep->phys_base = res->start;
ep->addr_size = resource_size(res);
+ if (ep->ops->pre_init)
+ ep->ops->pre_init(ep);
+
dw_pcie_version_detect(pci);
dw_pcie_iatu_detect(pci);
@@ -794,7 +800,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
ep->page_size);
if (ret < 0) {
dev_err(dev, "Failed to initialize address space\n");
- return ret;
+ goto err_ep_deinit;
}
ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
@@ -831,6 +837,10 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
err_exit_epc_mem:
pci_epc_mem_exit(epc);
+err_ep_deinit:
+ if (ep->ops->deinit)
+ ep->ops->deinit(ep);
+
return ret;
}
EXPORT_SYMBOL_GPL(dw_pcie_ep_init);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index e10f7e18b13a..8c637392ab08 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -330,7 +330,9 @@ struct dw_pcie_rp {
};
struct dw_pcie_ep_ops {
+ void (*pre_init)(struct dw_pcie_ep *ep);
void (*ep_init)(struct dw_pcie_ep *ep);
+ void (*deinit)(struct dw_pcie_ep *ep);
int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
enum pci_epc_irq_type type, u16 interrupt_num);
const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 09/16] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (7 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 08/16] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
` (6 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin, Conor Dooley
Update maxItems of reg and reg-names on both host and endpoint
for supporting Renesas R-Car Gen4 PCIe controllers later.
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-14-yoshihiro.shimoda.uh@renesas.com
Link: https://lore.kernel.org/linux-pci/20230901131711.2861283-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/pci/snps,dw-pcie-common.yaml | 4 ++--
Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 4 ++--
Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
index d87e13496834..dc05761c5cf9 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
@@ -33,11 +33,11 @@ properties:
specific for each activated function, while the rest of the sub-spaces
are common for all of them (if there are more than one).
minItems: 2
- maxItems: 6
+ maxItems: 7
reg-names:
minItems: 2
- maxItems: 6
+ maxItems: 7
interrupts:
description:
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
index 8fc2151691a4..bbdb01d22848 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
@@ -33,11 +33,11 @@ properties:
normal controller functioning. iATU memory IO region is also required
if the space is unrolled (IP-core version >= 4.80a).
minItems: 2
- maxItems: 5
+ maxItems: 7
reg-names:
minItems: 2
- maxItems: 5
+ maxItems: 7
items:
oneOf:
- description:
diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
index 8bbdeb8821f8..022055edbf9e 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
@@ -42,11 +42,11 @@ properties:
are required for the normal controller work. iATU memory IO region is
also required if the space is unrolled (IP-core version >= 4.80a).
minItems: 2
- maxItems: 5
+ maxItems: 7
reg-names:
minItems: 2
- maxItems: 5
+ maxItems: 7
items:
oneOf:
- description:
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (8 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 09/16] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-10-10 11:25 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 11/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
` (5 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Geert Uytterhoeven, Serge Semin, Conor Dooley
Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
PCIe host module.
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-15-yoshihiro.shimoda.uh@renesas.com
Link: https://lore.kernel.org/linux-pci/20230901131711.2861283-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/pci/rcar-gen4-pci-host.yaml | 127 ++++++++++++++++++
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
new file mode 100644
index 000000000000..ffb34339b637
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022-2023 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Gen4 PCIe Host
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+ - $ref: snps,dw-pcie.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: renesas,r8a779f0-pcie # R-Car S4-8
+ - const: renesas,rcar-gen4-pcie # R-Car Gen4
+
+ reg:
+ maxItems: 7
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: atu
+ - const: dma
+ - const: app
+ - const: phy
+ - const: config
+
+ interrupts:
+ maxItems: 4
+
+ interrupt-names:
+ items:
+ - const: msi
+ - const: dma
+ - const: sft_ce
+ - const: app
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: core
+ - const: ref
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pwr
+
+ max-link-speed:
+ maximum: 4
+
+ num-lanes:
+ maximum: 4
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a779f0-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie: pcie@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
+ <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ reset-names = "pwr";
+ max-link-speed = <4>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
+ <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
+ snps,enable-cdm-check;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 11/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (9 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 12/16] PCI: add T_PVPERL macro Yoshihiro Shimoda
` (4 subsequent siblings)
15 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Geert Uytterhoeven, Serge Semin, Conor Dooley
Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
PCIe endpoint module.
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-16-yoshihiro.shimoda.uh@renesas.com
Link: https://lore.kernel.org/linux-pci/20230901131711.2861283-4-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
---
.../bindings/pci/rcar-gen4-pci-ep.yaml | 115 ++++++++++++++++++
1 file changed, 115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
new file mode 100644
index 000000000000..fe38f62da066
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2022-2023 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Gen4 PCIe Endpoint
+
+maintainers:
+ - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+allOf:
+ - $ref: snps,dw-pcie-ep.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: renesas,r8a779f0-pcie-ep # R-Car S4-8
+ - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4
+
+ reg:
+ maxItems: 7
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: dbi2
+ - const: atu
+ - const: dma
+ - const: app
+ - const: phy
+ - const: addr_space
+
+ interrupts:
+ maxItems: 3
+
+ interrupt-names:
+ items:
+ - const: dma
+ - const: sft_ce
+ - const: app
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: core
+ - const: ref
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: pwr
+
+ max-link-speed:
+ maximum: 4
+
+ num-lanes:
+ maximum: 4
+
+ max-functions:
+ maximum: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - reset-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a779f0-sysc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcie0_ep: pcie-ep@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie-ep", "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
+ <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
+ interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
+ clock-names = "core", "ref";
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ reset-names = "pwr";
+ max-link-speed = <4>;
+ num-lanes = <2>;
+ max-functions = /bits/ 8 <2>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 12/16] PCI: add T_PVPERL macro
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (10 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 11/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-10-10 11:30 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support Yoshihiro Shimoda
` (3 subsequent siblings)
15 siblings, 1 reply; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
According to the PCI Express Card Electromechanical Specification,
Power stable to PERST# inactive interval is 100 ms as minimum.
So, add the macro to use PCIe controller drivers.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/pci/pci.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 39a8932dc340..5ecbcf041179 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -13,6 +13,9 @@
#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
+/* Power stable to PERST# inactive from PCIe card Electromechanical Spec */
+#define PCIE_T_PVPERL_MS 100
+
/*
* PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
* Recommends 1ms to 10ms timeout to check L2 ready.
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (11 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 12/16] PCI: add T_PVPERL macro Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-09-22 13:47 ` kernel test robot
2023-10-10 12:04 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 14/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
` (2 subsequent siblings)
15 siblings, 2 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin
Add R-Car Gen4 PCIe controller support for host mode.
This controller is based on Synopsys DesignWare PCIe. However, this
particular controller has a number of vendor-specific registers, and as
such, requires initialization code like mode setting and retraining and
so on.
[kwilczynski: commit log]
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-17-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/Kconfig | 14 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 380 ++++++++++++++++++++
3 files changed, 395 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index ab96da43e0c2..bc69fcab2e2a 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -415,4 +415,18 @@ config PCIE_VISCONTI_HOST
Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
This driver supports TMPV7708 SoC.
+config PCIE_RCAR_GEN4
+ tristate
+
+config PCIE_RCAR_GEN4_HOST
+ tristate "Renesas R-Car Gen4 PCIe controller (host mode)"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ depends on PCI_MSI
+ select PCIE_DW_HOST
+ select PCIE_RCAR_GEN4
+ help
+ Say Y here if you want PCIe controller (host mode) on R-Car Gen4 SoCs.
+ To compile this driver as a module, choose M here: the module will be
+ called pcie-rcar-gen4.ko. This uses the DesignWare core.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index bf5c311875a1..bac103faa523 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
+obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
new file mode 100644
index 000000000000..dfff6bb18932
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
+ * Copyright (C) 2022-2023 Renesas Electronics Corporation
+ */
+
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include "../../pci.h"
+#include "pcie-designware.h"
+
+/* Renesas-specific */
+/* PCIe Mode Setting Register 0 */
+#define PCIEMSR0 0x0000
+#define BIFUR_MOD_SET_ON BIT(0)
+#define DEVICE_TYPE_EP 0
+#define DEVICE_TYPE_RC BIT(4)
+
+/* PCIe Interrupt Status 0 */
+#define PCIEINTSTS0 0x0084
+
+/* PCIe Interrupt Status 0 Enable */
+#define PCIEINTSTS0EN 0x0310
+#define MSI_CTRL_INT BIT(26)
+#define SMLH_LINK_UP BIT(7)
+#define RDLH_LINK_UP BIT(6)
+
+/* PCIe DMA Interrupt Status Enable */
+#define PCIEDMAINTSTSEN 0x0314
+#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
+
+/* PCIe Reset Control Register 1 */
+#define PCIERSTCTRL1 0x0014
+#define APP_HOLD_PHY_RST BIT(16)
+#define APP_LTSSM_ENABLE BIT(0)
+
+#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
+#define RCAR_MAX_LINK_SPEED 4
+
+struct rcar_gen4_pcie {
+ struct dw_pcie dw;
+ void __iomem *base;
+ struct platform_device *pdev;
+ enum dw_pcie_device_mode mode;
+};
+#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
+
+static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
+ bool enable)
+{
+ u32 val;
+
+ val = readl(rcar->base + PCIERSTCTRL1);
+ if (enable) {
+ val |= APP_LTSSM_ENABLE;
+ val &= ~APP_HOLD_PHY_RST;
+ } else {
+ /*
+ * Since the datasheet of R-Car doesn't mention how to assert
+ * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
+ * hang-up issue happened in the dw_edma_core_off() when
+ * the controller didn't detect a PCI device.
+ */
+ val &= ~APP_LTSSM_ENABLE;
+ }
+ writel(val, rcar->base + PCIERSTCTRL1);
+}
+
+static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
+{
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ u32 val, mask;
+
+ val = readl(rcar->base + PCIEINTSTS0);
+ mask = RDLH_LINK_UP | SMLH_LINK_UP;
+
+ return (val & mask) == mask;
+}
+
+/*
+ * Manually initiate the speed change. Return true if the change succeeded,
+ * false if the change didn't finish within certain periods.
+ */
+static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
+{
+ u32 val;
+ int i;
+
+ val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+
+ val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val |= PORT_LOGIC_SPEED_CHANGE;
+ dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+
+ for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
+ val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
+ if (!(val & PORT_LOGIC_SPEED_CHANGE))
+ return 0;
+ usleep_range(10000, 11000);
+ }
+
+ return -ETIMEDOUT;
+}
+
+/*
+ * Enable LTSSM of this controller and manually initiate the speed change.
+ * Always return 0.
+ */
+static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
+{
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int i, changes;
+
+ rcar_gen4_pcie_ltssm_enable(rcar, true);
+
+ /*
+ * Require direct speed change with retrying here if the link_gen is
+ * PCIe Gen2 or higher.
+ */
+ changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
+
+ /*
+ * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
+ * So, this needs remaining times for up to PCIe Gen4 if RC mode.
+ */
+ if (changes && rcar->mode == DW_PCIE_RC_TYPE)
+ changes--;
+
+ for (i = 0; i < changes; i++) {
+ /* No error because possible disconnected here if EP mode */
+ if (rcar_gen4_pcie_speed_change(dw))
+ break;
+ }
+
+ return 0;
+}
+
+static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
+{
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+
+ rcar_gen4_pcie_ltssm_enable(rcar, false);
+}
+
+int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ u32 val;
+ int ret;
+
+ ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+ if (ret) {
+ dev_err(dw->dev, "Failed to enable ref clocks\n");
+ return ret;
+ }
+
+ if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
+ reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
+
+ val = readl(rcar->base + PCIEMSR0);
+ if (rcar->mode == DW_PCIE_RC_TYPE) {
+ val |= DEVICE_TYPE_RC;
+ } else if (rcar->mode == DW_PCIE_EP_TYPE) {
+ val |= DEVICE_TYPE_EP;
+ } else {
+ ret = -EINVAL;
+ goto err_unprepare;
+ }
+
+ if (dw->num_lanes < 4)
+ val |= BIFUR_MOD_SET_ON;
+
+ writel(val, rcar->base + PCIEMSR0);
+
+ ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
+ if (ret)
+ goto err_unprepare;
+
+ return 0;
+
+err_unprepare:
+ clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+
+ return ret;
+}
+
+void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+
+ reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
+ clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+}
+
+int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
+{
+ struct device *dev = rcar->dw.dev;
+ int err;
+
+ pm_runtime_enable(dev);
+ err = pm_runtime_resume_and_get(dev);
+ if (err < 0) {
+ dev_err(dev, "Failed to resume/get Runtime PM\n");
+ pm_runtime_disable(dev);
+ }
+
+ return err;
+}
+
+void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
+{
+ struct device *dev = rcar->dw.dev;
+
+ pm_runtime_put(dev);
+ pm_runtime_disable(dev);
+}
+
+int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
+{
+ /* Renesas-specific registers */
+ rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
+
+ return PTR_ERR_OR_ZERO(rcar->base);
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+ .start_link = rcar_gen4_pcie_start_link,
+ .stop_link = rcar_gen4_pcie_stop_link,
+ .link_up = rcar_gen4_pcie_link_up,
+};
+
+struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct rcar_gen4_pcie *rcar;
+
+ rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
+ if (!rcar)
+ return ERR_PTR(-ENOMEM);
+
+ rcar->dw.ops = &dw_pcie_ops;
+ rcar->dw.dev = dev;
+ rcar->pdev = pdev;
+ dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
+ dw_pcie_cap_set(&rcar->dw, REQ_RES);
+ platform_set_drvdata(pdev, rcar);
+
+ return rcar;
+}
+
+/* Host mode */
+static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int ret;
+ u32 val;
+
+ gpiod_set_value_cansleep(dw->pe_rst, 1);
+
+ ret = rcar_gen4_pcie_common_init(rcar);
+ if (ret)
+ return ret;
+
+ /*
+ * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
+ * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
+ * assignment during device enumeration.
+ */
+ dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
+ dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
+
+ /* Enable MSI interrupt signal */
+ val = readl(rcar->base + PCIEINTSTS0EN);
+ val |= MSI_CTRL_INT;
+ writel(val, rcar->base + PCIEINTSTS0EN);
+
+ msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */
+
+ gpiod_set_value_cansleep(dw->pe_rst, 0);
+
+ return 0;
+}
+
+static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+
+ gpiod_set_value_cansleep(dw->pe_rst, 1);
+ rcar_gen4_pcie_common_deinit(rcar);
+}
+
+static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
+ .host_init = rcar_gen4_pcie_host_init,
+ .host_deinit = rcar_gen4_pcie_host_deinit,
+};
+
+static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie_rp *pp = &rcar->dw.pp;
+
+ pp->num_vectors = MAX_MSI_IRQS;
+ pp->ops = &rcar_gen4_pcie_host_ops;
+ rcar->mode = DW_PCIE_RC_TYPE;
+
+ return dw_pcie_host_init(pp);
+}
+
+static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
+{
+ dw_pcie_host_deinit(&rcar->dw.pp);
+}
+
+static int rcar_gen4_pcie_probe(struct platform_device *pdev)
+{
+ struct rcar_gen4_pcie *rcar;
+ int err;
+
+ rcar = rcar_gen4_pcie_devm_alloc(pdev);
+ if (IS_ERR(rcar))
+ return PTR_ERR(rcar);
+
+ err = rcar_gen4_pcie_get_resources(rcar);
+ if (err)
+ return err;
+
+ err = rcar_gen4_pcie_prepare(rcar);
+ if (err)
+ return err;
+
+ err = rcar_gen4_add_dw_pcie_rp(rcar);
+ if (err)
+ goto err_unprepare;
+
+ return 0;
+
+err_unprepare:
+ rcar_gen4_pcie_unprepare(rcar);
+
+ return err;
+}
+
+static void rcar_gen4_pcie_remove(struct platform_device *pdev)
+{
+ struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
+
+ rcar_gen4_remove_dw_pcie_rp(rcar);
+ rcar_gen4_pcie_unprepare(rcar);
+}
+
+static const struct of_device_id rcar_gen4_pcie_of_match[] = {
+ { .compatible = "renesas,rcar-gen4-pcie", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match);
+
+static struct platform_driver rcar_gen4_pcie_driver = {
+ .driver = {
+ .name = "pcie-rcar-gen4",
+ .of_match_table = rcar_gen4_pcie_of_match,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ },
+ .probe = rcar_gen4_pcie_probe,
+ .remove_new = rcar_gen4_pcie_remove,
+};
+module_platform_driver(rcar_gen4_pcie_driver);
+
+MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe controller driver");
+MODULE_LICENSE("GPL");
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 14/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe Endpoint support
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (12 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-10-10 12:06 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 15/16] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 16/16] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
15 siblings, 1 reply; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin
Add R-Car Gen4 PCIe controller for endpoint mode. This controller is based
on Synopsys DesignWare PCIe.
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-18-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/pci/controller/dwc/Kconfig | 11 ++
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 136 +++++++++++++++++++-
2 files changed, 144 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index bc69fcab2e2a..e7fd37717998 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -429,4 +429,15 @@ config PCIE_RCAR_GEN4_HOST
To compile this driver as a module, choose M here: the module will be
called pcie-rcar-gen4.ko. This uses the DesignWare core.
+config PCIE_RCAR_GEN4_EP
+ tristate "Renesas R-Car Gen4 PCIe controller (endpoint mode)"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ depends on PCI_ENDPOINT
+ select PCIE_DW_EP
+ select PCIE_RCAR_GEN4
+ help
+ Say Y here if you want PCIe controller (endpoint mode) on R-Car Gen4
+ SoCs. To compile this driver as a module, choose M here: the module
+ will be called pcie-rcar-gen4.ko. This uses the DesignWare core.
+
endmenu
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index dfff6bb18932..68879b7308c5 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -45,6 +45,9 @@
#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
#define RCAR_MAX_LINK_SPEED 4
+#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
+#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
+
struct rcar_gen4_pcie {
struct dw_pcie dw;
void __iomem *base;
@@ -53,6 +56,7 @@ struct rcar_gen4_pcie {
};
#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
+/* Common */
static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
bool enable)
{
@@ -310,6 +314,9 @@ static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
{
struct dw_pcie_rp *pp = &rcar->dw.pp;
+ if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_HOST))
+ return -ENODEV;
+
pp->num_vectors = MAX_MSI_IRQS;
pp->ops = &rcar_gen4_pcie_host_ops;
rcar->mode = DW_PCIE_RC_TYPE;
@@ -322,8 +329,114 @@ static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
dw_pcie_host_deinit(&rcar->dw.pp);
}
+/* Endpoind mode */
+static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int ret;
+
+ ret = rcar_gen4_pcie_common_init(rcar);
+ if (ret)
+ return;
+
+ writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
+}
+
+static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ enum pci_barno bar;
+
+ for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
+ dw_pcie_ep_reset_bar(pci, bar);
+}
+
+static void rcar_gen4_pcie_ep_deinit(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+
+ writel(0, rcar->base + PCIEDMAINTSTSEN);
+ rcar_gen4_pcie_common_deinit(rcar);
+}
+
+static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+ unsigned int type, u16 interrupt_num)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
+
+ switch (type) {
+ case PCI_IRQ_LEGACY:
+ return dw_pcie_ep_raise_legacy_irq(ep, func_no);
+ case PCI_IRQ_MSI:
+ return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
+ default:
+ dev_err(dw->dev, "Unknown IRQ type\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
+ .align = SZ_1M,
+};
+
+static const struct pci_epc_features*
+rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep)
+{
+ return &rcar_gen4_pcie_epc_features;
+}
+
+static unsigned int rcar_gen4_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
+ u8 func_no)
+{
+ return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET;
+}
+
+static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
+ u8 func_no)
+{
+ return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET;
+}
+
+static const struct dw_pcie_ep_ops pcie_ep_ops = {
+ .pre_init = rcar_gen4_pcie_ep_pre_init,
+ .ep_init = rcar_gen4_pcie_ep_init,
+ .deinit = rcar_gen4_pcie_ep_deinit,
+ .raise_irq = rcar_gen4_pcie_ep_raise_irq,
+ .get_features = rcar_gen4_pcie_ep_get_features,
+ .func_conf_select = rcar_gen4_pcie_ep_func_conf_select,
+ .get_dbi2_offset = rcar_gen4_pcie_ep_get_dbi2_offset,
+};
+
+static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie_ep *ep = &rcar->dw.ep;
+
+ if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_EP))
+ return -ENODEV;
+
+ rcar->mode = DW_PCIE_EP_TYPE;
+ ep->ops = &pcie_ep_ops;
+
+ return dw_pcie_ep_init(ep);
+}
+
+static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
+{
+ dw_pcie_ep_exit(&rcar->dw.ep);
+}
+
+/* Common */
static int rcar_gen4_pcie_probe(struct platform_device *pdev)
{
+ enum dw_pcie_device_mode mode;
struct rcar_gen4_pcie *rcar;
int err;
@@ -339,7 +452,13 @@ static int rcar_gen4_pcie_probe(struct platform_device *pdev)
if (err)
return err;
- err = rcar_gen4_add_dw_pcie_rp(rcar);
+ mode = (enum dw_pcie_device_mode)of_device_get_match_data(&pdev->dev);
+
+ if (mode == DW_PCIE_RC_TYPE)
+ err = rcar_gen4_add_dw_pcie_rp(rcar);
+ else if (mode == DW_PCIE_EP_TYPE)
+ err = rcar_gen4_add_dw_pcie_ep(rcar);
+
if (err)
goto err_unprepare;
@@ -355,12 +474,23 @@ static void rcar_gen4_pcie_remove(struct platform_device *pdev)
{
struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
- rcar_gen4_remove_dw_pcie_rp(rcar);
+ if (rcar->mode == DW_PCIE_RC_TYPE)
+ rcar_gen4_remove_dw_pcie_rp(rcar);
+ else if (rcar->mode == DW_PCIE_EP_TYPE)
+ rcar_gen4_remove_dw_pcie_ep(rcar);
+
rcar_gen4_pcie_unprepare(rcar);
}
static const struct of_device_id rcar_gen4_pcie_of_match[] = {
- { .compatible = "renesas,rcar-gen4-pcie", },
+ {
+ .compatible = "renesas,rcar-gen4-pcie",
+ .data = (void *)DW_PCIE_RC_TYPE,
+ },
+ {
+ .compatible = "renesas,rcar-gen4-pcie-ep",
+ .data = (void *)DW_PCIE_EP_TYPE,
+ },
{},
};
MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match);
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 15/16] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (13 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 14/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 16/16] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
15 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda, Serge Semin
Update this entry for R-Car Gen4's source code.
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-19-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 90f13281d297..4115e648b4af 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16424,6 +16424,7 @@ L: linux-renesas-soc@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/pci/*rcar*
F: drivers/pci/controller/*rcar*
+F: drivers/pci/controller/dwc/*rcar*
PCI DRIVER FOR SAMSUNG EXYNOS
M: Jingoo Han <jingoohan1@gmail.com>
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v21 16/16] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
` (14 preceding siblings ...)
2023-09-22 6:53 ` [PATCH v21 15/16] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
@ 2023-09-22 6:53 ` Yoshihiro Shimoda
15 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-22 6:53 UTC (permalink / raw)
To: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani
Cc: marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Yoshihiro Shimoda
Add Renesas R8A779F0 in pci_device_id table so that pci-epf-test
can be used for testing PCIe EP on R-Car S4-8.
Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-20-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
---
drivers/misc/pci_endpoint_test.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index ed4d0ef5e5c3..150083dab71a 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -81,6 +81,7 @@
#define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
#define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
#define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
+#define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
static DEFINE_IDA(pci_endpoint_test_ida);
@@ -990,6 +991,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
+ { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),
+ .driver_data = (kernel_ulong_t)&default_data,
+ },
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
.driver_data = (kernel_ulong_t)&j721e_data,
},
--
2.25.1
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
2023-09-22 6:53 ` [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support Yoshihiro Shimoda
@ 2023-09-22 13:47 ` kernel test robot
2023-09-25 6:54 ` Yoshihiro Shimoda
2023-10-10 12:04 ` Manivannan Sadhasivam
1 sibling, 1 reply; 34+ messages in thread
From: kernel test robot @ 2023-09-22 13:47 UTC (permalink / raw)
To: Yoshihiro Shimoda, lpieralisi, kw, robh, bhelgaas,
krzysztof.kozlowski+dt, conor+dt, jingoohan1, gustavo.pimentel,
mani
Cc: oe-kbuild-all, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc, Yoshihiro Shimoda, Serge Semin
Hi Yoshihiro,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus linus/master v6.6-rc2 next-20230921]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Yoshihiro-Shimoda/PCI-dwc-endpoint-Add-multiple-PFs-support-for-dbi2/20230922-145529
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20230922065331.3806925-14-yoshihiro.shimoda.uh%40renesas.com
patch subject: [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
config: sparc-allyesconfig (https://download.01.org/0day-ci/archive/20230922/202309222125.KiN4nFhD-lkp@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230922/202309222125.KiN4nFhD-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309222125.KiN4nFhD-lkp@intel.com/
All warnings (new ones prefixed by >>):
>> drivers/pci/controller/dwc/pcie-rcar-gen4.c:155:5: warning: no previous prototype for 'rcar_gen4_pcie_common_init' [-Wmissing-prototypes]
155 | int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/controller/dwc/pcie-rcar-gen4.c:197:6: warning: no previous prototype for 'rcar_gen4_pcie_common_deinit' [-Wmissing-prototypes]
197 | void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/controller/dwc/pcie-rcar-gen4.c:205:5: warning: no previous prototype for 'rcar_gen4_pcie_prepare' [-Wmissing-prototypes]
205 | int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
| ^~~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/controller/dwc/pcie-rcar-gen4.c:220:6: warning: no previous prototype for 'rcar_gen4_pcie_unprepare' [-Wmissing-prototypes]
220 | void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
| ^~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/controller/dwc/pcie-rcar-gen4.c:228:5: warning: no previous prototype for 'rcar_gen4_pcie_get_resources' [-Wmissing-prototypes]
228 | int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/pci/controller/dwc/pcie-rcar-gen4.c:242:24: warning: no previous prototype for 'rcar_gen4_pcie_devm_alloc' [-Wmissing-prototypes]
242 | struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
vim +/rcar_gen4_pcie_common_init +155 drivers/pci/controller/dwc/pcie-rcar-gen4.c
154
> 155 int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
156 {
157 struct dw_pcie *dw = &rcar->dw;
158 u32 val;
159 int ret;
160
161 ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
162 if (ret) {
163 dev_err(dw->dev, "Failed to enable ref clocks\n");
164 return ret;
165 }
166
167 if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
168 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
169
170 val = readl(rcar->base + PCIEMSR0);
171 if (rcar->mode == DW_PCIE_RC_TYPE) {
172 val |= DEVICE_TYPE_RC;
173 } else if (rcar->mode == DW_PCIE_EP_TYPE) {
174 val |= DEVICE_TYPE_EP;
175 } else {
176 ret = -EINVAL;
177 goto err_unprepare;
178 }
179
180 if (dw->num_lanes < 4)
181 val |= BIFUR_MOD_SET_ON;
182
183 writel(val, rcar->base + PCIEMSR0);
184
185 ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
186 if (ret)
187 goto err_unprepare;
188
189 return 0;
190
191 err_unprepare:
192 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
193
194 return ret;
195 }
196
> 197 void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
198 {
199 struct dw_pcie *dw = &rcar->dw;
200
201 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
202 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
203 }
204
> 205 int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
206 {
207 struct device *dev = rcar->dw.dev;
208 int err;
209
210 pm_runtime_enable(dev);
211 err = pm_runtime_resume_and_get(dev);
212 if (err < 0) {
213 dev_err(dev, "Failed to resume/get Runtime PM\n");
214 pm_runtime_disable(dev);
215 }
216
217 return err;
218 }
219
> 220 void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
221 {
222 struct device *dev = rcar->dw.dev;
223
224 pm_runtime_put(dev);
225 pm_runtime_disable(dev);
226 }
227
> 228 int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
229 {
230 /* Renesas-specific registers */
231 rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
232
233 return PTR_ERR_OR_ZERO(rcar->base);
234 }
235
236 static const struct dw_pcie_ops dw_pcie_ops = {
237 .start_link = rcar_gen4_pcie_start_link,
238 .stop_link = rcar_gen4_pcie_stop_link,
239 .link_up = rcar_gen4_pcie_link_up,
240 };
241
> 242 struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
243 {
244 struct device *dev = &pdev->dev;
245 struct rcar_gen4_pcie *rcar;
246
247 rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
248 if (!rcar)
249 return ERR_PTR(-ENOMEM);
250
251 rcar->dw.ops = &dw_pcie_ops;
252 rcar->dw.dev = dev;
253 rcar->pdev = pdev;
254 dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
255 dw_pcie_cap_set(&rcar->dw, REQ_RES);
256 platform_set_drvdata(pdev, rcar);
257
258 return rcar;
259 }
260
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 34+ messages in thread
* RE: [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
2023-09-22 13:47 ` kernel test robot
@ 2023-09-25 6:54 ` Yoshihiro Shimoda
0 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-09-25 6:54 UTC (permalink / raw)
To: kernel test robot, lpieralisi, kw, robh, bhelgaas,
krzysztof.kozlowski+dt, conor+dt, jingoohan1, gustavo.pimentel,
mani
Cc: oe-kbuild-all, marek.vasut+renesas, linux-pci, devicetree,
linux-renesas-soc, Serge Semin
Hi kerenl test robot,
> From: kernel test robot, Sent: Friday, September 22, 2023 10:47 PM
>
> Hi Yoshihiro,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on pci/next]
> [also build test WARNING on pci/for-linus linus/master v6.6-rc2 next-20230921]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
<snip URLs>]
>
> url:
...
> base:
...
next
> patch link:
...
> patch subject: [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
> config: sparc-allyesconfig
...
> compiler: sparc64-linux-gcc (GCC) 13.2.0
> reproduce (this is a W=1 build):
...
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> | Reported-by: kernel test robot <lkp@intel.com>
> | Closes:
...
>
> All warnings (new ones prefixed by >>):
>
> >> drivers/pci/controller/dwc/pcie-rcar-gen4.c:155:5: warning: no previous prototype for 'rcar_gen4_pcie_common_init'
> [-Wmissing-prototypes]
> 155 | int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~
> >> drivers/pci/controller/dwc/pcie-rcar-gen4.c:197:6: warning: no previous prototype for 'rcar_gen4_pcie_common_deinit'
> [-Wmissing-prototypes]
> 197 | void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >> drivers/pci/controller/dwc/pcie-rcar-gen4.c:205:5: warning: no previous prototype for 'rcar_gen4_pcie_prepare'
> [-Wmissing-prototypes]
> 205 | int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
> | ^~~~~~~~~~~~~~~~~~~~~~
> >> drivers/pci/controller/dwc/pcie-rcar-gen4.c:220:6: warning: no previous prototype for 'rcar_gen4_pcie_unprepare'
> [-Wmissing-prototypes]
> 220 | void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
> | ^~~~~~~~~~~~~~~~~~~~~~~~
> >> drivers/pci/controller/dwc/pcie-rcar-gen4.c:228:5: warning: no previous prototype for 'rcar_gen4_pcie_get_resources'
> [-Wmissing-prototypes]
> 228 | int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >> drivers/pci/controller/dwc/pcie-rcar-gen4.c:242:24: warning: no previous prototype for 'rcar_gen4_pcie_devm_alloc'
> [-Wmissing-prototypes]
> 242 | struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
> | ^~~~~~~~~~~~~~~~~~~~~~~~~
Thank you for the review! I should have added "static" to each function.
I'll submit v22 patch series later.
Best regards,
Yoshihiro Shimoda
>
> vim +/rcar_gen4_pcie_common_init +155 drivers/pci/controller/dwc/pcie-rcar-gen4.c
>
> 154
> > 155 int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
> 156 {
> 157 struct dw_pcie *dw = &rcar->dw;
> 158 u32 val;
> 159 int ret;
> 160
> 161 ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> 162 if (ret) {
> 163 dev_err(dw->dev, "Failed to enable ref clocks\n");
> 164 return ret;
> 165 }
> 166
> 167 if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
> 168 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> 169
> 170 val = readl(rcar->base + PCIEMSR0);
> 171 if (rcar->mode == DW_PCIE_RC_TYPE) {
> 172 val |= DEVICE_TYPE_RC;
> 173 } else if (rcar->mode == DW_PCIE_EP_TYPE) {
> 174 val |= DEVICE_TYPE_EP;
> 175 } else {
> 176 ret = -EINVAL;
> 177 goto err_unprepare;
> 178 }
> 179
> 180 if (dw->num_lanes < 4)
> 181 val |= BIFUR_MOD_SET_ON;
> 182
> 183 writel(val, rcar->base + PCIEMSR0);
> 184
> 185 ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> 186 if (ret)
> 187 goto err_unprepare;
> 188
> 189 return 0;
> 190
> 191 err_unprepare:
> 192 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> 193
> 194 return ret;
> 195 }
> 196
> > 197 void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
> 198 {
> 199 struct dw_pcie *dw = &rcar->dw;
> 200
> 201 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> 202 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> 203 }
> 204
> > 205 int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
> 206 {
> 207 struct device *dev = rcar->dw.dev;
> 208 int err;
> 209
> 210 pm_runtime_enable(dev);
> 211 err = pm_runtime_resume_and_get(dev);
> 212 if (err < 0) {
> 213 dev_err(dev, "Failed to resume/get Runtime PM\n");
> 214 pm_runtime_disable(dev);
> 215 }
> 216
> 217 return err;
> 218 }
> 219
> > 220 void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
> 221 {
> 222 struct device *dev = rcar->dw.dev;
> 223
> 224 pm_runtime_put(dev);
> 225 pm_runtime_disable(dev);
> 226 }
> 227
> > 228 int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
> 229 {
> 230 /* Renesas-specific registers */
> 231 rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
> 232
> 233 return PTR_ERR_OR_ZERO(rcar->base);
> 234 }
> 235
> 236 static const struct dw_pcie_ops dw_pcie_ops = {
> 237 .start_link = rcar_gen4_pcie_start_link,
> 238 .stop_link = rcar_gen4_pcie_stop_link,
> 239 .link_up = rcar_gen4_pcie_link_up,
> 240 };
> 241
> > 242 struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
> 243 {
> 244 struct device *dev = &pdev->dev;
> 245 struct rcar_gen4_pcie *rcar;
> 246
> 247 rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
> 248 if (!rcar)
> 249 return ERR_PTR(-ENOMEM);
> 250
> 251 rcar->dw.ops = &dw_pcie_ops;
> 252 rcar->dw.dev = dev;
> 253 rcar->pdev = pdev;
> 254 dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
> 255 dw_pcie_cap_set(&rcar->dw, REQ_RES);
> 256 platform_set_drvdata(pdev, rcar);
> 257
> 258 return rcar;
> 259 }
> 260
>
> --
> 0-DAY CI Kernel Test Service
> https://github.com/intel/lkp-tests/wiki
> %7Cyoshihiro.shimoda.uh%40renesas.com%7Cbcb9117ada5545f21dd908dbbb7279cf%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%
> 7C638309872567098849%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C30
> 00%7C%7C%7C&sdata=hZzw8jndtIs8RuMO9fvilRhybUCLFgA7gEyUSEdxZuI%3D&reserved=0
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2
2023-09-22 6:53 ` [PATCH v21 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
@ 2023-10-10 11:12 ` Manivannan Sadhasivam
2023-10-11 0:46 ` Yoshihiro Shimoda
0 siblings, 1 reply; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-10 11:12 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, mani, marek.vasut+renesas,
linux-pci, devicetree, linux-renesas-soc
On Fri, Sep 22, 2023 at 03:53:16PM +0900, Yoshihiro Shimoda wrote:
> The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
> for DWC") added .func_conf_select() to get the configuration space of
> different PFs and assumed that the offsets between dbi and dbi2 would
> be the same.
>
> However, Renesas R-Car Gen4 PCIe controllers have different offsets of
> function 1: dbi (+0x1000) and dbi2 (+0x800). To get the offset for dbi2,
> add .get_dbi2_offset() and dw_pcie_ep_get_dbi2_offset().
>
> Note:
> - .func_conf_select() should be renamed later.
> - dw_pcie_ep_get_dbi2_offset() will call .func_conf_select()
> if .get_dbi2_offset() doesn't exist for backward compatibility.
> - dw_pcie_writeX_{dbi/dbi2} APIs accepted the func_no argument,
> so that these offset calculations are contained in the API
> definitions itself as it should.
>
> [kwilczynski: commit log]
> Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-6-yoshihiro.shimoda.uh@renesas.com
No need of the "Link". It will be added by the maintainer while applying this
patch.
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Your s-o-b tag should come last indicating that you are sending the patch.
- Mani
> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> ---
> .../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> 2 files changed, 25 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index f9182f8d552f..851538ddec0a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -52,21 +52,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
> return func_offset;
> }
>
> +static unsigned int dw_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep, u8 func_no)
> +{
> + unsigned int dbi2_offset = 0;
> +
> + if (ep->ops->get_dbi2_offset)
> + dbi2_offset = ep->ops->get_dbi2_offset(ep, func_no);
> + else if (ep->ops->func_conf_select) /* for backward compatibility */
> + dbi2_offset = ep->ops->func_conf_select(ep, func_no);
> +
> + return dbi2_offset;
> +}
> +
> static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
> enum pci_barno bar, int flags)
> {
> - u32 reg;
> - unsigned int func_offset = 0;
> + unsigned int func_offset, dbi2_offset;
> struct dw_pcie_ep *ep = &pci->ep;
> + u32 reg, reg_dbi2;
>
> func_offset = dw_pcie_ep_func_select(ep, func_no);
> + dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
>
> reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
> + reg_dbi2 = dbi2_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
> dw_pcie_dbi_ro_wr_en(pci);
> - dw_pcie_writel_dbi2(pci, reg, 0x0);
> + dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
> dw_pcie_writel_dbi(pci, reg, 0x0);
> if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> - dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
> + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
> dw_pcie_writel_dbi(pci, reg + 4, 0x0);
> }
> dw_pcie_dbi_ro_wr_dis(pci);
> @@ -228,16 +242,18 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> {
> struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + unsigned int func_offset, dbi2_offset;
> enum pci_barno bar = epf_bar->barno;
> size_t size = epf_bar->size;
> int flags = epf_bar->flags;
> - unsigned int func_offset = 0;
> + u32 reg, reg_dbi2;
> int ret, type;
> - u32 reg;
>
> func_offset = dw_pcie_ep_func_select(ep, func_no);
> + dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
>
> reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
> + reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + dbi2_offset;
>
> if (!(flags & PCI_BASE_ADDRESS_SPACE))
> type = PCIE_ATU_TYPE_MEM;
> @@ -253,11 +269,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
>
> dw_pcie_dbi_ro_wr_en(pci);
>
> - dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
> + dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
> dw_pcie_writel_dbi(pci, reg, flags);
>
> if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> - dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
> + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
> dw_pcie_writel_dbi(pci, reg + 4, 0);
> }
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index ef0b2efa9f93..6189884b4efa 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -341,6 +341,7 @@ struct dw_pcie_ep_ops {
> * driver.
> */
> unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
> + unsigned int (*get_dbi2_offset)(struct dw_pcie_ep *ep, u8 func_no);
> };
>
> struct dw_pcie_ep_func {
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 03/16] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling
2023-09-22 6:53 ` [PATCH v21 03/16] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
@ 2023-10-10 11:14 ` Manivannan Sadhasivam
0 siblings, 0 replies; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-10 11:14 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Serge Semin
On Fri, Sep 22, 2023 at 03:53:18PM +0900, Yoshihiro Shimoda wrote:
> Update dw_pcie_link_set_max_link_width() to set PCI_EXP_LNKCAP_MLW.
>
> In accordance with the DW PCIe RC/EP HW manuals [1,2,3,...] aside with
> the PORT_LINK_CTRL_OFF.LINK_CAPABLE and GEN2_CTRL_OFF.NUM_OF_LANES[8:0]
> field there is another one which needs to be updated.
>
> It's LINK_CAPABILITIES_REG.PCIE_CAP_MAX_LINK_WIDTH. If it isn't done at
> the very least the maximum link-width capability CSR won't expose the
> actual maximum capability.
>
> [1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> Version 4.60a, March 2015, p.1032
> [2] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> Version 4.70a, March 2016, p.1065
> [3] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> Version 4.90a, March 2016, p.1057
> ...
> [X] DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint,
> Version 5.40a, March 2019, p.1396
> [X+1] DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port,
> Version 5.40a, March 2019, p.1266
>
> [kwilczynski: commit log]
> Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-8-yoshihiro.shimoda.uh@renesas.com
> Suggested-by: Serge Semin <fancer.lancer@gmail.com>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Same comment about s-o-b.
- Mani
> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index da4aba4aee62..2b60d20dfdf5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -734,7 +734,8 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
>
> static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> {
> - u32 lwsc, plc;
> + u32 lnkcap, lwsc, plc;
> + u8 cap;
>
> if (!num_lanes)
> return;
> @@ -770,6 +771,12 @@ static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes)
> }
> dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, plc);
> dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, lwsc);
> +
> + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
> + lnkcap &= ~PCI_EXP_LNKCAP_MLW;
> + lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
> + dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
> }
>
> void dw_pcie_iatu_detect(struct dw_pcie *pci)
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 07/16] PCI: dwc: Expose dw_pcie_write_dbi2() to module
2023-09-22 6:53 ` [PATCH v21 07/16] PCI: dwc: Expose dw_pcie_write_dbi2() " Yoshihiro Shimoda
@ 2023-10-10 11:15 ` Manivannan Sadhasivam
0 siblings, 0 replies; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-10 11:15 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Serge Semin
On Fri, Sep 22, 2023 at 03:53:22PM +0900, Yoshihiro Shimoda wrote:
> Since no PCIe controller drivers call this, this change is not required
> for now. But, Renesas R-Car Gen4 PCIe controller driver will call this
> and if the controller driver is built as a kernel module, the following
> build error happens:
>
> ERROR: modpost: "dw_pcie_write_dbi2" [drivers/pci/controller/dwc/pcie-rcar-gen4-host-drv.ko] undefined!
>
> So, expose dw_pcie_write_dbi2() for it.
>
> [kwilczynski: commit log]
> Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-12-yoshihiro.shimoda.uh@renesas.com
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
(Fix the Link and s-o-b for all patches).
- Mani
> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 1f900be94556..250cf7f40b85 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -365,6 +365,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val)
> if (ret)
> dev_err(pci->dev, "write DBI address failed\n");
> }
> +EXPORT_SYMBOL_GPL(dw_pcie_write_dbi2);
>
> static inline void __iomem *dw_pcie_select_atu(struct dw_pcie *pci, u32 dir,
> u32 index)
> --
> 2.25.1
>
--
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^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 08/16] PCI: dwc: endpoint: Introduce .pre_init() and .deinit()
2023-09-22 6:53 ` [PATCH v21 08/16] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Yoshihiro Shimoda
@ 2023-10-10 11:17 ` Manivannan Sadhasivam
0 siblings, 0 replies; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-10 11:17 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Serge Semin
On Fri, Sep 22, 2023 at 03:53:23PM +0900, Yoshihiro Shimoda wrote:
> Renesas R-Car Gen4 PCIe controllers require vendor-specific
> initialization before .init().
>
> To use dw->dbi and dw->num-lanes in the initialization code,
> introduce .pre_init() into struct dw_pcie_ep_ops. While at it,
> also introduce .deinit() to disable the controller by using
> vendor-specific de-initialization.
>
> Note that the ep_init in the struct dw_pcie_ep_ops should be
> renamed to init later.
>
> [kwilczynski: commit log]
> Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-13-yoshihiro.shimoda.uh@renesas.com
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 12 +++++++++++-
> drivers/pci/controller/dwc/pcie-designware.h | 2 ++
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index a8bcbc57ef86..d34a5e87ad18 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -637,6 +637,9 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> epc->mem->window.page_size);
>
> pci_epc_mem_exit(epc);
> +
> + if (ep->ops->deinit)
> + ep->ops->deinit(ep);
> }
> EXPORT_SYMBOL_GPL(dw_pcie_ep_exit);
>
> @@ -740,6 +743,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> ep->phys_base = res->start;
> ep->addr_size = resource_size(res);
>
> + if (ep->ops->pre_init)
> + ep->ops->pre_init(ep);
> +
> dw_pcie_version_detect(pci);
>
> dw_pcie_iatu_detect(pci);
> @@ -794,7 +800,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> ep->page_size);
> if (ret < 0) {
> dev_err(dev, "Failed to initialize address space\n");
> - return ret;
> + goto err_ep_deinit;
> }
>
> ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
> @@ -831,6 +837,10 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> err_exit_epc_mem:
> pci_epc_mem_exit(epc);
>
> +err_ep_deinit:
> + if (ep->ops->deinit)
> + ep->ops->deinit(ep);
> +
> return ret;
> }
> EXPORT_SYMBOL_GPL(dw_pcie_ep_init);
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index e10f7e18b13a..8c637392ab08 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -330,7 +330,9 @@ struct dw_pcie_rp {
> };
>
> struct dw_pcie_ep_ops {
> + void (*pre_init)(struct dw_pcie_ep *ep);
> void (*ep_init)(struct dw_pcie_ep *ep);
> + void (*deinit)(struct dw_pcie_ep *ep);
> int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
> enum pci_epc_irq_type type, u16 interrupt_num);
> const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
> --
> 2.25.1
>
--
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^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
2023-09-22 6:53 ` [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
@ 2023-10-10 11:25 ` Manivannan Sadhasivam
2023-10-11 0:54 ` Yoshihiro Shimoda
0 siblings, 1 reply; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-10 11:25 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Geert Uytterhoeven, Serge Semin,
Conor Dooley
On Fri, Sep 22, 2023 at 03:53:25PM +0900, Yoshihiro Shimoda wrote:
> Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
> PCIe host module.
>
> Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-15-yoshihiro.shimoda.uh@renesas.com
> Link: https://lore.kernel.org/linux-pci/20230901131711.2861283-3-yoshihiro.shimoda.uh@renesas.com
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/pci/rcar-gen4-pci-host.yaml | 127 ++++++++++++++++++
> 1 file changed, 127 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> new file mode 100644
> index 000000000000..ffb34339b637
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> @@ -0,0 +1,127 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (C) 2022-2023 Renesas Electronics Corp.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas R-Car Gen4 PCIe Host
> +
> +maintainers:
> + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> +
> +allOf:
> + - $ref: snps,dw-pcie.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: renesas,r8a779f0-pcie # R-Car S4-8
> + - const: renesas,rcar-gen4-pcie # R-Car Gen4
> +
> + reg:
> + maxItems: 7
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: dbi2
> + - const: atu
> + - const: dma
> + - const: app
> + - const: phy
> + - const: config
> +
> + interrupts:
> + maxItems: 4
> +
> + interrupt-names:
> + items:
> + - const: msi
> + - const: dma
> + - const: sft_ce
> + - const: app
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: core
> + - const: ref
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + reset-names:
> + items:
> + - const: pwr
> +
> + max-link-speed:
> + maximum: 4
> +
> + num-lanes:
> + maximum: 4
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> + - power-domains
> + - resets
> + - reset-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/r8a779f0-sysc.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + pcie: pcie@e65d0000 {
> + compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
> + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
> + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
> + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
> + <0 0xfe000000 0 0x400000>;
> + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
> + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi", "dma", "sft_ce", "app";
> + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
> + clock-names = "core", "ref";
> + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> + resets = <&cpg 624>;
> + reset-names = "pwr";
> + max-link-speed = <4>;
> + num-lanes = <2>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x00 0xff>;
> + device_type = "pci";
> + ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
> + <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
> + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
I believe these are for legacy INTx interrupts. But you are using the same IRQ
number used for MSI above. Can you clarify?
- Mani
> + snps,enable-cdm-check;
> + };
> + };
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 12/16] PCI: add T_PVPERL macro
2023-09-22 6:53 ` [PATCH v21 12/16] PCI: add T_PVPERL macro Yoshihiro Shimoda
@ 2023-10-10 11:30 ` Manivannan Sadhasivam
2023-10-11 0:56 ` Yoshihiro Shimoda
0 siblings, 1 reply; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-10 11:30 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc
On Fri, Sep 22, 2023 at 03:53:27PM +0900, Yoshihiro Shimoda wrote:
> According to the PCI Express Card Electromechanical Specification,
> Power stable to PERST# inactive interval is 100 ms as minimum.
> So, add the macro to use PCIe controller drivers.
>
"Add a macro so that the PCIe controller drivers can make use of it."
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> ---
> drivers/pci/pci.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index 39a8932dc340..5ecbcf041179 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -13,6 +13,9 @@
>
> #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
>
> +/* Power stable to PERST# inactive from PCIe card Electromechanical Spec */
> +#define PCIE_T_PVPERL_MS 100
> +
> /*
> * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
> * Recommends 1ms to 10ms timeout to check L2 ready.
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
2023-09-22 6:53 ` [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support Yoshihiro Shimoda
2023-09-22 13:47 ` kernel test robot
@ 2023-10-10 12:04 ` Manivannan Sadhasivam
2023-10-11 1:18 ` Yoshihiro Shimoda
1 sibling, 1 reply; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-10 12:04 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Serge Semin
On Fri, Sep 22, 2023 at 03:53:28PM +0900, Yoshihiro Shimoda wrote:
> Add R-Car Gen4 PCIe controller support for host mode.
>
> This controller is based on Synopsys DesignWare PCIe. However, this
> particular controller has a number of vendor-specific registers, and as
> such, requires initialization code like mode setting and retraining and
> so on.
>
> [kwilczynski: commit log]
> Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-17-yoshihiro.shimoda.uh@renesas.com
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/controller/dwc/Kconfig | 14 +
> drivers/pci/controller/dwc/Makefile | 1 +
> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 380 ++++++++++++++++++++
> 3 files changed, 395 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index ab96da43e0c2..bc69fcab2e2a 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -415,4 +415,18 @@ config PCIE_VISCONTI_HOST
> Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> This driver supports TMPV7708 SoC.
>
> +config PCIE_RCAR_GEN4
> + tristate
> +
> +config PCIE_RCAR_GEN4_HOST
> + tristate "Renesas R-Car Gen4 PCIe controller (host mode)"
> + depends on ARCH_RENESAS || COMPILE_TEST
> + depends on PCI_MSI
> + select PCIE_DW_HOST
> + select PCIE_RCAR_GEN4
> + help
> + Say Y here if you want PCIe controller (host mode) on R-Car Gen4 SoCs.
> + To compile this driver as a module, choose M here: the module will be
> + called pcie-rcar-gen4.ko. This uses the DesignWare core.
> +
> endmenu
> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> index bf5c311875a1..bac103faa523 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
> obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
> obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> new file mode 100644
> index 000000000000..dfff6bb18932
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -0,0 +1,380 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
> + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +
> +#include "../../pci.h"
> +#include "pcie-designware.h"
> +
> +/* Renesas-specific */
> +/* PCIe Mode Setting Register 0 */
> +#define PCIEMSR0 0x0000
> +#define BIFUR_MOD_SET_ON BIT(0)
> +#define DEVICE_TYPE_EP 0
> +#define DEVICE_TYPE_RC BIT(4)
> +
> +/* PCIe Interrupt Status 0 */
> +#define PCIEINTSTS0 0x0084
> +
> +/* PCIe Interrupt Status 0 Enable */
> +#define PCIEINTSTS0EN 0x0310
> +#define MSI_CTRL_INT BIT(26)
> +#define SMLH_LINK_UP BIT(7)
> +#define RDLH_LINK_UP BIT(6)
> +
> +/* PCIe DMA Interrupt Status Enable */
> +#define PCIEDMAINTSTSEN 0x0314
> +#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
> +
> +/* PCIe Reset Control Register 1 */
> +#define PCIERSTCTRL1 0x0014
> +#define APP_HOLD_PHY_RST BIT(16)
> +#define APP_LTSSM_ENABLE BIT(0)
> +
> +#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
> +#define RCAR_MAX_LINK_SPEED 4
> +
> +struct rcar_gen4_pcie {
> + struct dw_pcie dw;
> + void __iomem *base;
> + struct platform_device *pdev;
> + enum dw_pcie_device_mode mode;
> +};
> +#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
> +
> +static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
> + bool enable)
> +{
> + u32 val;
> +
> + val = readl(rcar->base + PCIERSTCTRL1);
> + if (enable) {
> + val |= APP_LTSSM_ENABLE;
> + val &= ~APP_HOLD_PHY_RST;
> + } else {
> + /*
> + * Since the datasheet of R-Car doesn't mention how to assert
> + * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
> + * hang-up issue happened in the dw_edma_core_off() when
> + * the controller didn't detect a PCI device.
> + */
> + val &= ~APP_LTSSM_ENABLE;
> + }
> + writel(val, rcar->base + PCIERSTCTRL1);
> +}
> +
> +static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
> +{
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> + u32 val, mask;
> +
> + val = readl(rcar->base + PCIEINTSTS0);
> + mask = RDLH_LINK_UP | SMLH_LINK_UP;
> +
> + return (val & mask) == mask;
> +}
> +
> +/*
> + * Manually initiate the speed change. Return true if the change succeeded,
> + * false if the change didn't finish within certain periods.
This function returns 0 in success case and -ETIMEDOUT for failure. So the
comment should be fixed.
> + */
> +static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
> +{
> + u32 val;
> + int i;
> +
> + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + val &= ~PORT_LOGIC_SPEED_CHANGE;
> + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> +
> + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + val |= PORT_LOGIC_SPEED_CHANGE;
> + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> +
> + for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
> + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> + if (!(val & PORT_LOGIC_SPEED_CHANGE))
> + return 0;
> + usleep_range(10000, 11000);
> + }
> +
> + return -ETIMEDOUT;
> +}
> +
> +/*
> + * Enable LTSSM of this controller and manually initiate the speed change.
> + * Always return 0.
> + */
> +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
> +{
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> + int i, changes;
> +
> + rcar_gen4_pcie_ltssm_enable(rcar, true);
> +
> + /*
> + * Require direct speed change with retrying here if the link_gen is
> + * PCIe Gen2 or higher.
> + */
> + changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
> +
> + /*
> + * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
> + * So, this needs remaining times for up to PCIe Gen4 if RC mode.
> + */
> + if (changes && rcar->mode == DW_PCIE_RC_TYPE)
> + changes--;
> +
> + for (i = 0; i < changes; i++) {
> + /* No error because possible disconnected here if EP mode */
This comment is not grammatically correct.
> + if (rcar_gen4_pcie_speed_change(dw))
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
> +{
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> +
> + rcar_gen4_pcie_ltssm_enable(rcar, false);
> +}
> +
> +int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
> +{
> + struct dw_pcie *dw = &rcar->dw;
> + u32 val;
> + int ret;
> +
> + ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> + if (ret) {
> + dev_err(dw->dev, "Failed to enable ref clocks\n");
Not all clocks are reference clocks.
> + return ret;
> + }
> +
> + if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
> + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> +
> + val = readl(rcar->base + PCIEMSR0);
> + if (rcar->mode == DW_PCIE_RC_TYPE) {
> + val |= DEVICE_TYPE_RC;
> + } else if (rcar->mode == DW_PCIE_EP_TYPE) {
> + val |= DEVICE_TYPE_EP;
> + } else {
> + ret = -EINVAL;
> + goto err_unprepare;
> + }
> +
> + if (dw->num_lanes < 4)
> + val |= BIFUR_MOD_SET_ON;
> +
> + writel(val, rcar->base + PCIEMSR0);
> +
> + ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> + if (ret)
> + goto err_unprepare;
> +
> + return 0;
> +
> +err_unprepare:
> + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> +
> + return ret;
> +}
> +
> +void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
> +{
> + struct dw_pcie *dw = &rcar->dw;
> +
> + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> +}
> +
> +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
> +{
> + struct device *dev = rcar->dw.dev;
> + int err;
> +
> + pm_runtime_enable(dev);
> + err = pm_runtime_resume_and_get(dev);
> + if (err < 0) {
> + dev_err(dev, "Failed to resume/get Runtime PM\n");
"Runtime resume failed\n"
> + pm_runtime_disable(dev);
> + }
> +
> + return err;
> +}
> +
> +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
> +{
> + struct device *dev = rcar->dw.dev;
> +
> + pm_runtime_put(dev);
> + pm_runtime_disable(dev);
> +}
> +
> +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
> +{
> + /* Renesas-specific registers */
> + rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
> +
> + return PTR_ERR_OR_ZERO(rcar->base);
> +}
> +
> +static const struct dw_pcie_ops dw_pcie_ops = {
> + .start_link = rcar_gen4_pcie_start_link,
> + .stop_link = rcar_gen4_pcie_stop_link,
> + .link_up = rcar_gen4_pcie_link_up,
> +};
> +
> +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
You should not name the functions based on the internal APIs. Please use
something like, rcar_gen4_pcie_drv_alloc() or just rcar_gen4_pcie_alloc().
> +{
> + struct device *dev = &pdev->dev;
> + struct rcar_gen4_pcie *rcar;
> +
> + rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
> + if (!rcar)
> + return ERR_PTR(-ENOMEM);
> +
> + rcar->dw.ops = &dw_pcie_ops;
> + rcar->dw.dev = dev;
> + rcar->pdev = pdev;
> + dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
> + dw_pcie_cap_set(&rcar->dw, REQ_RES);
> + platform_set_drvdata(pdev, rcar);
> +
> + return rcar;
> +}
> +
> +/* Host mode */
> +static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> + int ret;
> + u32 val;
> +
> + gpiod_set_value_cansleep(dw->pe_rst, 1);
> +
> + ret = rcar_gen4_pcie_common_init(rcar);
> + if (ret)
> + return ret;
> +
> + /*
> + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> + * assignment during device enumeration.
> + */
> + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
> + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
If this is DWC specific, can we move it to the common code?
> +
> + /* Enable MSI interrupt signal */
> + val = readl(rcar->base + PCIEINTSTS0EN);
> + val |= MSI_CTRL_INT;
> + writel(val, rcar->base + PCIEINTSTS0EN);
> +
Above should be guarded with:
if (IS_ENABLED(CONFIG_PCI_MSI)) {
...
}
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 14/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe Endpoint support
2023-09-22 6:53 ` [PATCH v21 14/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
@ 2023-10-10 12:06 ` Manivannan Sadhasivam
0 siblings, 0 replies; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-10 12:06 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Serge Semin
On Fri, Sep 22, 2023 at 03:53:29PM +0900, Yoshihiro Shimoda wrote:
> Add R-Car Gen4 PCIe controller for endpoint mode. This controller is based
> on Synopsys DesignWare PCIe.
>
> Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-18-yoshihiro.shimoda.uh@renesas.com
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
- Mani
> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> ---
> drivers/pci/controller/dwc/Kconfig | 11 ++
> drivers/pci/controller/dwc/pcie-rcar-gen4.c | 136 +++++++++++++++++++-
> 2 files changed, 144 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index bc69fcab2e2a..e7fd37717998 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -429,4 +429,15 @@ config PCIE_RCAR_GEN4_HOST
> To compile this driver as a module, choose M here: the module will be
> called pcie-rcar-gen4.ko. This uses the DesignWare core.
>
> +config PCIE_RCAR_GEN4_EP
> + tristate "Renesas R-Car Gen4 PCIe controller (endpoint mode)"
> + depends on ARCH_RENESAS || COMPILE_TEST
> + depends on PCI_ENDPOINT
> + select PCIE_DW_EP
> + select PCIE_RCAR_GEN4
> + help
> + Say Y here if you want PCIe controller (endpoint mode) on R-Car Gen4
> + SoCs. To compile this driver as a module, choose M here: the module
> + will be called pcie-rcar-gen4.ko. This uses the DesignWare core.
> +
> endmenu
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> index dfff6bb18932..68879b7308c5 100644
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -45,6 +45,9 @@
> #define RCAR_NUM_SPEED_CHANGE_RETRIES 10
> #define RCAR_MAX_LINK_SPEED 4
>
> +#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
> +#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
> +
> struct rcar_gen4_pcie {
> struct dw_pcie dw;
> void __iomem *base;
> @@ -53,6 +56,7 @@ struct rcar_gen4_pcie {
> };
> #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
>
> +/* Common */
> static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
> bool enable)
> {
> @@ -310,6 +314,9 @@ static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> {
> struct dw_pcie_rp *pp = &rcar->dw.pp;
>
> + if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_HOST))
> + return -ENODEV;
> +
> pp->num_vectors = MAX_MSI_IRQS;
> pp->ops = &rcar_gen4_pcie_host_ops;
> rcar->mode = DW_PCIE_RC_TYPE;
> @@ -322,8 +329,114 @@ static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
> dw_pcie_host_deinit(&rcar->dw.pp);
> }
>
> +/* Endpoind mode */
> +static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> + int ret;
> +
> + ret = rcar_gen4_pcie_common_init(rcar);
> + if (ret)
> + return;
> +
> + writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
> +}
> +
> +static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + enum pci_barno bar;
> +
> + for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> + dw_pcie_ep_reset_bar(pci, bar);
> +}
> +
> +static void rcar_gen4_pcie_ep_deinit(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> +
> + writel(0, rcar->base + PCIEDMAINTSTSEN);
> + rcar_gen4_pcie_common_deinit(rcar);
> +}
> +
> +static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> + unsigned int type, u16 interrupt_num)
> +{
> + struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
> +
> + switch (type) {
> + case PCI_IRQ_LEGACY:
> + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> + case PCI_IRQ_MSI:
> + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> + default:
> + dev_err(dw->dev, "Unknown IRQ type\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
> + .linkup_notifier = false,
> + .msi_capable = true,
> + .msix_capable = false,
> + .reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
> + .align = SZ_1M,
> +};
> +
> +static const struct pci_epc_features*
> +rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep)
> +{
> + return &rcar_gen4_pcie_epc_features;
> +}
> +
> +static unsigned int rcar_gen4_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
> + u8 func_no)
> +{
> + return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET;
> +}
> +
> +static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
> + u8 func_no)
> +{
> + return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET;
> +}
> +
> +static const struct dw_pcie_ep_ops pcie_ep_ops = {
> + .pre_init = rcar_gen4_pcie_ep_pre_init,
> + .ep_init = rcar_gen4_pcie_ep_init,
> + .deinit = rcar_gen4_pcie_ep_deinit,
> + .raise_irq = rcar_gen4_pcie_ep_raise_irq,
> + .get_features = rcar_gen4_pcie_ep_get_features,
> + .func_conf_select = rcar_gen4_pcie_ep_func_conf_select,
> + .get_dbi2_offset = rcar_gen4_pcie_ep_get_dbi2_offset,
> +};
> +
> +static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
> +{
> + struct dw_pcie_ep *ep = &rcar->dw.ep;
> +
> + if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_EP))
> + return -ENODEV;
> +
> + rcar->mode = DW_PCIE_EP_TYPE;
> + ep->ops = &pcie_ep_ops;
> +
> + return dw_pcie_ep_init(ep);
> +}
> +
> +static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
> +{
> + dw_pcie_ep_exit(&rcar->dw.ep);
> +}
> +
> +/* Common */
> static int rcar_gen4_pcie_probe(struct platform_device *pdev)
> {
> + enum dw_pcie_device_mode mode;
> struct rcar_gen4_pcie *rcar;
> int err;
>
> @@ -339,7 +452,13 @@ static int rcar_gen4_pcie_probe(struct platform_device *pdev)
> if (err)
> return err;
>
> - err = rcar_gen4_add_dw_pcie_rp(rcar);
> + mode = (enum dw_pcie_device_mode)of_device_get_match_data(&pdev->dev);
> +
> + if (mode == DW_PCIE_RC_TYPE)
> + err = rcar_gen4_add_dw_pcie_rp(rcar);
> + else if (mode == DW_PCIE_EP_TYPE)
> + err = rcar_gen4_add_dw_pcie_ep(rcar);
> +
> if (err)
> goto err_unprepare;
>
> @@ -355,12 +474,23 @@ static void rcar_gen4_pcie_remove(struct platform_device *pdev)
> {
> struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
>
> - rcar_gen4_remove_dw_pcie_rp(rcar);
> + if (rcar->mode == DW_PCIE_RC_TYPE)
> + rcar_gen4_remove_dw_pcie_rp(rcar);
> + else if (rcar->mode == DW_PCIE_EP_TYPE)
> + rcar_gen4_remove_dw_pcie_ep(rcar);
> +
> rcar_gen4_pcie_unprepare(rcar);
> }
>
> static const struct of_device_id rcar_gen4_pcie_of_match[] = {
> - { .compatible = "renesas,rcar-gen4-pcie", },
> + {
> + .compatible = "renesas,rcar-gen4-pcie",
> + .data = (void *)DW_PCIE_RC_TYPE,
> + },
> + {
> + .compatible = "renesas,rcar-gen4-pcie-ep",
> + .data = (void *)DW_PCIE_EP_TYPE,
> + },
> {},
> };
> MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match);
> --
> 2.25.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* RE: [PATCH v21 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2
2023-10-10 11:12 ` Manivannan Sadhasivam
@ 2023-10-11 0:46 ` Yoshihiro Shimoda
0 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-10-11 0:46 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc
Hello Manivannan,
> From: Manivannan Sadhasivam, Sent: Tuesday, October 10, 2023 8:12 PM
>
> On Fri, Sep 22, 2023 at 03:53:16PM +0900, Yoshihiro Shimoda wrote:
> > The commit 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support
> > for DWC") added .func_conf_select() to get the configuration space of
> > different PFs and assumed that the offsets between dbi and dbi2 would
> > be the same.
> >
> > However, Renesas R-Car Gen4 PCIe controllers have different offsets of
> > function 1: dbi (+0x1000) and dbi2 (+0x800). To get the offset for dbi2,
> > add .get_dbi2_offset() and dw_pcie_ep_get_dbi2_offset().
> >
> > Note:
> > - .func_conf_select() should be renamed later.
> > - dw_pcie_ep_get_dbi2_offset() will call .func_conf_select()
> > if .get_dbi2_offset() doesn't exist for backward compatibility.
> > - dw_pcie_writeX_{dbi/dbi2} APIs accepted the func_no argument,
> > so that these offset calculations are contained in the API
> > definitions itself as it should.
> >
> > [kwilczynski: commit log]
> > Link: https://lore.kernel.org/linux-pci/20230825093219.2685912-6-yoshihiro.shimoda.uh@renesas.com/
>
> No need of the "Link". It will be added by the maintainer while applying this
> patch.
I got it. I'll remove this.
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thank you for your review!
> Your s-o-b tag should come last indicating that you are sending the patch.
I got it. I also got a comment from Bjorn [1], so I'll remove Krzysztof's s-o-b tag.
[1] https://lore.kernel.org/all/20231005150907.GA746291@bhelgaas/
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> > ---
> > .../pci/controller/dwc/pcie-designware-ep.c | 32 ++++++++++++++-----
> > drivers/pci/controller/dwc/pcie-designware.h | 1 +
> > 2 files changed, 25 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > index f9182f8d552f..851538ddec0a 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> > @@ -52,21 +52,35 @@ static unsigned int dw_pcie_ep_func_select(struct dw_pcie_ep *ep, u8 func_no)
> > return func_offset;
> > }
> >
> > +static unsigned int dw_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep, u8 func_no)
> > +{
> > + unsigned int dbi2_offset = 0;
> > +
> > + if (ep->ops->get_dbi2_offset)
> > + dbi2_offset = ep->ops->get_dbi2_offset(ep, func_no);
> > + else if (ep->ops->func_conf_select) /* for backward compatibility */
> > + dbi2_offset = ep->ops->func_conf_select(ep, func_no);
> > +
> > + return dbi2_offset;
> > +}
> > +
> > static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, u8 func_no,
> > enum pci_barno bar, int flags)
> > {
> > - u32 reg;
> > - unsigned int func_offset = 0;
> > + unsigned int func_offset, dbi2_offset;
> > struct dw_pcie_ep *ep = &pci->ep;
> > + u32 reg, reg_dbi2;
> >
> > func_offset = dw_pcie_ep_func_select(ep, func_no);
> > + dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
> >
> > reg = func_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
> > + reg_dbi2 = dbi2_offset + PCI_BASE_ADDRESS_0 + (4 * bar);
> > dw_pcie_dbi_ro_wr_en(pci);
> > - dw_pcie_writel_dbi2(pci, reg, 0x0);
> > + dw_pcie_writel_dbi2(pci, reg_dbi2, 0x0);
> > dw_pcie_writel_dbi(pci, reg, 0x0);
> > if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > - dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
> > + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, 0x0);
> > dw_pcie_writel_dbi(pci, reg + 4, 0x0);
> > }
> > dw_pcie_dbi_ro_wr_dis(pci);
> > @@ -228,16 +242,18 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> > {
> > struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> > struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > + unsigned int func_offset, dbi2_offset;
> > enum pci_barno bar = epf_bar->barno;
> > size_t size = epf_bar->size;
> > int flags = epf_bar->flags;
> > - unsigned int func_offset = 0;
> > + u32 reg, reg_dbi2;
> > int ret, type;
> > - u32 reg;
> >
> > func_offset = dw_pcie_ep_func_select(ep, func_no);
> > + dbi2_offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);
> >
> > reg = PCI_BASE_ADDRESS_0 + (4 * bar) + func_offset;
> > + reg_dbi2 = PCI_BASE_ADDRESS_0 + (4 * bar) + dbi2_offset;
> >
> > if (!(flags & PCI_BASE_ADDRESS_SPACE))
> > type = PCIE_ATU_TYPE_MEM;
> > @@ -253,11 +269,11 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
> >
> > dw_pcie_dbi_ro_wr_en(pci);
> >
> > - dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
> > + dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1));
> > dw_pcie_writel_dbi(pci, reg, flags);
> >
> > if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
> > - dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
> > + dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1));
> > dw_pcie_writel_dbi(pci, reg + 4, 0);
> > }
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> > index ef0b2efa9f93..6189884b4efa 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -341,6 +341,7 @@ struct dw_pcie_ep_ops {
> > * driver.
> > */
> > unsigned int (*func_conf_select)(struct dw_pcie_ep *ep, u8 func_no);
> > + unsigned int (*get_dbi2_offset)(struct dw_pcie_ep *ep, u8 func_no);
> > };
> >
> > struct dw_pcie_ep_func {
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* RE: [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
2023-10-10 11:25 ` Manivannan Sadhasivam
@ 2023-10-11 0:54 ` Yoshihiro Shimoda
2023-10-11 4:43 ` Manivannan Sadhasivam
0 siblings, 1 reply; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-10-11 0:54 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Geert Uytterhoeven, Serge Semin,
Conor Dooley
Hello Manivannan,
> From: Manivannan Sadhasivam, Sent: Tuesday, October 10, 2023 8:25 PM
> To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Cc: lpieralisi@kernel.org; kw@linux.com; robh@kernel.org; bhelgaas@google.com; krzysztof.kozlowski+dt@linaro.org;
> conor+dt@kernel.org; jingoohan1@gmail.com; gustavo.pimentel@synopsys.com; marek.vasut+renesas@gmail.com;
> linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-renesas-soc@vger.kernel.org; Geert Uytterhoeven
> <geert+renesas@glider.be>; Serge Semin <fancer.lancer@gmail.com>; Conor Dooley <conor.dooley@microchip.com>
> Subject: Re: [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
>
> On Fri, Sep 22, 2023 at 03:53:25PM +0900, Yoshihiro Shimoda wrote:
> > Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
> > PCIe host module.
> >
> > Link:
<snip URL>
> > Link:
<snip URL>
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > .../bindings/pci/rcar-gen4-pci-host.yaml | 127 ++++++++++++++++++
> > 1 file changed, 127 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> > new file mode 100644
> > index 000000000000..ffb34339b637
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> > @@ -0,0 +1,127 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (C) 2022-2023 Renesas Electronics Corp.
> > +%YAML 1.2
> > +---
> > +$id:
<snip URL>
> > +$schema:
<snip URL>
> > +
> > +title: Renesas R-Car Gen4 PCIe Host
> > +
> > +maintainers:
> > + - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > +
> > +allOf:
> > + - $ref: snps,dw-pcie.yaml#
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: renesas,r8a779f0-pcie # R-Car S4-8
> > + - const: renesas,rcar-gen4-pcie # R-Car Gen4
> > +
> > + reg:
> > + maxItems: 7
> > +
> > + reg-names:
> > + items:
> > + - const: dbi
> > + - const: dbi2
> > + - const: atu
> > + - const: dma
> > + - const: app
> > + - const: phy
> > + - const: config
> > +
> > + interrupts:
> > + maxItems: 4
> > +
> > + interrupt-names:
> > + items:
> > + - const: msi
> > + - const: dma
> > + - const: sft_ce
> > + - const: app
> > +
> > + clocks:
> > + maxItems: 2
> > +
> > + clock-names:
> > + items:
> > + - const: core
> > + - const: ref
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + reset-names:
> > + items:
> > + - const: pwr
> > +
> > + max-link-speed:
> > + maximum: 4
> > +
> > + num-lanes:
> > + maximum: 4
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > + - clock-names
> > + - power-domains
> > + - resets
> > + - reset-names
> > +
> > +unevaluatedProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/power/r8a779f0-sysc.h>
> > +
> > + soc {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + pcie: pcie@e65d0000 {
> > + compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie";
> > + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
> > + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
> > + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
> > + <0 0xfe000000 0 0x400000>;
> > + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
> > + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "msi", "dma", "sft_ce", "app";
> > + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
> > + clock-names = "core", "ref";
> > + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> > + resets = <&cpg 624>;
> > + reset-names = "pwr";
> > + max-link-speed = <4>;
> > + num-lanes = <2>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + bus-range = <0x00 0xff>;
> > + device_type = "pci";
> > + ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
> > + <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
> > + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
>
> I believe these are for legacy INTx interrupts. But you are using the same IRQ
> number used for MSI above. Can you clarify?
On the SoC (R-Car S4-8), the same IRQ number is used for both MSI and legacy INTx
interrupts...
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > + snps,enable-cdm-check;
> > + };
> > + };
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* RE: [PATCH v21 12/16] PCI: add T_PVPERL macro
2023-10-10 11:30 ` Manivannan Sadhasivam
@ 2023-10-11 0:56 ` Yoshihiro Shimoda
0 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-10-11 0:56 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc
Hello Manivannan,
> From: Manivannan Sadhasivam, Sent: Tuesday, October 10, 2023 8:31 PM
>
> On Fri, Sep 22, 2023 at 03:53:27PM +0900, Yoshihiro Shimoda wrote:
> > According to the PCI Express Card Electromechanical Specification,
> > Power stable to PERST# inactive interval is 100 ms as minimum.
> > So, add the macro to use PCIe controller drivers.
> >
>
> "Add a macro so that the PCIe controller drivers can make use of it."
I'll revise this.
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thank you for your review!
Best regards,
Yoshihiro Shimoda
> - Mani
>
> > ---
> > drivers/pci/pci.h | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > index 39a8932dc340..5ecbcf041179 100644
> > --- a/drivers/pci/pci.h
> > +++ b/drivers/pci/pci.h
> > @@ -13,6 +13,9 @@
> >
> > #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
> >
> > +/* Power stable to PERST# inactive from PCIe card Electromechanical Spec */
> > +#define PCIE_T_PVPERL_MS 100
> > +
> > /*
> > * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
> > * Recommends 1ms to 10ms timeout to check L2 ready.
> > --
> > 2.25.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* RE: [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
2023-10-10 12:04 ` Manivannan Sadhasivam
@ 2023-10-11 1:18 ` Yoshihiro Shimoda
2023-10-11 4:41 ` Manivannan Sadhasivam
0 siblings, 1 reply; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-10-11 1:18 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Serge Semin
Hello Manivannan,
> From: Manivannan Sadhasivam, Sent: Tuesday, October 10, 2023 9:04 PM
>
> On Fri, Sep 22, 2023 at 03:53:28PM +0900, Yoshihiro Shimoda wrote:
> > Add R-Car Gen4 PCIe controller support for host mode.
> >
> > This controller is based on Synopsys DesignWare PCIe. However, this
> > particular controller has a number of vendor-specific registers, and as
> > such, requires initialization code like mode setting and retraining and
> > so on.
> >
> > [kwilczynski: commit log]
> > Link:
<snip URL>
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > ---
> > drivers/pci/controller/dwc/Kconfig | 14 +
> > drivers/pci/controller/dwc/Makefile | 1 +
> > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 380 ++++++++++++++++++++
> > 3 files changed, 395 insertions(+)
> > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
> >
> > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > index ab96da43e0c2..bc69fcab2e2a 100644
> > --- a/drivers/pci/controller/dwc/Kconfig
> > +++ b/drivers/pci/controller/dwc/Kconfig
> > @@ -415,4 +415,18 @@ config PCIE_VISCONTI_HOST
> > Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> > This driver supports TMPV7708 SoC.
> >
> > +config PCIE_RCAR_GEN4
> > + tristate
> > +
> > +config PCIE_RCAR_GEN4_HOST
> > + tristate "Renesas R-Car Gen4 PCIe controller (host mode)"
> > + depends on ARCH_RENESAS || COMPILE_TEST
> > + depends on PCI_MSI
> > + select PCIE_DW_HOST
> > + select PCIE_RCAR_GEN4
> > + help
> > + Say Y here if you want PCIe controller (host mode) on R-Car Gen4 SoCs.
> > + To compile this driver as a module, choose M here: the module will be
> > + called pcie-rcar-gen4.ko. This uses the DesignWare core.
> > +
> > endmenu
> > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> > index bf5c311875a1..bac103faa523 100644
> > --- a/drivers/pci/controller/dwc/Makefile
> > +++ b/drivers/pci/controller/dwc/Makefile
> > @@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
> > obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
> > obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> > obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> > +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
> >
> > # The following drivers are for devices that use the generic ACPI
> > # pci_root.c driver but don't support standard ECAM config access.
> > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > new file mode 100644
> > index 000000000000..dfff6bb18932
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > @@ -0,0 +1,380 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
> > + * Copyright (C) 2022-2023 Renesas Electronics Corporation
> > + */
> > +
> > +#include <linux/delay.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/pci.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/reset.h>
> > +
> > +#include "../../pci.h"
> > +#include "pcie-designware.h"
> > +
> > +/* Renesas-specific */
> > +/* PCIe Mode Setting Register 0 */
> > +#define PCIEMSR0 0x0000
> > +#define BIFUR_MOD_SET_ON BIT(0)
> > +#define DEVICE_TYPE_EP 0
> > +#define DEVICE_TYPE_RC BIT(4)
> > +
> > +/* PCIe Interrupt Status 0 */
> > +#define PCIEINTSTS0 0x0084
> > +
> > +/* PCIe Interrupt Status 0 Enable */
> > +#define PCIEINTSTS0EN 0x0310
> > +#define MSI_CTRL_INT BIT(26)
> > +#define SMLH_LINK_UP BIT(7)
> > +#define RDLH_LINK_UP BIT(6)
> > +
> > +/* PCIe DMA Interrupt Status Enable */
> > +#define PCIEDMAINTSTSEN 0x0314
> > +#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
> > +
> > +/* PCIe Reset Control Register 1 */
> > +#define PCIERSTCTRL1 0x0014
> > +#define APP_HOLD_PHY_RST BIT(16)
> > +#define APP_LTSSM_ENABLE BIT(0)
> > +
> > +#define RCAR_NUM_SPEED_CHANGE_RETRIES 10
> > +#define RCAR_MAX_LINK_SPEED 4
> > +
> > +struct rcar_gen4_pcie {
> > + struct dw_pcie dw;
> > + void __iomem *base;
> > + struct platform_device *pdev;
> > + enum dw_pcie_device_mode mode;
> > +};
> > +#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
> > +
> > +static void rcar_gen4_pcie_ltssm_enable(struct rcar_gen4_pcie *rcar,
> > + bool enable)
> > +{
> > + u32 val;
> > +
> > + val = readl(rcar->base + PCIERSTCTRL1);
> > + if (enable) {
> > + val |= APP_LTSSM_ENABLE;
> > + val &= ~APP_HOLD_PHY_RST;
> > + } else {
> > + /*
> > + * Since the datasheet of R-Car doesn't mention how to assert
> > + * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
> > + * hang-up issue happened in the dw_edma_core_off() when
> > + * the controller didn't detect a PCI device.
> > + */
> > + val &= ~APP_LTSSM_ENABLE;
> > + }
> > + writel(val, rcar->base + PCIERSTCTRL1);
> > +}
> > +
> > +static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
> > +{
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > + u32 val, mask;
> > +
> > + val = readl(rcar->base + PCIEINTSTS0);
> > + mask = RDLH_LINK_UP | SMLH_LINK_UP;
> > +
> > + return (val & mask) == mask;
> > +}
> > +
> > +/*
> > + * Manually initiate the speed change. Return true if the change succeeded,
> > + * false if the change didn't finish within certain periods.
>
> This function returns 0 in success case and -ETIMEDOUT for failure. So the
> comment should be fixed.
Thank you for your comment! I also got a comment from Bjorn [1]. So,
I'll fix it and submit patch series as v24.
[1] https://lore.kernel.org/linux-pci/20231005150907.GA746291@bhelgaas/
> > + */
> > +static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
> > +{
> > + u32 val;
> > + int i;
> > +
> > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > + val &= ~PORT_LOGIC_SPEED_CHANGE;
> > + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > +
> > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > + val |= PORT_LOGIC_SPEED_CHANGE;
> > + dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > +
> > + for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
> > + val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
> > + if (!(val & PORT_LOGIC_SPEED_CHANGE))
> > + return 0;
> > + usleep_range(10000, 11000);
> > + }
> > +
> > + return -ETIMEDOUT;
> > +}
> > +
> > +/*
> > + * Enable LTSSM of this controller and manually initiate the speed change.
> > + * Always return 0.
> > + */
> > +static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
> > +{
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > + int i, changes;
> > +
> > + rcar_gen4_pcie_ltssm_enable(rcar, true);
> > +
> > + /*
> > + * Require direct speed change with retrying here if the link_gen is
> > + * PCIe Gen2 or higher.
> > + */
> > + changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
> > +
> > + /*
> > + * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
> > + * So, this needs remaining times for up to PCIe Gen4 if RC mode.
> > + */
> > + if (changes && rcar->mode == DW_PCIE_RC_TYPE)
> > + changes--;
> > +
> > + for (i = 0; i < changes; i++) {
> > + /* No error because possible disconnected here if EP mode */
>
> This comment is not grammatically correct.
I'll fix this comment.
> > + if (rcar_gen4_pcie_speed_change(dw))
> > + break;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
> > +{
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > +
> > + rcar_gen4_pcie_ltssm_enable(rcar, false);
> > +}
> > +
> > +int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
> > +{
> > + struct dw_pcie *dw = &rcar->dw;
> > + u32 val;
> > + int ret;
> > +
> > + ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > + if (ret) {
> > + dev_err(dw->dev, "Failed to enable ref clocks\n");
>
> Not all clocks are reference clocks.
I'll fix this message.
> > + return ret;
> > + }
> > +
> > + if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
> > + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > +
> > + val = readl(rcar->base + PCIEMSR0);
> > + if (rcar->mode == DW_PCIE_RC_TYPE) {
> > + val |= DEVICE_TYPE_RC;
> > + } else if (rcar->mode == DW_PCIE_EP_TYPE) {
> > + val |= DEVICE_TYPE_EP;
> > + } else {
> > + ret = -EINVAL;
> > + goto err_unprepare;
> > + }
> > +
> > + if (dw->num_lanes < 4)
> > + val |= BIFUR_MOD_SET_ON;
> > +
> > + writel(val, rcar->base + PCIEMSR0);
> > +
> > + ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > + if (ret)
> > + goto err_unprepare;
> > +
> > + return 0;
> > +
> > +err_unprepare:
> > + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > +
> > + return ret;
> > +}
> > +
> > +void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
> > +{
> > + struct dw_pcie *dw = &rcar->dw;
> > +
> > + reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
> > + clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
> > +}
> > +
> > +int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
> > +{
> > + struct device *dev = rcar->dw.dev;
> > + int err;
> > +
> > + pm_runtime_enable(dev);
> > + err = pm_runtime_resume_and_get(dev);
> > + if (err < 0) {
> > + dev_err(dev, "Failed to resume/get Runtime PM\n");
>
> "Runtime resume failed\n"
Thank you for your suggestion. I'll fix it.
> > + pm_runtime_disable(dev);
> > + }
> > +
> > + return err;
> > +}
> > +
> > +void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
> > +{
> > + struct device *dev = rcar->dw.dev;
> > +
> > + pm_runtime_put(dev);
> > + pm_runtime_disable(dev);
> > +}
> > +
> > +int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
> > +{
> > + /* Renesas-specific registers */
> > + rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
> > +
> > + return PTR_ERR_OR_ZERO(rcar->base);
> > +}
> > +
> > +static const struct dw_pcie_ops dw_pcie_ops = {
> > + .start_link = rcar_gen4_pcie_start_link,
> > + .stop_link = rcar_gen4_pcie_stop_link,
> > + .link_up = rcar_gen4_pcie_link_up,
> > +};
> > +
> > +struct rcar_gen4_pcie *rcar_gen4_pcie_devm_alloc(struct platform_device *pdev)
>
> You should not name the functions based on the internal APIs. Please use
> something like, rcar_gen4_pcie_drv_alloc() or just rcar_gen4_pcie_alloc().
I got it. I'll rename this function name.
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct rcar_gen4_pcie *rcar;
> > +
> > + rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
> > + if (!rcar)
> > + return ERR_PTR(-ENOMEM);
> > +
> > + rcar->dw.ops = &dw_pcie_ops;
> > + rcar->dw.dev = dev;
> > + rcar->pdev = pdev;
> > + dw_pcie_cap_set(&rcar->dw, EDMA_UNROLL);
> > + dw_pcie_cap_set(&rcar->dw, REQ_RES);
> > + platform_set_drvdata(pdev, rcar);
> > +
> > + return rcar;
> > +}
> > +
> > +/* Host mode */
> > +static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
> > +{
> > + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > + int ret;
> > + u32 val;
> > +
> > + gpiod_set_value_cansleep(dw->pe_rst, 1);
> > +
> > + ret = rcar_gen4_pcie_common_init(rcar);
> > + if (ret)
> > + return ret;
> > +
> > + /*
> > + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> > + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> > + * assignment during device enumeration.
> > + */
> > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
> > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
>
> If this is DWC specific, can we move it to the common code?
Hmm, it seems so. However, I didn't find any similar code on other DWC drivers.
So, for now, moving it to the common code is not needed, I think.
> > +
> > + /* Enable MSI interrupt signal */
> > + val = readl(rcar->base + PCIEINTSTS0EN);
> > + val |= MSI_CTRL_INT;
> > + writel(val, rcar->base + PCIEINTSTS0EN);
> > +
>
> Above should be guarded with:
>
> if (IS_ENABLED(CONFIG_PCI_MSI)) {
> ...
> }
Since this driver depends on PCI_MSI by Kconfig, such a IS_ENABLED is not
needed. This is from your suggestion ;) [2]
[2] https://lore.kernel.org/linux-devicetree/20230724122820.GM6291@thinkpad/
Best regards,
Yoshihiro Shimoda
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
2023-10-11 1:18 ` Yoshihiro Shimoda
@ 2023-10-11 4:41 ` Manivannan Sadhasivam
2023-10-11 5:06 ` Yoshihiro Shimoda
0 siblings, 1 reply; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-11 4:41 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Manivannan Sadhasivam, lpieralisi, kw, robh, bhelgaas,
krzysztof.kozlowski+dt, conor+dt, jingoohan1, gustavo.pimentel,
marek.vasut+renesas, linux-pci, devicetree, linux-renesas-soc,
Serge Semin
On Wed, Oct 11, 2023 at 01:18:11AM +0000, Yoshihiro Shimoda wrote:
> Hello Manivannan,
>
> > From: Manivannan Sadhasivam, Sent: Tuesday, October 10, 2023 9:04 PM
> >
> > On Fri, Sep 22, 2023 at 03:53:28PM +0900, Yoshihiro Shimoda wrote:
> > > Add R-Car Gen4 PCIe controller support for host mode.
> > >
> > > This controller is based on Synopsys DesignWare PCIe. However, this
> > > particular controller has a number of vendor-specific registers, and as
> > > such, requires initialization code like mode setting and retraining and
> > > so on.
> > >
> > > [kwilczynski: commit log]
> > > Link:
> <snip URL>
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > ---
> > > drivers/pci/controller/dwc/Kconfig | 14 +
> > > drivers/pci/controller/dwc/Makefile | 1 +
> > > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 380 ++++++++++++++++++++
> > > 3 files changed, 395 insertions(+)
> > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > >
> > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > > index ab96da43e0c2..bc69fcab2e2a 100644
> > > --- a/drivers/pci/controller/dwc/Kconfig
> > > +++ b/drivers/pci/controller/dwc/Kconfig
> > > @@ -415,4 +415,18 @@ config PCIE_VISCONTI_HOST
> > > Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> > > This driver supports TMPV7708 SoC.
> > >
> > > +config PCIE_RCAR_GEN4
> > > + tristate
> > > +
> > > +config PCIE_RCAR_GEN4_HOST
> > > + tristate "Renesas R-Car Gen4 PCIe controller (host mode)"
> > > + depends on ARCH_RENESAS || COMPILE_TEST
> > > + depends on PCI_MSI
> > > + select PCIE_DW_HOST
> > > + select PCIE_RCAR_GEN4
> > > + help
> > > + Say Y here if you want PCIe controller (host mode) on R-Car Gen4 SoCs.
> > > + To compile this driver as a module, choose M here: the module will be
> > > + called pcie-rcar-gen4.ko. This uses the DesignWare core.
> > > +
> > > endmenu
> > > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> > > index bf5c311875a1..bac103faa523 100644
> > > --- a/drivers/pci/controller/dwc/Makefile
> > > +++ b/drivers/pci/controller/dwc/Makefile
> > > @@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
> > > obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
> > > obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> > > obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> > > +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
> > >
> > > # The following drivers are for devices that use the generic ACPI
> > > # pci_root.c driver but don't support standard ECAM config access.
> > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > new file mode 100644
> > > index 000000000000..dfff6bb18932
> > > --- /dev/null
> > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
[...]
> > > +/* Host mode */
> > > +static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
> > > +{
> > > + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > + int ret;
> > > + u32 val;
> > > +
> > > + gpiod_set_value_cansleep(dw->pe_rst, 1);
> > > +
> > > + ret = rcar_gen4_pcie_common_init(rcar);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + /*
> > > + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> > > + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> > > + * assignment during device enumeration.
> > > + */
> > > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
> > > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
> >
> > If this is DWC specific, can we move it to the common code?
>
> Hmm, it seems so. However, I didn't find any similar code on other DWC drivers.
> So, for now, moving it to the common code is not needed, I think.
>
No. If this is as per the DWC spec, then it should be part of the common code.
> > > +
> > > + /* Enable MSI interrupt signal */
> > > + val = readl(rcar->base + PCIEINTSTS0EN);
> > > + val |= MSI_CTRL_INT;
> > > + writel(val, rcar->base + PCIEINTSTS0EN);
> > > +
> >
> > Above should be guarded with:
> >
> > if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > ...
> > }
>
> Since this driver depends on PCI_MSI by Kconfig, such a IS_ENABLED is not
> needed. This is from your suggestion ;) [2]
>
> [2] https://lore.kernel.org/linux-devicetree/20230724122820.GM6291@thinkpad/
>
heh... thanks for reminding me ;)
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
2023-10-11 0:54 ` Yoshihiro Shimoda
@ 2023-10-11 4:43 ` Manivannan Sadhasivam
0 siblings, 0 replies; 34+ messages in thread
From: Manivannan Sadhasivam @ 2023-10-11 4:43 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Geert Uytterhoeven, Serge Semin,
Conor Dooley
On Wed, Oct 11, 2023 at 12:54:59AM +0000, Yoshihiro Shimoda wrote:
> Hello Manivannan,
>
> > From: Manivannan Sadhasivam, Sent: Tuesday, October 10, 2023 8:25 PM
> > To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > Cc: lpieralisi@kernel.org; kw@linux.com; robh@kernel.org; bhelgaas@google.com; krzysztof.kozlowski+dt@linaro.org;
> > conor+dt@kernel.org; jingoohan1@gmail.com; gustavo.pimentel@synopsys.com; marek.vasut+renesas@gmail.com;
> > linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-renesas-soc@vger.kernel.org; Geert Uytterhoeven
> > <geert+renesas@glider.be>; Serge Semin <fancer.lancer@gmail.com>; Conor Dooley <conor.dooley@microchip.com>
> > Subject: Re: [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host
> >
> > On Fri, Sep 22, 2023 at 03:53:25PM +0900, Yoshihiro Shimoda wrote:
> > > Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0)
> > > PCIe host module.
> > >
> > > Link:
> <snip URL>
> > > Link:
> <snip URL>
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > > ---
> > > .../bindings/pci/rcar-gen4-pci-host.yaml | 127 ++++++++++++++++++
> > > 1 file changed, 127 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> > b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
> > > new file mode 100644
> > > index 000000000000..ffb34339b637
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml
[...]
> > > + #interrupt-cells = <1>;
> > > + interrupt-map-mask = <0 0 0 7>;
> > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > > + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > > + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> > > + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
> >
> > I believe these are for legacy INTx interrupts. But you are using the same IRQ
> > number used for MSI above. Can you clarify?
>
> On the SoC (R-Car S4-8), the same IRQ number is used for both MSI and legacy INTx
> interrupts...
>
Ok. This seems wierd, but fine with me.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
* RE: [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support
2023-10-11 4:41 ` Manivannan Sadhasivam
@ 2023-10-11 5:06 ` Yoshihiro Shimoda
0 siblings, 0 replies; 34+ messages in thread
From: Yoshihiro Shimoda @ 2023-10-11 5:06 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: lpieralisi, kw, robh, bhelgaas, krzysztof.kozlowski+dt, conor+dt,
jingoohan1, gustavo.pimentel, marek.vasut+renesas, linux-pci,
devicetree, linux-renesas-soc, Serge Semin
Hello Manivannan,
> From: Manivannan Sadhasivam, Sent: Wednesday, October 11, 2023 1:42 PM
> On Wed, Oct 11, 2023 at 01:18:11AM +0000, Yoshihiro Shimoda wrote:
> > Hello Manivannan,
> >
> > > From: Manivannan Sadhasivam, Sent: Tuesday, October 10, 2023 9:04 PM
> > >
> > > On Fri, Sep 22, 2023 at 03:53:28PM +0900, Yoshihiro Shimoda wrote:
> > > > Add R-Car Gen4 PCIe controller support for host mode.
> > > >
> > > > This controller is based on Synopsys DesignWare PCIe. However, this
> > > > particular controller has a number of vendor-specific registers, and as
> > > > such, requires initialization code like mode setting and retraining and
> > > > so on.
> > > >
> > > > [kwilczynski: commit log]
> > > > Link:
> > <snip URL>
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > > > Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
> > > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > > ---
> > > > drivers/pci/controller/dwc/Kconfig | 14 +
> > > > drivers/pci/controller/dwc/Makefile | 1 +
> > > > drivers/pci/controller/dwc/pcie-rcar-gen4.c | 380 ++++++++++++++++++++
> > > > 3 files changed, 395 insertions(+)
> > > > create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> > > > index ab96da43e0c2..bc69fcab2e2a 100644
> > > > --- a/drivers/pci/controller/dwc/Kconfig
> > > > +++ b/drivers/pci/controller/dwc/Kconfig
> > > > @@ -415,4 +415,18 @@ config PCIE_VISCONTI_HOST
> > > > Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
> > > > This driver supports TMPV7708 SoC.
> > > >
> > > > +config PCIE_RCAR_GEN4
> > > > + tristate
> > > > +
> > > > +config PCIE_RCAR_GEN4_HOST
> > > > + tristate "Renesas R-Car Gen4 PCIe controller (host mode)"
> > > > + depends on ARCH_RENESAS || COMPILE_TEST
> > > > + depends on PCI_MSI
> > > > + select PCIE_DW_HOST
> > > > + select PCIE_RCAR_GEN4
> > > > + help
> > > > + Say Y here if you want PCIe controller (host mode) on R-Car Gen4 SoCs.
> > > > + To compile this driver as a module, choose M here: the module will be
> > > > + called pcie-rcar-gen4.ko. This uses the DesignWare core.
> > > > +
> > > > endmenu
> > > > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> > > > index bf5c311875a1..bac103faa523 100644
> > > > --- a/drivers/pci/controller/dwc/Makefile
> > > > +++ b/drivers/pci/controller/dwc/Makefile
> > > > @@ -26,6 +26,7 @@ obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o
> > > > obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
> > > > obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o
> > > > obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o
> > > > +obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
> > > >
> > > > # The following drivers are for devices that use the generic ACPI
> > > > # pci_root.c driver but don't support standard ECAM config access.
> > > > diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> > > > new file mode 100644
> > > > index 000000000000..dfff6bb18932
> > > > --- /dev/null
> > > > +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
>
> [...]
>
> > > > +/* Host mode */
> > > > +static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
> > > > +{
> > > > + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
> > > > + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
> > > > + int ret;
> > > > + u32 val;
> > > > +
> > > > + gpiod_set_value_cansleep(dw->pe_rst, 1);
> > > > +
> > > > + ret = rcar_gen4_pcie_common_init(rcar);
> > > > + if (ret)
> > > > + return ret;
> > > > +
> > > > + /*
> > > > + * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
> > > > + * Rev.5.20a, we should disable two BARs to avoid unnecessary memory
> > > > + * assignment during device enumeration.
> > > > + */
> > > > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
> > > > + dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
> > >
> > > If this is DWC specific, can we move it to the common code?
> >
> > Hmm, it seems so. However, I didn't find any similar code on other DWC drivers.
> > So, for now, moving it to the common code is not needed, I think.
> >
>
> No. If this is as per the DWC spec, then it should be part of the common code.
I got it. I'll add such a code by a separate patch.
> > > > +
> > > > + /* Enable MSI interrupt signal */
> > > > + val = readl(rcar->base + PCIEINTSTS0EN);
> > > > + val |= MSI_CTRL_INT;
> > > > + writel(val, rcar->base + PCIEINTSTS0EN);
> > > > +
> > >
> > > Above should be guarded with:
> > >
> > > if (IS_ENABLED(CONFIG_PCI_MSI)) {
> > > ...
> > > }
> >
> > Since this driver depends on PCI_MSI by Kconfig, such a IS_ENABLED is not
> > needed. This is from your suggestion ;) [2]
> >
> > [2] https://lore.kernel.org/linux-devicetree/20230724122820.GM6291@thinkpad/
>
> heh... thanks for reminding me ;)
You're welcome :)
Thank you very much for your support!
Best regards,
Yoshihiro Shimoda
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2023-10-11 5:06 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-22 6:53 [PATCH v21 00/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe support Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 01/16] PCI: dwc: endpoint: Add multiple PFs support for dbi2 Yoshihiro Shimoda
2023-10-10 11:12 ` Manivannan Sadhasivam
2023-10-11 0:46 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 02/16] PCI: dwc: Add dw_pcie_link_set_max_link_width() Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 03/16] PCI: dwc: Add missing PCI_EXP_LNKCAP_MLW handling Yoshihiro Shimoda
2023-10-10 11:14 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 04/16] PCI: tegra194: Drop PCI_EXP_LNKSTA_NLW setting Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 05/16] PCI: dwc: Add EDMA_UNROLL capability flag Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 06/16] PCI: dwc: Expose dw_pcie_ep_exit() to module Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 07/16] PCI: dwc: Expose dw_pcie_write_dbi2() " Yoshihiro Shimoda
2023-10-10 11:15 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 08/16] PCI: dwc: endpoint: Introduce .pre_init() and .deinit() Yoshihiro Shimoda
2023-10-10 11:17 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 09/16] dt-bindings: PCI: dwc: Update maxItems of reg and reg-names Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 10/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Yoshihiro Shimoda
2023-10-10 11:25 ` Manivannan Sadhasivam
2023-10-11 0:54 ` Yoshihiro Shimoda
2023-10-11 4:43 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 11/16] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Endpoint Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 12/16] PCI: add T_PVPERL macro Yoshihiro Shimoda
2023-10-10 11:30 ` Manivannan Sadhasivam
2023-10-11 0:56 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 13/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe controller support Yoshihiro Shimoda
2023-09-22 13:47 ` kernel test robot
2023-09-25 6:54 ` Yoshihiro Shimoda
2023-10-10 12:04 ` Manivannan Sadhasivam
2023-10-11 1:18 ` Yoshihiro Shimoda
2023-10-11 4:41 ` Manivannan Sadhasivam
2023-10-11 5:06 ` Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 14/16] PCI: dwc: rcar-gen4: Add R-Car Gen4 PCIe Endpoint support Yoshihiro Shimoda
2023-10-10 12:06 ` Manivannan Sadhasivam
2023-09-22 6:53 ` [PATCH v21 15/16] MAINTAINERS: Update PCI DRIVER FOR RENESAS R-CAR for R-Car Gen4 Yoshihiro Shimoda
2023-09-22 6:53 ` [PATCH v21 16/16] misc: pci_endpoint_test: Add Device ID for R-Car S4-8 PCIe controller Yoshihiro Shimoda
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