* [PATCH 0/2] arm64: dts: renesas: r8a779f0: Add PCIe support
@ 2023-04-14 7:27 Yoshihiro Shimoda
2023-04-14 7:27 ` [PATCH 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2023-04-14 7:27 ` [PATCH 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
0 siblings, 2 replies; 4+ messages in thread
From: Yoshihiro Shimoda @ 2023-04-14 7:27 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Add PCIe support for R-Car S4-8 (r8a779f0). The dt-bindings doc
patches are under review now:
https://patchwork.kernel.org/project/linux-pci/list/?series=739719
Yoshihiro Shimoda (2):
arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes
arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0
.../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 19 ++++
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 104 ++++++++++++++++++
2 files changed, 123 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes
2023-04-14 7:27 [PATCH 0/2] arm64: dts: renesas: r8a779f0: Add PCIe support Yoshihiro Shimoda
@ 2023-04-14 7:27 ` Yoshihiro Shimoda
2023-04-18 11:37 ` Yoshihiro Shimoda
2023-04-14 7:27 ` [PATCH 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
1 sibling, 1 reply; 4+ messages in thread
From: Yoshihiro Shimoda @ 2023-04-14 7:27 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Add PCIe Host and Endpoint nodes for R-Car S4-8 (R8A779F0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 104 ++++++++++++++++++++++
1 file changed, 104 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 1d5426e6293c..b3fe7e0599c3 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -711,6 +711,110 @@ hscif3: serial@e66a0000 {
status = "disabled";
};
+ pciec0: pcie@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie",
+ "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x1100>, <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "sft_ce", "app";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 624>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ num-lanes = <2>;
+ snps,enable-cdm-check;
+ max-link-speed = <4>;
+ status = "disabled";
+ };
+
+ pciec1: pcie@e65d8000 {
+ compatible = "renesas,r8a779f0-pcie",
+ "renesas,rcar-gen4-pcie";
+ reg = <0 0xe65d8000 0 0x1000>, <0 0xe65d8200 0 0x0800>,
+ <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
+ <0 0xe65de200 0 0x1100>, <0 0xee900000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x00 0xff>;
+ device_type = "pci";
+ ranges = <0x82000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "dma", "sft_ce", "app";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ num-lanes = <2>;
+ snps,enable-cdm-check;
+ max-link-speed = <4>;
+ status = "disabled";
+ };
+
+ pciec0_ep: pcie-ep@e65d0000 {
+ compatible = "renesas,r8a779f0-pcie-ep",
+ "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2800 0 0x800>,
+ <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+ <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space";
+ interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 624>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 624>;
+ num-lanes = <2>;
+ max-link-speed = <4>;
+ status = "disabled";
+ };
+
+ pciec1_ep: pcie-ep@e65d8000 {
+ compatible = "renesas,r8a779f0-pcie-ep",
+ "renesas,rcar-gen4-pcie-ep";
+ reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da800 0 0x0800>,
+ <0 0xe65dd000 0 0x1200>, <0 0xe65de200 0 0x0e00>,
+ <0 0xee900000 0 0x400000>;
+ reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space";
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma", "sft_ce", "app";
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ num-lanes = <2>;
+ max-link-speed = <4>;
+ status = "disabled";
+ };
+
ufs: ufs@e6860000 {
compatible = "renesas,r8a779f0-ufs";
reg = <0 0xe6860000 0 0x100>;
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0
2023-04-14 7:27 [PATCH 0/2] arm64: dts: renesas: r8a779f0: Add PCIe support Yoshihiro Shimoda
2023-04-14 7:27 ` [PATCH 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
@ 2023-04-14 7:27 ` Yoshihiro Shimoda
1 sibling, 0 replies; 4+ messages in thread
From: Yoshihiro Shimoda @ 2023-04-14 7:27 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc, Yoshihiro Shimoda
Enable PCIe Host controller channel 0 on R-Car S4-8 Spider board.
Since this board has an Oculink connector, CLKREQ# pin of PFC for PCIe
should not be used. So, using a GPIO is used to output the clock instead.
Otherwise the controller cannot detect a PCIe device.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
.../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index dd8e0e159526..12f2a1db4fb7 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -66,6 +66,14 @@ &extalr_clk {
clock-frequency = <32768>;
};
+&gpio2 {
+ pci-clkreq0-hog {
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_LOW>;
+ output-high;
+ };
+};
+
&hscif0 {
pinctrl-0 = <&hscif0_pins>;
pinctrl-names = "default";
@@ -86,6 +94,12 @@ gpio_exp_20: gpio@20 {
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
+
+ rc21012-gpio2-hog {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ output-high;
+ };
};
};
@@ -125,6 +139,11 @@ &mmc0 {
status = "okay";
};
+&pciec0 {
+ reset-gpio = <&gpio_exp_20 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
--
2.25.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* RE: [PATCH 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes
2023-04-14 7:27 ` [PATCH 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
@ 2023-04-18 11:37 ` Yoshihiro Shimoda
0 siblings, 0 replies; 4+ messages in thread
From: Yoshihiro Shimoda @ 2023-04-18 11:37 UTC (permalink / raw)
To: geert+renesas, magnus.damm; +Cc: linux-renesas-soc
Hi Geert-san,
> From: Yoshihiro Shimoda, Sent: Friday, April 14, 2023 4:27 PM
>
> Add PCIe Host and Endpoint nodes for R-Car S4-8 (R8A779F0).
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 104 ++++++++++++++++++++++
> 1 file changed, 104 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> index 1d5426e6293c..b3fe7e0599c3 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> @@ -711,6 +711,110 @@ hscif3: serial@e66a0000 {
> status = "disabled";
> };
>
> + pciec0: pcie@e65d0000 {
> + compatible = "renesas,r8a779f0-pcie",
> + "renesas,rcar-gen4-pcie";
> + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
> + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
> + <0 0xe65d6200 0 0x1100>, <0 0xfe000000 0 0x400000>;
> + reg-names = "dbi", "dbi2", "atu", "dma", "app", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x00 0xff>;
> + device_type = "pci";
> + ranges = <0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>;
> + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
> + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi", "dma", "sft_ce", "app";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 624>;
> + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> + resets = <&cpg 624>;
> + num-lanes = <2>;
> + snps,enable-cdm-check;
> + max-link-speed = <4>;
> + status = "disabled";
> + };
> +
> + pciec1: pcie@e65d8000 {
> + compatible = "renesas,r8a779f0-pcie",
> + "renesas,rcar-gen4-pcie";
> + reg = <0 0xe65d8000 0 0x1000>, <0 0xe65d8200 0 0x0800>,
I realized that the second "dbi2" address should be 0xe65da000, not 0xe65d8200.
> + <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
> + <0 0xe65de200 0 0x1100>, <0 0xee900000 0 0x400000>;
> + reg-names = "dbi", "dbi2", "atu", "dma", "app", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x00 0xff>;
> + device_type = "pci";
> + ranges = <0x82000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
> + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
> + interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi", "dma", "sft_ce", "app";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 625>;
> + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> + resets = <&cpg 625>;
> + num-lanes = <2>;
> + snps,enable-cdm-check;
> + max-link-speed = <4>;
> + status = "disabled";
> + };
> +
> + pciec0_ep: pcie-ep@e65d0000 {
> + compatible = "renesas,r8a779f0-pcie-ep",
> + "renesas,rcar-gen4-pcie-ep";
> + reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2800 0 0x800>,
> + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
> + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>;
> + reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space";
> + interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "dma", "sft_ce", "app";
> + clocks = <&cpg CPG_MOD 624>;
> + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> + resets = <&cpg 624>;
> + num-lanes = <2>;
> + max-link-speed = <4>;
> + status = "disabled";
> + };
> +
> + pciec1_ep: pcie-ep@e65d8000 {
> + compatible = "renesas,r8a779f0-pcie-ep",
> + "renesas,rcar-gen4-pcie-ep";
> + reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da800 0 0x0800>,
> + <0 0xe65dd000 0 0x1200>, <0 0xe65de200 0 0x0e00>,
> + <0 0xee900000 0 0x400000>;
I realized that missing the "dbi2" resource on the reg.
I'll fix them on v2.
Best regards,
Yoshihiro Shimoda
> + reg-names = "dbi", "dbi2", "atu", "dma", "app", "addr_space";
> + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "dma", "sft_ce", "app";
> + clocks = <&cpg CPG_MOD 625>;
> + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
> + resets = <&cpg 625>;
> + num-lanes = <2>;
> + max-link-speed = <4>;
> + status = "disabled";
> + };
> +
> ufs: ufs@e6860000 {
> compatible = "renesas,r8a779f0-ufs";
> reg = <0 0xe6860000 0 0x100>;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-04-18 11:38 UTC | newest]
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2023-04-14 7:27 [PATCH 0/2] arm64: dts: renesas: r8a779f0: Add PCIe support Yoshihiro Shimoda
2023-04-14 7:27 ` [PATCH 1/2] arm64: dts: renesas: r8a779f0: Add PCIe Host and Endpoint nodes Yoshihiro Shimoda
2023-04-18 11:37 ` Yoshihiro Shimoda
2023-04-14 7:27 ` [PATCH 2/2] arm64: dts: renesas: r8a779f0: spider: Enable PCIe Host ch0 Yoshihiro Shimoda
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