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From: Chris Paterson <Chris.Paterson2@renesas.com>
To: "Conor.Dooley@microchip.com" <Conor.Dooley@microchip.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>
Cc: "atishp@rivosinc.com" <atishp@rivosinc.com>,
	"apatel@ventanamicro.com" <apatel@ventanamicro.com>,
	"geert+renesas@glider.be" <geert+renesas@glider.be>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-renesas-soc@vger.kernel.org" 
	<linux-renesas-soc@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"prabhakar.csengg@gmail.com" <prabhakar.csengg@gmail.com>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: RE: [RFC PATCH 1/2] riscv: vendors: andes: Add support to configure the PMA regions
Date: Wed, 7 Sep 2022 08:18:31 +0000	[thread overview]
Message-ID: <TYCPR01MB1058865290D9F2ACFE99086DEB7419@TYCPR01MB10588.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <8ecb62b7-53c4-1c43-65b3-567d8c12e131@microchip.com>

Hello Conor,

Thank you for your interest.

> From: Conor.Dooley@microchip.com <Conor.Dooley@microchip.com>
> Sent: 06 September 2022 11:39
> 
> On 06/09/2022 11:21, Lad Prabhakar wrote:
> 
> > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> > index 2a0ef738695e..10a7c855d125 100644
> > --- a/arch/riscv/include/asm/sbi.h
> > +++ b/arch/riscv/include/asm/sbi.h
> > @@ -37,6 +37,7 @@ enum sbi_ext_id {
> >
> >          /* Vendor extensions must lie within this range */
> >          SBI_EXT_VENDOR_START = 0x09000000,
> > +       SBI_EXT_ANDES = 0x0900031E,
> >          SBI_EXT_VENDOR_END = 0x09FFFFFF,
> >   };
> 
> Everything else aside, I am very interested in what's happening
> here. I'll take a proper look through things later, but for now:
> 
> For PolarFire SoC we have an InterHart Communication SBI EXT that
> would would like to upstream support for. We are not aiming to put
> the driver itself in arch/riscv - it's just a mailbox driver, but
> I would like to use sbi.h for defining the vendor id etc.
> 
> I am not sure how this all aligns with:
> > We’ll only accept patches for new modules or extensions if the
> > specifications for those modules or extensions are listed as being
> > “Frozen” or “Ratified” by the RISC-V Foundation. (Developers may, of
> > course, maintain their own Linux kernel trees that contain code for
> > any draft extensions that they wish.)
> >
> > Additionally, the RISC-V specification allows implementors to create
> > their own custom extensions. These custom extensions aren’t required
> > to go through any review or ratification process by the RISC-V
> > Foundation. To avoid the maintenance complexity and potential
> > performance impact of adding kernel code for implementor-specific
> > RISC-V extensions, we’ll only to accept patches for extensions that
> > have been officially frozen or ratified by the RISC-V Foundation.
> > (Implementors, may, of course, maintain their own Linux kernel trees
> > containing code for any custom extensions that they wish.)
> 
> Which is in: https://docs.kernel.org/riscv/patch-acceptance.html
> 
> It is unclear to me whether that is just for ISA extensions or if that
> covers SBI extensions too. At least for us, since we don't touch arch
> code there is relatively little friction & there's no concerns about
> reducing the portability of a kernel since it is just a regular old
> driver.
> 
> I was planning on cornering some people *cough* Palmer *cough* at
> LPC and asking him what his thoughts were there.
> 
> FWIW this is what we have been doing:
> https://github.com/linux4microchip/linux/blob/linux-5.15-mchp/drivers/mailbox/mailbox-miv-ihc.c#L27
> 
> The IP itself has not stabilised yet, so we have not sent any patches
> yet, but we do intend doing so...
> 
> But yea, I'll take a properly look at what you're doing here soonTM,
> although at this point it may be the other side of LPC.
> 
> btw, where can I get my hands on your hardware?

The latest information I have is that it should be available via various distributors on the 21st Sept.

Kind regards, Chris

> 
> Thanks,
> Conor.
> 


  parent reply	other threads:[~2022-09-07  8:18 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-06 10:21 [RFC PATCH 0/2] AX45MP: Add support to non-coherent DMA Lad Prabhakar
2022-09-06 10:21 ` [RFC PATCH 1/2] riscv: vendors: andes: Add support to configure the PMA regions Lad Prabhakar
2022-09-06 10:39   ` Conor.Dooley
2022-09-06 11:23     ` Lad, Prabhakar
2022-09-07  8:18     ` Chris Paterson [this message]
2022-09-22 15:00       ` Chris Paterson
     [not found]     ` <CAOnJCUKLpRz4Fbx1XiMnap-ELw2k1c8E9V8bZiSP+x7z9Z5QrA@mail.gmail.com>
2022-09-07 23:37       ` Conor.Dooley
2022-09-08  8:39         ` Biju Das
2022-09-08 11:50           ` Lad, Prabhakar
2022-09-08 11:59             ` Conor.Dooley
2022-09-08 12:13               ` Lad, Prabhakar
2022-09-08 12:43           ` Conor.Dooley
2022-09-08 13:01             ` Biju Das
2022-09-08 13:20               ` Geert Uytterhoeven
2022-09-08 13:54                 ` Biju Das
2022-09-08 14:04               ` Conor.Dooley
2022-09-08 14:39                 ` Lad, Prabhakar
2022-09-06 10:21 ` [RFC PATCH 2/2] riscv: vendors: andes: Add support for non-cohernet dma Lad Prabhakar
2022-09-08 21:44 ` [RFC PATCH 0/2] AX45MP: Add support to non-coherent DMA Conor.Dooley
2022-09-09 10:21   ` Lad, Prabhakar
2022-09-09 23:06   ` Atish Patra

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