From: Biju Das <biju.das.jz@bp.renesas.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Subject: RE: [PATCH 2/6] drivers: clk: renesas: r9a07g044-cpg: Add USB clocks
Date: Wed, 16 Jun 2021 10:12:49 +0000 [thread overview]
Message-ID: <TYCPR01MB593339B3D580336CE2FB5BAC860F9@TYCPR01MB5933.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CAMuHMdV=AcCgwJqiEoUyK9cDnyT-arOVSNFS5Z1xxXQ7PeZzkg@mail.gmail.com>
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 2/6] drivers: clk: renesas: r9a07g044-cpg: Add USB
> clocks
>
> Hi Biju,
>
> On Mon, Jun 14, 2021 at 2:26 PM Geert Uytterhoeven <geert@linux-m68k.org>
> wrote:
> > On Fri, Jun 11, 2021 at 3:46 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > Add clock entries for USB{0,1}.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/clk/renesas/r9a07g044-cpg.c
> > > +++ b/drivers/clk/renesas/r9a07g044-cpg.c
> > > @@ -88,6 +88,12 @@ static struct rzg2l_mod_clk r9a07g044_mod_clks[] =
> {
> > > DEF_MOD("dmac", R9A07G044_CLK_DMAC,
> > > R9A07G044_CLK_P1,
> > > 0x52c, (BIT(0) | BIT(1)), (BIT(0) |
> > > BIT(1))),
> > > + DEF_MOD("usb0", R9A07G044_CLK_USB0,
> > > + R9A07G044_CLK_P1,
> > > + 0x578, (BIT(0) | BIT(2) | BIT(3)),
> (BIT(0) | BIT(2) | BIT(3))),
> > > + DEF_MOD("usb1", R9A07G044_CLK_USB1,
> > > + R9A07G044_CLK_P1,
> > > + 0x578, (BIT(1) | BIT(3)), (BIT(1) |
> > > + BIT(3))),
> > > DEF_MOD("scif0", R9A07G044_CLK_SCIF0,
> > > R9A07G044_CLK_P0,
> > > 0x584, BIT(0), BIT(0)),
> >
> > While the above matches the datasheet, I see a problem with the
> > implementation. As BIT(3) of the CPG_{CLKON,CLKMON,RST}_USB is shared
> > by the two USB2.0 channels, disabling USB_PCLK or asserting
> > USB_PRESETN will affect both channels. So it looks like you need
> > special handling to make sure that doesn't happen while the other
> channel is in use.
> >
> > Or am I missing something?
>
> I'm getting the impression we do have to model the individual bits as
> separate clocks (and resets). That would solve the problem with the
> shared USB_PCLK, as the clock framework will take care of keeping it
> enabled when at least one channel is in use.
>
> Besides USB, SDHI has 4 clock bits, which we definitely don't want to
> control together, as the card detect clock must not be stopped while
> suspended.
> However, the exception to the rule is Ethernet: each channel has
> 2 clocks, but only a single bit to control, so this needs a custom single-
> gate-for-dual-clock driver.
>
> Perhaps merging the clock binding definitions and initial driver for
> v5.14 was a bit premature...
> Anyway, we'll have 6 rcs after v5.14-rc1 to get it right ;-)
>
> What do you think?
I am ok with this approach for USB, SDHI and Ethernet.
Regards,
Biju
next prev parent reply other threads:[~2021-06-16 10:12 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-11 13:46 [PATCH 0/6] Add RZ/G2L USB2.0 phy and host support Biju Das
2021-06-11 13:46 ` [PATCH 1/6] dt-bindings: phy: renesas: Document RZ/G2L USB PHY Control bindings Biju Das
2021-06-21 4:01 ` Vinod Koul
2021-06-21 6:40 ` Biju Das
2021-06-11 13:46 ` [PATCH 2/6] drivers: clk: renesas: r9a07g044-cpg: Add USB clocks Biju Das
2021-06-14 12:26 ` Geert Uytterhoeven
2021-06-15 8:58 ` Geert Uytterhoeven
2021-06-15 9:48 ` Laurent Pinchart
2021-06-15 9:53 ` Geert Uytterhoeven
2021-06-15 9:57 ` Laurent Pinchart
2021-06-15 10:24 ` Geert Uytterhoeven
2021-06-16 10:16 ` Biju Das
2021-06-16 11:33 ` Laurent Pinchart
2021-06-16 10:12 ` Biju Das [this message]
2021-06-11 13:46 ` [PATCH 3/6] phy: renesas: Add RZ/G2L usb phy control driver Biju Das
2021-06-21 4:13 ` Vinod Koul
2021-06-21 6:51 ` Biju Das
2021-06-11 13:46 ` [PATCH 4/6] arm64: configs: defconfig: Enable RZ/G2L USB PHY " Biju Das
2021-06-11 13:46 ` [PATCH 5/6] dt-bindings: phy: renesas,usb2-phy: Document RZ/G2L phy bindings Biju Das
2021-06-11 13:46 ` [PATCH 6/6] arm64: dts: renesas: r9a07g044: Add USB2.0 phy and host support Biju Das
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