* [PATCH v2 0/3] arm64: dts: renesas: r8a779a0 DU support
@ 2021-09-01 23:53 Kieran Bingham
2021-09-01 23:53 ` [PATCH v2 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Kieran Bingham @ 2021-09-01 23:53 UTC (permalink / raw)
To: Laurent Pinchart, Geert Uytterhoeven, linux-renesas-soc; +Cc: Kieran Bingham
Provide the DT nodes for the DU, and DSI found on the r8a779a0, and
extend the falcon-cpu board add on with the TI SN65DSI86 bridge which is
used to connect the DSI output to the mini display-port connector on the
Falcon CPU board.
Kieran Bingham (3):
arm64: dts: renesas: r8a779a0: Add DU support
arm64: dts: renesas: r8a779a0: Add DSI encoders
arm64: dts: renesas: falcon-cpu: Add DSI display output
.../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 84 +++++++++++++++++
arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 90 +++++++++++++++++++
2 files changed, 174 insertions(+)
--
2.30.2
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v2 1/3] arm64: dts: renesas: r8a779a0: Add DU support 2021-09-01 23:53 [PATCH v2 0/3] arm64: dts: renesas: r8a779a0 DU support Kieran Bingham @ 2021-09-01 23:53 ` Kieran Bingham 2021-09-22 23:32 ` Laurent Pinchart 2021-09-01 23:53 ` [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham 2021-09-01 23:53 ` [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Kieran Bingham 2 siblings, 1 reply; 10+ messages in thread From: Kieran Bingham @ 2021-09-01 23:53 UTC (permalink / raw) To: Laurent Pinchart, Geert Uytterhoeven, linux-renesas-soc Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Provide the device nodes for the DU on the V3U platforms. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> --- v2 - Use a single clock specification for the whole DU. arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 631d520cebee..3241f7e7c01e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1142,6 +1142,36 @@ vspd1: vsp@fea28000 { renesas,fcp = <&fcpvd1>; }; + du: display@feb00000 { + compatible = "renesas,du-r8a779a0"; + reg = <0 0xfeb00000 0 0x40000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 411>; + clock-names = "du"; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 411>; + vsps = <&vspd0 0>, <&vspd1 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_dsi0: endpoint { + }; + }; + + port@1 { + reg = <1>; + du_out_dsi1: endpoint { + }; + }; + }; + }; + prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; -- 2.30.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/3] arm64: dts: renesas: r8a779a0: Add DU support 2021-09-01 23:53 ` [PATCH v2 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham @ 2021-09-22 23:32 ` Laurent Pinchart 0 siblings, 0 replies; 10+ messages in thread From: Laurent Pinchart @ 2021-09-22 23:32 UTC (permalink / raw) To: Kieran Bingham Cc: Geert Uytterhoeven, linux-renesas-soc, Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi Kieran, Thank you for the patch. On Thu, Sep 02, 2021 at 12:53:28AM +0100, Kieran Bingham wrote: > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > Provide the device nodes for the DU on the V3U platforms. > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > --- > v2 > - Use a single clock specification for the whole DU. > > arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 30 +++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > index 631d520cebee..3241f7e7c01e 100644 > --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > @@ -1142,6 +1142,36 @@ vspd1: vsp@fea28000 { > renesas,fcp = <&fcpvd1>; > }; > > + du: display@feb00000 { > + compatible = "renesas,du-r8a779a0"; > + reg = <0 0xfeb00000 0 0x40000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 411>; > + clock-names = "du"; With the clock name set to "du.0" as discussed in the DT bindings review, Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + resets = <&cpg 411>; > + vsps = <&vspd0 0>, <&vspd1 0>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + du_out_dsi0: endpoint { > + }; > + }; > + > + port@1 { > + reg = <1>; > + du_out_dsi1: endpoint { > + }; > + }; > + }; > + }; > + > prr: chipid@fff00044 { > compatible = "renesas,prr"; > reg = <0 0xfff00044 0 4>; -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders 2021-09-01 23:53 [PATCH v2 0/3] arm64: dts: renesas: r8a779a0 DU support Kieran Bingham 2021-09-01 23:53 ` [PATCH v2 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham @ 2021-09-01 23:53 ` Kieran Bingham 2021-09-21 15:52 ` Geert Uytterhoeven 2021-09-22 23:34 ` Laurent Pinchart 2021-09-01 23:53 ` [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Kieran Bingham 2 siblings, 2 replies; 10+ messages in thread From: Kieran Bingham @ 2021-09-01 23:53 UTC (permalink / raw) To: Laurent Pinchart, Geert Uytterhoeven, linux-renesas-soc Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Provide the two MIPI DSI encoders on the V3U and connect them to the DU accordingly. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> --- v2 - Fixup indentation arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 3241f7e7c01e..1ce9884ea527 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1161,12 +1161,72 @@ ports { port@0 { reg = <0>; du_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in>; }; }; port@1 { reg = <1>; du_out_dsi1: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; + + dsi0: dsi-encoder@fed80000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed80000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>; + clock-names = "fck", "dsi"; + resets = <&cpg 415>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&du_out_dsi0>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + }; + + dsi1: dsi-encoder@fed90000 { + compatible = "renesas,r8a779a0-dsi-csi2-tx"; + reg = <0 0xfed90000 0 0x10000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + clocks = <&cpg CPG_MOD 416>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>; + clock-names = "fck", "dsi"; + resets = <&cpg 416>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&du_out_dsi1>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { }; }; }; -- 2.30.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders 2021-09-01 23:53 ` [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham @ 2021-09-21 15:52 ` Geert Uytterhoeven 2021-09-22 23:34 ` Laurent Pinchart 1 sibling, 0 replies; 10+ messages in thread From: Geert Uytterhoeven @ 2021-09-21 15:52 UTC (permalink / raw) To: Kieran Bingham Cc: Laurent Pinchart, Linux-Renesas, Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi Kieran, On Thu, Sep 2, 2021 at 1:53 AM Kieran Bingham <kieran.bingham@ideasonboard.com> wrote: > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > Provide the two MIPI DSI encoders on the V3U and connect them to the DU > accordingly. > > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > @@ -1161,12 +1161,72 @@ ports { > port@0 { > reg = <0>; > du_out_dsi0: endpoint { > + remote-endpoint = <&dsi0_in>; > }; > }; > > port@1 { > reg = <1>; > du_out_dsi1: endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi-encoder@fed80000 { > + compatible = "renesas,r8a779a0-dsi-csi2-tx"; > + reg = <0 0xfed80000 0 0x10000>; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + clocks = <&cpg CPG_MOD 415>, > + <&cpg CPG_CORE R8A779A0_CLK_DSI>; > + clock-names = "fck", "dsi"; The last posted binding says you need 3 clocks? No interrupts (yes, they're not in the bindings either)? The rest looks good to me. > + resets = <&cpg 415>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&du_out_dsi0>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders 2021-09-01 23:53 ` [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham 2021-09-21 15:52 ` Geert Uytterhoeven @ 2021-09-22 23:34 ` Laurent Pinchart 1 sibling, 0 replies; 10+ messages in thread From: Laurent Pinchart @ 2021-09-22 23:34 UTC (permalink / raw) To: Kieran Bingham Cc: Geert Uytterhoeven, linux-renesas-soc, Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi Kieran, Thank you for the patch. On Thu, Sep 02, 2021 at 12:53:29AM +0100, Kieran Bingham wrote: > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > Provide the two MIPI DSI encoders on the V3U and connect them to the DU > accordingly. > > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > > --- > v2 > - Fixup indentation > > arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 60 +++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > index 3241f7e7c01e..1ce9884ea527 100644 > --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi > @@ -1161,12 +1161,72 @@ ports { > port@0 { > reg = <0>; > du_out_dsi0: endpoint { > + remote-endpoint = <&dsi0_in>; > }; > }; > > port@1 { > reg = <1>; > du_out_dsi1: endpoint { > + remote-endpoint = <&dsi1_in>; > + }; > + }; > + }; > + }; > + > + dsi0: dsi-encoder@fed80000 { > + compatible = "renesas,r8a779a0-dsi-csi2-tx"; > + reg = <0 0xfed80000 0 0x10000>; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + clocks = <&cpg CPG_MOD 415>, > + <&cpg CPG_CORE R8A779A0_CLK_DSI>; > + clock-names = "fck", "dsi"; > + resets = <&cpg 415>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi0_in: endpoint { > + remote-endpoint = <&du_out_dsi0>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi0_out: endpoint { > + }; > + }; > + }; > + }; > + > + dsi1: dsi-encoder@fed90000 { > + compatible = "renesas,r8a779a0-dsi-csi2-tx"; > + reg = <0 0xfed90000 0 0x10000>; > + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; > + clocks = <&cpg CPG_MOD 416>, > + <&cpg CPG_CORE R8A779A0_CLK_DSI>; > + clock-names = "fck", "dsi"; > + resets = <&cpg 416>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dsi1_in: endpoint { > + remote-endpoint = <&du_out_dsi1>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi1_out: endpoint { > }; > }; > }; -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output 2021-09-01 23:53 [PATCH v2 0/3] arm64: dts: renesas: r8a779a0 DU support Kieran Bingham 2021-09-01 23:53 ` [PATCH v2 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham 2021-09-01 23:53 ` [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham @ 2021-09-01 23:53 ` Kieran Bingham 2021-09-21 15:59 ` Geert Uytterhoeven 2021-09-22 23:56 ` Laurent Pinchart 2 siblings, 2 replies; 10+ messages in thread From: Kieran Bingham @ 2021-09-01 23:53 UTC (permalink / raw) To: Laurent Pinchart, Geert Uytterhoeven, linux-renesas-soc Cc: Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Provide the display output using the sn65dsi86 MIPI DSI bridge. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> --- .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index a0a1a1da0d87..5530bb82de6b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -66,6 +66,15 @@ memory@700000000 { reg = <0x7 0x00000000 0x0 0x80000000>; }; + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; @@ -83,6 +92,46 @@ reg_3p3v: regulator-3p3v { regulator-boot-on; regulator-always-on; }; + + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + sn65dsi86_refclk: sn65dsi86-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; +}; + +&dsi0 { + status = "okay"; + + clocks = <&cpg CPG_MOD 415>, + <&cpg CPG_CORE R8A779A0_CLK_DSI>, + <&extal_clk>; + clock-names = "fck", "dsi", "extal"; + + ports { + port@1 { + endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; }; &extal_clk { @@ -114,6 +163,41 @@ &i2c1 { status = "okay"; clock-frequency = <400000>; + + sn65dsi86@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; }; &i2c6 { -- 2.30.2 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output 2021-09-01 23:53 ` [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Kieran Bingham @ 2021-09-21 15:59 ` Geert Uytterhoeven 2021-09-22 23:40 ` Laurent Pinchart 2021-09-22 23:56 ` Laurent Pinchart 1 sibling, 1 reply; 10+ messages in thread From: Geert Uytterhoeven @ 2021-09-21 15:59 UTC (permalink / raw) To: Kieran Bingham Cc: Laurent Pinchart, Linux-Renesas, Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi Kieran, On Thu, Sep 2, 2021 at 1:53 AM Kieran Bingham <kieran.bingham@ideasonboard.com> wrote: > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > Provide the display output using the sn65dsi86 MIPI DSI bridge. > > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi > @@ -66,6 +66,15 @@ memory@700000000 { > reg = <0x7 0x00000000 0x0 0x80000000>; > }; > > + reg_1p2v: regulator-1p2v { > + compatible = "regulator-fixed"; > + regulator-name = "fixed-1.2V"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-boot-on; > + regulator-always-on; > + }; > + > reg_1p8v: regulator-1p8v { > compatible = "regulator-fixed"; > regulator-name = "fixed-1.8V"; > @@ -83,6 +92,46 @@ reg_3p3v: regulator-3p3v { > regulator-boot-on; > regulator-always-on; > }; > + > + mini-dp-con { > + compatible = "dp-connector"; > + label = "CN5"; > + type = "mini"; > + > + port { > + mini_dp_con_in: endpoint { > + remote-endpoint = <&sn65dsi86_out>; > + }; > + }; > + }; > + > + sn65dsi86_refclk: sn65dsi86-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <38400000>; > + }; > +}; > + > +&dsi0 { > + status = "okay"; > + > + clocks = <&cpg CPG_MOD 415>, > + <&cpg CPG_CORE R8A779A0_CLK_DSI>, > + <&extal_clk>; > + clock-names = "fck", "dsi", "extal"; Ah, that's where the third clock was hiding ;-) Is this hardwired to extal, or board-specific? In case of the former, I think it should be moved to the .dtsi. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output 2021-09-21 15:59 ` Geert Uytterhoeven @ 2021-09-22 23:40 ` Laurent Pinchart 0 siblings, 0 replies; 10+ messages in thread From: Laurent Pinchart @ 2021-09-22 23:40 UTC (permalink / raw) To: Geert Uytterhoeven Cc: Kieran Bingham, Linux-Renesas, Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hello, On Tue, Sep 21, 2021 at 05:59:24PM +0200, Geert Uytterhoeven wrote: > On Thu, Sep 2, 2021 at 1:53 AM Kieran Bingham wrote: > > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > > > Provide the display output using the sn65dsi86 MIPI DSI bridge. > > > > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > Thanks for your patch! > > > --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi > > @@ -66,6 +66,15 @@ memory@700000000 { > > reg = <0x7 0x00000000 0x0 0x80000000>; > > }; > > > > + reg_1p2v: regulator-1p2v { > > + compatible = "regulator-fixed"; > > + regulator-name = "fixed-1.2V"; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + regulator-boot-on; > > + regulator-always-on; > > + }; > > + > > reg_1p8v: regulator-1p8v { > > compatible = "regulator-fixed"; > > regulator-name = "fixed-1.8V"; > > @@ -83,6 +92,46 @@ reg_3p3v: regulator-3p3v { > > regulator-boot-on; > > regulator-always-on; > > }; > > + > > + mini-dp-con { > > + compatible = "dp-connector"; > > + label = "CN5"; > > + type = "mini"; > > + > > + port { > > + mini_dp_con_in: endpoint { > > + remote-endpoint = <&sn65dsi86_out>; > > + }; > > + }; > > + }; > > + > > + sn65dsi86_refclk: sn65dsi86-refclk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <38400000>; > > + }; > > +}; > > + > > +&dsi0 { > > + status = "okay"; > > + > > + clocks = <&cpg CPG_MOD 415>, > > + <&cpg CPG_CORE R8A779A0_CLK_DSI>, > > + <&extal_clk>; > > + clock-names = "fck", "dsi", "extal"; > > Ah, that's where the third clock was hiding ;-) > > Is this hardwired to extal, or board-specific? > In case of the former, I think it should be moved to the .dtsi. I think this is actually incorrect. The clock name, according to the bindings, is "pll", and it's documented as a 16.66MHz PLL reference clock. It comes from the CPG, but I'm not sure which clock it actually is. -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output 2021-09-01 23:53 ` [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Kieran Bingham 2021-09-21 15:59 ` Geert Uytterhoeven @ 2021-09-22 23:56 ` Laurent Pinchart 1 sibling, 0 replies; 10+ messages in thread From: Laurent Pinchart @ 2021-09-22 23:56 UTC (permalink / raw) To: Kieran Bingham Cc: Geert Uytterhoeven, linux-renesas-soc, Kieran Bingham, Geert Uytterhoeven, Magnus Damm, Rob Herring, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi Kieran, Thank you for the patch. On Thu, Sep 02, 2021 at 12:53:30AM +0100, Kieran Bingham wrote: > From: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > > Provide the display output using the sn65dsi86 MIPI DSI bridge. > > Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > --- > .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 84 +++++++++++++++++++ > 1 file changed, 84 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi > index a0a1a1da0d87..5530bb82de6b 100644 > --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi > @@ -66,6 +66,15 @@ memory@700000000 { > reg = <0x7 0x00000000 0x0 0x80000000>; > }; > > + reg_1p2v: regulator-1p2v { > + compatible = "regulator-fixed"; > + regulator-name = "fixed-1.2V"; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; 1.8V is a weird voltage for a 1.2V regulator :-) > + regulator-boot-on; > + regulator-always-on; > + }; > + > reg_1p8v: regulator-1p8v { > compatible = "regulator-fixed"; > regulator-name = "fixed-1.8V"; > @@ -83,6 +92,46 @@ reg_3p3v: regulator-3p3v { > regulator-boot-on; > regulator-always-on; > }; > + > + mini-dp-con { > + compatible = "dp-connector"; > + label = "CN5"; > + type = "mini"; > + > + port { > + mini_dp_con_in: endpoint { > + remote-endpoint = <&sn65dsi86_out>; > + }; > + }; > + }; > + > + sn65dsi86_refclk: sn65dsi86-refclk { I'd name the node x6-clk after the components on the board (or clk-x6). The label can stay the same, up to you. > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <38400000>; > + }; > +}; > + > +&dsi0 { > + status = "okay"; > + > + clocks = <&cpg CPG_MOD 415>, > + <&cpg CPG_CORE R8A779A0_CLK_DSI>, > + <&extal_clk>; > + clock-names = "fck", "dsi", "extal"; As discussed separately, this should go to r8a79a0.dtsi, and the last clock should be named "pll". Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > + > + ports { > + port@1 { > + endpoint { > + remote-endpoint = <&sn65dsi86_in>; > + data-lanes = <1 2 3 4>; > + }; > + }; > + }; > +}; > + > +&du { > + status = "okay"; > }; > > &extal_clk { > @@ -114,6 +163,41 @@ &i2c1 { > > status = "okay"; > clock-frequency = <400000>; > + > + sn65dsi86@2c { > + compatible = "ti,sn65dsi86"; > + reg = <0x2c>; > + > + clocks = <&sn65dsi86_refclk>; > + clock-names = "refclk"; > + > + interrupt-parent = <&gpio1>; > + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; > + > + vccio-supply = <®_1p8v>; > + vpll-supply = <®_1p8v>; > + vcca-supply = <®_1p2v>; > + vcc-supply = <®_1p2v>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + sn65dsi86_in: endpoint { > + remote-endpoint = <&dsi0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + sn65dsi86_out: endpoint { > + remote-endpoint = <&mini_dp_con_in>; > + }; > + }; > + }; > + }; > }; > > &i2c6 { -- Regards, Laurent Pinchart ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-09-22 23:56 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-01 23:53 [PATCH v2 0/3] arm64: dts: renesas: r8a779a0 DU support Kieran Bingham 2021-09-01 23:53 ` [PATCH v2 1/3] arm64: dts: renesas: r8a779a0: Add " Kieran Bingham 2021-09-22 23:32 ` Laurent Pinchart 2021-09-01 23:53 ` [PATCH v2 2/3] arm64: dts: renesas: r8a779a0: Add DSI encoders Kieran Bingham 2021-09-21 15:52 ` Geert Uytterhoeven 2021-09-22 23:34 ` Laurent Pinchart 2021-09-01 23:53 ` [PATCH v2 3/3] arm64: dts: renesas: falcon-cpu: Add DSI display output Kieran Bingham 2021-09-21 15:59 ` Geert Uytterhoeven 2021-09-22 23:40 ` Laurent Pinchart 2021-09-22 23:56 ` Laurent Pinchart
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